From 2af69dc9ab5ffd3613a59beb2f009072aeeb5357 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 11 Nov 2024 15:18:14 +0000 Subject: [PATCH] dt: arm64: Fixup RP1 ethernet DT configuration Configure RP1's ethernet block to do the correct thing. clk_eth is intended to be fixed at 125MHz, so use a new compatible, and use assigned-clocks to configure the clock appropriately. Signed-off-by: Dave Stevenson --- arch/arm64/boot/dts/broadcom/rp1.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/rp1.dtsi b/arch/arm64/boot/dts/broadcom/rp1.dtsi index cd3480ff5842f..d3a8fe2d3417e 100644 --- a/arch/arm64/boot/dts/broadcom/rp1.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1.dtsi @@ -24,6 +24,7 @@ // RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers <&rp1_clocks RP1_PLL_SYS>, <&rp1_clocks RP1_PLL_SYS_SEC>, + <&rp1_clocks RP1_CLK_ETH>, <&rp1_clocks RP1_PLL_AUDIO>, <&rp1_clocks RP1_PLL_AUDIO_SEC>, <&rp1_clocks RP1_CLK_SYS>, @@ -38,6 +39,7 @@ <1536000000>, // RP1_PLL_AUDIO_CORE <200000000>, // RP1_PLL_SYS <125000000>, // RP1_PLL_SYS_SEC + <125000000>, // RP1_CLK_ETH <61440000>, // RP1_PLL_AUDIO <192000000>, // RP1_PLL_AUDIO_SEC <200000000>, // RP1_CLK_SYS @@ -968,12 +970,14 @@ rp1_eth: ethernet@100000 { reg = <0xc0 0x40100000 0x0 0x4000>; - compatible = "cdns,macb"; + compatible = "raspberrypi,rp1-gem", "cdns,macb"; #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>; - clock-names = "pclk", "hclk", "tsu_clk"; + clocks = <&macb_pclk &macb_hclk + &rp1_clocks RP1_CLK_ETH_TSU + &rp1_clocks RP1_CLK_ETH>; + clock-names = "pclk", "hclk", "tsu_clk", "tx_clk"; phy-mode = "rgmii-id"; cdns,aw2w-max-pipe = /bits/ 8 <8>; cdns,ar2r-max-pipe = /bits/ 8 <8>;