diff --git a/arch/ARM/cortex_m/src/cortex_m-cache.ads b/arch/ARM/cortex_m/src/cortex_m-cache.ads index 7c2b11060..b985fca80 100644 --- a/arch/ARM/cortex_m/src/cortex_m-cache.ads +++ b/arch/ARM/cortex_m/src/cortex_m-cache.ads @@ -35,6 +35,7 @@ with System; package Cortex_M.Cache is + pragma Elaborate_Body; procedure Enable_I_Cache; diff --git a/arch/ARM/cortex_m/src/cortex_m-debug.ads b/arch/ARM/cortex_m/src/cortex_m-debug.ads index 946c11c07..b24222c99 100644 --- a/arch/ARM/cortex_m/src/cortex_m-debug.ads +++ b/arch/ARM/cortex_m/src/cortex_m-debug.ads @@ -30,6 +30,7 @@ ------------------------------------------------------------------------------ package Cortex_M.Debug is + pragma Preelaborate; function Halting_Debug_Enabled return Boolean; diff --git a/arch/ARM/cortex_m/src/cortex_m-dwt.ads b/arch/ARM/cortex_m/src/cortex_m-dwt.ads index 9b393a198..44055e8c5 100644 --- a/arch/ARM/cortex_m/src/cortex_m-dwt.ads +++ b/arch/ARM/cortex_m/src/cortex_m-dwt.ads @@ -51,10 +51,14 @@ package Cortex_M.DWT is -- Data Watchpoint Trace -- below. The values are just the NUMCOMP nibble and the boolean flags in -- the next nibble. No_DWT_Present : constant UInt32 := 0; - Only_One_Comparator : constant UInt32 := 16#1000_0000#; -- 268435456 dec - One_Comparator_Watchpoints : constant UInt32 := 16#1F00_0000#; -- 520093696 dec - Four_Comparators_Watchpoints_And_Triggers : constant UInt32 := 16#4000_0000#; -- 1073741824 dec - Four_Comparators_Watchpoints_Only : constant UInt32 := 16#4F00_0000#; -- 1325400064 dec + Only_One_Comparator : constant UInt32 := + 16#1000_0000#; -- 268435456 dec + One_Comparator_Watchpoints : constant UInt32 := + 16#1F00_0000#; -- 520093696 dec + Four_Comparators_Watchpoints_And_Triggers : constant UInt32 := + 16#4000_0000#; -- 1073741824 dec + Four_Comparators_Watchpoints_Only : constant UInt32 := + 16#4F00_0000#; -- 1325400064 dec function DWT_Reset_Value return UInt32 with Inline; -- Returns the value of the DWT.CTRL register as a word, for convenient diff --git a/arch/ARM/cortex_m/src/cortex_m-hints.ads b/arch/ARM/cortex_m/src/cortex_m-hints.ads index 9022d0693..e4daeb761 100644 --- a/arch/ARM/cortex_m/src/cortex_m-hints.ads +++ b/arch/ARM/cortex_m/src/cortex_m-hints.ads @@ -39,6 +39,7 @@ -- https://developer.arm.com/documentation/ddi0419/e package Cortex_M.Hints is + pragma Preelaborate; procedure Send_Event with Inline; -- A6.7.57 SEV diff --git a/arch/ARM/cortex_m/src/cortex_m-reset.adb b/arch/ARM/cortex_m/src/cortex_m-reset.adb new file mode 100644 index 000000000..3e6ea2058 --- /dev/null +++ b/arch/ARM/cortex_m/src/cortex_m-reset.adb @@ -0,0 +1,49 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2024, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with Memory_Barriers; +with Cortex_M_SVD.SCB; + +procedure Cortex_M.Reset is +begin + Memory_Barriers.Data_Synchronization_Barrier; + + Cortex_M_SVD.SCB.SCB_Periph.AIRCR := + (SYSRESETREQ => True, + VECTKEY => Cortex_M_SVD.SCB.Key, + others => <>); + + Memory_Barriers.Data_Synchronization_Barrier; + + loop + null; + end loop; +end Cortex_M.Reset; diff --git a/arch/ARM/cortex_m/src/cortex_m-reset.ads b/arch/ARM/cortex_m/src/cortex_m-reset.ads new file mode 100644 index 000000000..a9c7fcaf1 --- /dev/null +++ b/arch/ARM/cortex_m/src/cortex_m-reset.ads @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2024, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +-- Issue System Reset Request and loop until it complete. + +procedure Cortex_M.Reset + with No_Return; diff --git a/arch/ARM/cortex_m/src/cortex_m-systick.adb b/arch/ARM/cortex_m/src/cortex_m-systick.adb new file mode 100644 index 000000000..277118ddf --- /dev/null +++ b/arch/ARM/cortex_m/src/cortex_m-systick.adb @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2022, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with Cortex_M_SVD.SysTick; use Cortex_M_SVD.SysTick; + +with HAL; use HAL; + +package body Cortex_M.Systick is + + --------------- + -- Configure -- + --------------- + + procedure Configure + (Source : Clock_Source; + Generate_Interrupt : Boolean; + Reload_Value : HAL.UInt24) + is + begin + SysTick_Periph.CSR.CLKSOURCE := + (case Source is + when CPU_Clock => Cpu_Clk, + when External_Clock => External_Clk); + + SysTick_Periph.CSR.TICKINT := + (if Generate_Interrupt then Enable else Disable); + + SysTick_Periph.RVR.RELOAD := Reload_Value; + SysTick_Periph.CVR.CURRENT := Counter; + end Configure; + + ------------ + -- Enable -- + ------------ + + procedure Enable is + begin + SysTick_Periph.CSR.ENABLE := Enable; + end Enable; + + ------------- + -- Disable -- + ------------- + + procedure Disable is + begin + SysTick_Periph.CSR.ENABLE := Disable; + end Disable; + + --------------------- + -- Counted_To_Zero -- + --------------------- + + function Counted_To_Zero return Boolean is + begin + return SysTick_Periph.CSR.COUNTFLAG; + end Counted_To_Zero; + + ------------- + -- Counter -- + ------------- + + function Counter return HAL.UInt24 is + begin + return SysTick_Periph.CVR.CURRENT; + end Counter; + +end Cortex_M.Systick; diff --git a/arch/ARM/cortex_m/src/cortex_m-systick.ads b/arch/ARM/cortex_m/src/cortex_m-systick.ads new file mode 100644 index 000000000..6af1134d5 --- /dev/null +++ b/arch/ARM/cortex_m/src/cortex_m-systick.ads @@ -0,0 +1,55 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2022, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with HAL; + +package Cortex_M.Systick is + pragma Preelaborate; + + type Clock_Source is (CPU_Clock, External_Clock); + + procedure Configure (Source : Clock_Source; + Generate_Interrupt : Boolean; + Reload_Value : HAL.UInt24); + + procedure Enable; + -- Enable Systick + + procedure Disable; + -- Disable Systick + + function Counted_To_Zero return Boolean; + -- Return the value of the COUNTFLAB bit of the Control and Status Register + + function Counter return HAL.UInt24; + -- Return the current value of the counter + +end Cortex_M.Systick; diff --git a/arch/ARM/cortex_m/src/fpu/cortex_m-fpu.ads b/arch/ARM/cortex_m/src/fpu/cortex_m-fpu.ads index e15788249..e51394985 100644 --- a/arch/ARM/cortex_m/src/fpu/cortex_m-fpu.ads +++ b/arch/ARM/cortex_m/src/fpu/cortex_m-fpu.ads @@ -47,6 +47,7 @@ with HAL; use HAL; package Cortex_M.FPU is + pragma Preelaborate; function Sqrt (X : Float) return Float; diff --git a/arch/ARM/cortex_m/src/memory_barriers.adb b/arch/ARM/cortex_m/src/memory_barriers.adb index 6a4c9d6ea..f790ab434 100644 --- a/arch/ARM/cortex_m/src/memory_barriers.adb +++ b/arch/ARM/cortex_m/src/memory_barriers.adb @@ -44,4 +44,3 @@ package body Memory_Barriers is end Data_Synchronization_Barrier; end Memory_Barriers; - diff --git a/arch/ARM/cortex_m/src/memory_barriers.ads b/arch/ARM/cortex_m/src/memory_barriers.ads index beed73935..795e1bb44 100644 --- a/arch/ARM/cortex_m/src/memory_barriers.ads +++ b/arch/ARM/cortex_m/src/memory_barriers.ads @@ -32,6 +32,7 @@ -- This file provides utility functions for ARM Cortex microcontrollers package Memory_Barriers is + pragma Preelaborate; procedure Data_Synchronization_Barrier with Inline; -- Injects instruction "DSB Sy" i.e., a "full system" domain barrier @@ -39,4 +40,3 @@ package Memory_Barriers is procedure DSB renames Data_Synchronization_Barrier; end Memory_Barriers; - diff --git a/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads b/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads index 08a49c34c..01a3339b3 100644 --- a/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads +++ b/arch/ARM/cortex_m/src/nvic_cm0/cortex_m-nvic.ads @@ -45,6 +45,7 @@ with HAL; use HAL; package Cortex_M.NVIC is -- the Nested Vectored Interrupt Controller + pragma Preelaborate; NVIC_PRIO_BITS : constant := 2; -- All Cortex M0 parts have 2 bit priority mask diff --git a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb index 855729b98..45022c239 100644 --- a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb +++ b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.adb @@ -99,7 +99,8 @@ package body Cortex_M.NVIC is Subpriority : Interrupt_Priority) return Interrupt_Priority is - PriorityGroupTmp : constant Interrupt_Priority := Priority_Group and 16#07#; + PriorityGroupTmp : constant Interrupt_Priority := + Priority_Group and 16#07#; PreemptPriorityBits : Interrupt_Priority; SubPriorityBits : Interrupt_Priority; Temp1 : Interrupt_Priority; @@ -251,4 +252,3 @@ package body Cortex_M.NVIC is end Reset_System; end Cortex_M.NVIC; - diff --git a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads index 1b37b2eff..6a9620fc6 100644 --- a/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads +++ b/arch/ARM/cortex_m/src/nvic_cm4_cm7/cortex_m-nvic.ads @@ -46,6 +46,7 @@ with System; with HAL; use HAL; package Cortex_M.NVIC is -- the Nested Vectored Interrupt Controller + pragma Elaborate_Body; type Interrupt_ID is new Natural range 0 .. 240; type Interrupt_Priority is new UInt32; @@ -65,7 +66,6 @@ package Cortex_M.NVIC is -- the Nested Vectored Interrupt Controller -- 4 bits for pre-emption priority; 0 bits for subpriority Priority_Group_4 : constant UInt32 := 16#00000003#; - procedure Set_Priority_Grouping (Priority_Group : Interrupt_Priority) with Inline; @@ -110,7 +110,6 @@ private type Words is array (Natural range <>) of UInt32; type UInt8s is array (Natural range <>) of UInt8; - type Nested_Vectored_Interrupt_Controller is record ISER : Words (0 .. 7); -- Interrupt Set Enable Register @@ -151,7 +150,6 @@ private STIR at 3584 range 0 .. 31; -- 4 UInt8s end record; - type System_Control_Block is record CPUID : UInt32; -- CPUID Base Register (read-only) @@ -221,7 +219,6 @@ private CPACR at 136 range 0 .. 31; -- Offset: 0x088 end record; - SCS_Base : constant := 16#E000_E000#; -- system control space base address NVIC_Base : constant := SCS_Base + 16#0100#; @@ -238,7 +235,6 @@ private Address => System'To_Address (NVIC_Base); pragma Import (Ada, NVIC); - SCB_AIRCR_PRIGROUP_Pos : constant := 8; SCB_AIRCR_PRIGROUP_Mask : constant UInt32 := Shift_Left (7, SCB_AIRCR_PRIGROUP_Pos); diff --git a/arch/ARM/cortex_m/src/semihosting-filesystem.ads b/arch/ARM/cortex_m/src/semihosting-filesystem.ads index ce38cd790..69dfd3298 100644 --- a/arch/ARM/cortex_m/src/semihosting-filesystem.ads +++ b/arch/ARM/cortex_m/src/semihosting-filesystem.ads @@ -38,6 +38,7 @@ with HAL.Filesystem; use HAL.Filesystem; with HAL; use HAL; package Semihosting.Filesystem is + pragma Preelaborate; type SHFS is new HAL.Filesystem.Filesystem_Driver with private; type Any_SHFS is access all SHFS'Class; diff --git a/arch/ARM/cortex_m/src/semihosting.adb b/arch/ARM/cortex_m/src/semihosting.adb index bf3543ab4..95f90ebfd 100644 --- a/arch/ARM/cortex_m/src/semihosting.adb +++ b/arch/ARM/cortex_m/src/semihosting.adb @@ -97,7 +97,8 @@ package body Semihosting is -- Generic_SH_Call -- --------------------- - function Generic_SH_Call (R0 : SH_Word; R1 : System.Address) return SH_Word is + function Generic_SH_Call (R0 : SH_Word; R1 : System.Address) + return SH_Word is begin return Generic_SH_Call (R0, To_SH_u32 (R1)); end Generic_SH_Call; @@ -300,5 +301,4 @@ package body Semihosting is Write_C (ASCII.LF); end Log_New_Line; - end Semihosting; diff --git a/arch/ARM/cortex_m/src/semihosting.ads b/arch/ARM/cortex_m/src/semihosting.ads index 25534605b..992849e50 100644 --- a/arch/ARM/cortex_m/src/semihosting.ads +++ b/arch/ARM/cortex_m/src/semihosting.ads @@ -33,6 +33,7 @@ with System; with HAL; package Semihosting is + pragma Preelaborate; type SH_Word is new HAL.UInt32;