diff --git a/edg/abstract_parts/AbstractCapacitor.py b/edg/abstract_parts/AbstractCapacitor.py
index 52d2d0f4d..9277776fd 100644
--- a/edg/abstract_parts/AbstractCapacitor.py
+++ b/edg/abstract_parts/AbstractCapacitor.py
@@ -328,9 +328,10 @@ def __init__(self, capacitance: RangeLike, *, exact_capacitance: BoolLike = Fals
super().__init__()
self.cap = self.Block(Capacitor(capacitance, voltage=RangeExpr(), exact_capacitance=exact_capacitance))
- self.gnd = self.Export(self.cap.neg.adapt_to(VoltageSink()), [Common])
- self.pwr = self.Export(self.cap.pos.adapt_to(VoltageSink(
- voltage_limits=(self.cap.actual_voltage_rating + self.gnd.link().voltage).hull(self.gnd.link().voltage),
+ self.gnd = self.Export(self.cap.neg.adapt_to(Ground()), [Common])
+ self.pwr = self.Export(self.cap.pos.adapt_to(VoltageSink.from_gnd(
+ self.gnd,
+ voltage_limits=self.cap.actual_voltage_rating,
current_draw=0*Amp(tol=0)
)), [Power, InOut])
@@ -338,7 +339,7 @@ def __init__(self, capacitance: RangeLike, *, exact_capacitance: BoolLike = Fals
# TODO there should be a way to forward the description string of the inner element
- def connected(self, gnd: Optional[Port[VoltageLink]] = None, pwr: Optional[Port[VoltageLink]] = None) -> \
+ def connected(self, gnd: Optional[Port[GroundLink]] = None, pwr: Optional[Port[VoltageLink]] = None) -> \
'DecouplingCapacitor':
"""Convenience function to connect both ports, returning this object so it can still be given a name."""
if gnd is not None:
diff --git a/edg/abstract_parts/AbstractDevices.py b/edg/abstract_parts/AbstractDevices.py
index da7534957..976f9ad9e 100644
--- a/edg/abstract_parts/AbstractDevices.py
+++ b/edg/abstract_parts/AbstractDevices.py
@@ -11,7 +11,7 @@ def __init__(self, voltage: RangeLike,
super().__init__()
self.pwr = self.Port(VoltageSource.empty()) # set by subclasses
- self.gnd = self.Port(GroundSource.empty())
+ self.gnd = self.Port(Ground.empty())
self.voltage = self.ArgParameter(voltage)
self.capacity = self.ArgParameter(capacity)
diff --git a/edg/abstract_parts/AbstractLed.py b/edg/abstract_parts/AbstractLed.py
index 45d4f973e..0a56a76dc 100644
--- a/edg/abstract_parts/AbstractLed.py
+++ b/edg/abstract_parts/AbstractLed.py
@@ -111,7 +111,7 @@ def __init__(self, count: IntLike, color: LedColorLike = Led.Any, *,
current_draw: RangeLike = (1, 10) * mAmp):
super().__init__()
self.signals = self.Port(Vector(DigitalSink.empty()), [InOut])
- self.gnd = self.Port(VoltageSink.empty(), [Common])
+ self.gnd = self.Port(Ground.empty(), [Common])
self.color = self.ArgParameter(color)
self.current_draw = self.ArgParameter(current_draw)
diff --git a/edg/abstract_parts/AbstractOpamp.py b/edg/abstract_parts/AbstractOpamp.py
index a04b32d44..4bccfe89b 100644
--- a/edg/abstract_parts/AbstractOpamp.py
+++ b/edg/abstract_parts/AbstractOpamp.py
@@ -50,7 +50,7 @@ def __init__(self):
class MultipackOpampGenerator(MultipackOpamp, GeneratorBlock):
"""Skeleton base class that provides scaffolding for common packed opamp definitions"""
class OpampPorts(NamedTuple):
- gnd: VoltageSink
+ gnd: Ground
pwr: VoltageSink
amps: List[Tuple[AnalogSink, AnalogSink, AnalogSource]] # amp-, amp+, out
@@ -68,9 +68,9 @@ def generate(self):
super().generate()
amp_ports = self._make_multipack_opamp()
- self.gnd_merge = self.Block(PackedVoltageSource())
+ self.gnd_merge = self.Block(PackedGround())
self.pwr_merge = self.Block(PackedVoltageSource())
- self.connect(self.gnd_merge.pwr_out, amp_ports.gnd)
+ self.connect(self.gnd_merge.gnd_out, amp_ports.gnd)
self.connect(self.pwr_merge.pwr_out, amp_ports.pwr)
requested = self.get(self.pwr.requested())
@@ -78,7 +78,7 @@ def generate(self):
self.get(self.inn.requested()) == self.get(self.out.requested()) == requested
for i, (amp_neg, amp_pos, amp_out) in zip(requested, amp_ports.amps):
self.connect(self.pwr.append_elt(VoltageSink.empty(), i), self.pwr_merge.pwr_ins.request(i))
- self.connect(self.gnd.append_elt(VoltageSink.empty(), i), self.gnd_merge.pwr_ins.request(i))
+ self.connect(self.gnd.append_elt(Ground.empty(), i), self.gnd_merge.gnd_ins.request(i))
self.connect(self.inn.append_elt(AnalogSink.empty(), i), amp_neg)
self.connect(self.inp.append_elt(AnalogSink.empty(), i), amp_pos)
self.connect(self.out.append_elt(AnalogSource.empty(), i), amp_out)
diff --git a/edg/abstract_parts/AbstractResistor.py b/edg/abstract_parts/AbstractResistor.py
index 30cc25fed..ce48dec89 100644
--- a/edg/abstract_parts/AbstractResistor.py
+++ b/edg/abstract_parts/AbstractResistor.py
@@ -204,7 +204,7 @@ class PulldownResistorArray(TypedTestPoint, GeneratorBlock):
@init_in_parent
def __init__(self, resistance: RangeLike):
super().__init__()
- self.gnd = self.Port(VoltageSink.empty(), [Common])
+ self.gnd = self.Port(Ground.empty(), [Common])
self.io = self.Port(Vector(DigitalSingleSource.empty()), [InOut])
self.generator_param(self.io.requested())
self.resistance = self.ArgParameter(resistance)
diff --git a/edg/abstract_parts/AbstractTestPoint.py b/edg/abstract_parts/AbstractTestPoint.py
index a6f9b2366..528e1225f 100644
--- a/edg/abstract_parts/AbstractTestPoint.py
+++ b/edg/abstract_parts/AbstractTestPoint.py
@@ -51,6 +51,18 @@ def contents(self):
self.assign(conn_tp.tp_name, (self.tp_name == "").then_else(self.io.link().name(), self.tp_name))
+class GroundTestPoint(BaseTypedTestPoint, Block):
+ """Test point with a VoltageSink port."""
+ def __init__(self, *args):
+ super().__init__(*args)
+ self.io = self.Port(Ground.empty(), [InOut])
+ self.connect(self.io, self.tp.io.adapt_to(Ground()))
+
+ def connected(self, io: Port[GroundLink]) -> 'GroundTestPoint':
+ cast(Block, builder.get_enclosing_block()).connect(io, self.io)
+ return self
+
+
class VoltageTestPoint(BaseTypedTestPoint, Block):
"""Test point with a VoltageSink port."""
def __init__(self, *args):
diff --git a/edg/abstract_parts/DummyDevices.py b/edg/abstract_parts/DummyDevices.py
index d13da529c..45d5ae932 100644
--- a/edg/abstract_parts/DummyDevices.py
+++ b/edg/abstract_parts/DummyDevices.py
@@ -10,6 +10,12 @@ def __init__(self) -> None:
self.io = self.Port(Passive(), [InOut])
+class DummyGround(DummyDevice):
+ def __init__(self) -> None:
+ super().__init__()
+ self.gnd = self.Port(Ground(), [Common, InOut])
+
+
class DummyVoltageSource(DummyDevice):
@init_in_parent
def __init__(self, voltage_out: RangeLike = RangeExpr.ZERO,
diff --git a/edg/abstract_parts/GateDrivers.py b/edg/abstract_parts/GateDrivers.py
index 07b254fc2..0de07df00 100644
--- a/edg/abstract_parts/GateDrivers.py
+++ b/edg/abstract_parts/GateDrivers.py
@@ -29,7 +29,7 @@ def __init__(self, has_boot_diode: BoolLike):
self.low_out = self.Port(DigitalSource.empty()) # referenced to main gnd
self.high_pwr = self.Port(VoltageSink.empty(), optional=True) # not used with internal boot diode
- self.high_gnd = self.Port(VoltageSink.empty()) # this encodes the voltage limit from gnd
+ self.high_gnd = self.Port(Ground.empty()) # a separate constraint needs to encode voltage limits
self.high_out = self.Port(DigitalSource.empty()) # referenced to high_pwr and high_gnd
diff --git a/edg/abstract_parts/IoControllerInterfaceMixins.py b/edg/abstract_parts/IoControllerInterfaceMixins.py
index aa422f8dd..c83d9bf15 100644
--- a/edg/abstract_parts/IoControllerInterfaceMixins.py
+++ b/edg/abstract_parts/IoControllerInterfaceMixins.py
@@ -86,18 +86,7 @@ class IoControllerBle(BlockInterfaceMixin[BaseIoController]):
"""Mixin indicating this IoController has programmable Bluetooth LE. Does not expose any ports."""
-@non_library
-class IoControllerGroundOut(BlockInterfaceMixin[IoController]):
- """Base mixin for an IoController that can act as a power output (e.g. dev boards),
- this only provides the ground source pin. Subclasses can define output power pins.
- Multiple power pin mixins can be used on the same class, but only one gnd_out can be connected."""
- def __init__(self, *args, **kwargs) -> None:
- super().__init__(*args, **kwargs)
- self.gnd_out = self.Port(GroundSource.empty(), optional=True,
- doc="Ground for power output ports, when the device is acting as a power source")
-
-
-class IoControllerPowerOut(IoControllerGroundOut, BlockInterfaceMixin[IoController]):
+class IoControllerPowerOut(BlockInterfaceMixin[IoController]):
"""IO controller mixin that provides an output of the IO controller's VddIO rail, commonly 3.3v."""
def __init__(self, *args, **kwargs) -> None:
super().__init__(*args, **kwargs)
@@ -105,7 +94,7 @@ def __init__(self, *args, **kwargs) -> None:
doc="Power output port, typically of the device's Vdd or VddIO rail; must be used with gnd_out")
-class IoControllerUsbOut(IoControllerGroundOut, BlockInterfaceMixin[IoController]):
+class IoControllerUsbOut(BlockInterfaceMixin[IoController]):
"""IO controller mixin that provides an output of the IO controller's USB Vbus."""
def __init__(self, *args, **kwargs) -> None:
super().__init__(*args, **kwargs)
diff --git a/edg/abstract_parts/PowerCircuits.py b/edg/abstract_parts/PowerCircuits.py
index a0bb679e5..313ca048c 100644
--- a/edg/abstract_parts/PowerCircuits.py
+++ b/edg/abstract_parts/PowerCircuits.py
@@ -88,11 +88,11 @@ def contents(self):
self.connect(self.high_gate_res.b, self.high_fet.gate)
# to avoid tolerance stackup, model the switch node as a static voltage
+ self.connect(self.low_fet.drain, self.high_fet.source)
self.connect(self.low_fet.drain.adapt_to(VoltageSource(
- voltage_out=self.pwr.link().voltage)),
- self.high_fet.source.adapt_to(VoltageSink()),
- self.driver.high_gnd,
+ voltage_out=self.pwr.link().voltage)),
self.out)
+ self.connect(self.out.as_ground((0, 0)*Amp), self.driver.high_gnd) # TODO model driver current
class FetHalfBridgeIndependent(FetHalfBridge, HalfBridgeIndependent):
diff --git a/edg/abstract_parts/UsbConnectors.py b/edg/abstract_parts/UsbConnectors.py
index 3f43de265..ea07e3c12 100644
--- a/edg/abstract_parts/UsbConnectors.py
+++ b/edg/abstract_parts/UsbConnectors.py
@@ -27,7 +27,7 @@ class UsbDeviceConnector(UsbConnector, PowerSource):
def __init__(self) -> None:
super().__init__()
self.pwr = self.Port(VoltageSource.empty(), optional=True)
- self.gnd = self.Port(GroundSource.empty())
+ self.gnd = self.Port(Ground.empty())
self.usb = self.Port(UsbHostPort.empty(), optional=True)
diff --git a/edg/abstract_parts/__init__.py b/edg/abstract_parts/__init__.py
index b8d779fc5..b696c7c05 100644
--- a/edg/abstract_parts/__init__.py
+++ b/edg/abstract_parts/__init__.py
@@ -73,8 +73,8 @@
from .AbstractOscillator import Oscillator, TableOscillator
from .AbstractDebugHeaders import SwdCortexTargetConnector, SwdCortexTargetConnectorReset, \
SwdCortexTargetConnectorSwo, SwdCortexTargetConnectorTdi
-from .AbstractTestPoint import TestPoint, VoltageTestPoint, DigitalTestPoint, DigitalArrayTestPoint, AnalogTestPoint, \
- I2cTestPoint, SpiTestPoint, CanControllerTestPoint
+from .AbstractTestPoint import TestPoint, GroundTestPoint, VoltageTestPoint, DigitalTestPoint, DigitalArrayTestPoint, \
+ AnalogTestPoint, I2cTestPoint, SpiTestPoint, CanControllerTestPoint
from .AbstractTestPoint import AnalogRfTestPoint
from .AbstractJumper import Jumper, DigitalJumper
from .PassiveConnector import PassiveConnector, FootprintPassiveConnector
@@ -99,8 +99,8 @@
from .PinMappable import PinResource, PeripheralFixedPin, PeripheralAnyResource, PeripheralFixedResource
from .VariantPinRemapper import VariantPinRemapper
-from .DummyDevices import DummyPassive, DummyVoltageSource, DummyVoltageSink, DummyDigitalSink, DummyAnalogSource, \
- DummyAnalogSink
+from .DummyDevices import DummyPassive, DummyGround, DummyVoltageSource, DummyVoltageSink, DummyDigitalSink, \
+ DummyAnalogSource, DummyAnalogSink
from .DummyDevices import ForcedVoltageCurrentDraw, ForcedVoltage, ForcedVoltageCurrent, ForcedAnalogVoltage,\
ForcedAnalogSignal, ForcedDigitalSinkCurrentDraw
from .MergedBlocks import MergedVoltageSource, MergedDigitalSource, MergedAnalogSource, MergedSpiController
diff --git a/edg/abstract_parts/test_ideal_circuit.py b/edg/abstract_parts/test_ideal_circuit.py
index a0593fadb..2d8c40074 100644
--- a/edg/abstract_parts/test_ideal_circuit.py
+++ b/edg/abstract_parts/test_ideal_circuit.py
@@ -10,10 +10,10 @@
class IdealCircuitTestTop(Block):
def __init__(self):
super().__init__()
- self.gnd = self.Block(DummyVoltageSource(0*Volt(tol=0)))
+ self.gnd = self.Block(DummyGround())
self.pwr = self.Block(DummyVoltageSource(5*Volt(tol=0)))
with self.implicit_connect(
- ImplicitConnect(self.gnd.pwr, [Common]),
+ ImplicitConnect(self.gnd.gnd, [Common]),
) as imp:
self.reg = imp.Block(LinearRegulator(2*Volt(tol=0)))
self.connect(self.reg.pwr_in, self.pwr.pwr)
diff --git a/edg/abstract_parts/test_opamp.py b/edg/abstract_parts/test_opamp.py
index e1118ea2a..286ebddd9 100644
--- a/edg/abstract_parts/test_opamp.py
+++ b/edg/abstract_parts/test_opamp.py
@@ -37,7 +37,7 @@ def __init__(self):
(self.dummyref, ), _ = self.chain(self.dut.reference, self.Block(AnalogSourceDummy()))
(self.dummyout, ), _ = self.chain(self.dut.output, self.Block(DummyAnalogSink()))
(self.dummypwr, ), _ = self.chain(self.dut.pwr, self.Block(DummyVoltageSource()))
- (self.dummygnd, ), _ = self.chain(self.dut.gnd, self.Block(DummyVoltageSource()))
+ (self.dummygnd, ), _ = self.chain(self.dut.gnd, self.Block(DummyGround()))
class OpampCircuitTest(unittest.TestCase):
diff --git a/edg/electronics_model/AnalogPort.py b/edg/electronics_model/AnalogPort.py
index a8457a10c..2b9f897f0 100644
--- a/edg/electronics_model/AnalogPort.py
+++ b/edg/electronics_model/AnalogPort.py
@@ -4,6 +4,7 @@
from ..core import *
from .CircuitBlock import CircuitLink
+from .GroundPort import GroundLink
from .VoltagePorts import CircuitPort, CircuitPortBridge, VoltageLink
@@ -116,7 +117,7 @@ class AnalogSink(AnalogBase):
bridge_type = AnalogSinkBridge
@staticmethod
- def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink], *,
+ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink], *,
voltage_limit_tolerance: Optional[RangeLike] = None,
voltage_limit_abs: Optional[RangeLike] = None,
signal_limit_tolerance: Optional[RangeLike] = None,
@@ -172,7 +173,7 @@ class AnalogSource(AnalogBase):
bridge_type = AnalogSourceBridge
@staticmethod
- def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink], *,
+ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink], *,
signal_out_bound: Optional[Tuple[FloatLike, FloatLike]] = None,
current_limits: RangeLike = RangeExpr.ALL,
impedance: RangeLike = RangeExpr.ZERO):
diff --git a/edg/electronics_model/CircuitBlock.py b/edg/electronics_model/CircuitBlock.py
index cab99a620..a848f8b10 100644
--- a/edg/electronics_model/CircuitBlock.py
+++ b/edg/electronics_model/CircuitBlock.py
@@ -8,8 +8,11 @@
from ..core.ConstraintExpr import Refable
from .KiCadImportableBlock import KiCadImportableBlock
-if TYPE_CHECKING:
- from .VoltagePorts import CircuitPort
+
+CircuitLinkType = TypeVar('CircuitLinkType', bound=Link)
+class CircuitPort(Port[CircuitLinkType], Generic[CircuitLinkType]):
+ """Electrical connection that represents a single port into a single copper net"""
+ pass
T = TypeVar('T', bound=BasePort)
diff --git a/edg/electronics_model/CircuitPackingBlock.py b/edg/electronics_model/CircuitPackingBlock.py
index 35aeb98c4..17d449689 100644
--- a/edg/electronics_model/CircuitPackingBlock.py
+++ b/edg/electronics_model/CircuitPackingBlock.py
@@ -2,6 +2,7 @@
from ..core import *
from .PassivePort import Passive
+from .GroundPort import Ground, GroundReference
from .VoltagePorts import VoltageSource, VoltageSink
@@ -30,6 +31,28 @@ def generate(self):
self.elts.append_elt(Passive(), request)
+class PackedGround(NetPackingBlock, GeneratorBlock):
+ """Takes in several Ground connections that are of the same net (asserted in netlister),
+ and provides a single Ground."""
+ def __init__(self):
+ super().__init__()
+ self.gnd_ins = self.Port(Vector(Ground.empty()))
+ self.gnd_out = self.Port(GroundReference(
+ voltage_out=RangeExpr(),
+ ))
+ self.generator_param(self.gnd_ins.requested())
+ self.packed(self.gnd_ins, self.gnd_out)
+
+ def generate(self):
+ super().generate()
+ self.gnd_ins.defined()
+ for in_request in self.get(self.gnd_ins.requested()):
+ self.gnd_ins.append_elt(Ground(), in_request)
+
+ self.assign(self.gnd_out.voltage_out,
+ self.gnd_ins.hull(lambda x: x.link().voltage))
+
+
class PackedVoltageSource(NetPackingBlock, GeneratorBlock):
"""Takes in several VoltageSink connections that are of the same net (asserted in netlister),
and provides a single VoltageSource. Distributes the current draw from the VoltageSource
diff --git a/edg/electronics_model/DigitalPorts.py b/edg/electronics_model/DigitalPorts.py
index 2842182b6..5f58e84e9 100644
--- a/edg/electronics_model/DigitalPorts.py
+++ b/edg/electronics_model/DigitalPorts.py
@@ -3,6 +3,7 @@
from typing import Optional, Tuple
from ..core import *
from .CircuitBlock import CircuitLink, CircuitPortBridge, CircuitPortAdapter
+from .GroundPort import GroundLink
from .VoltagePorts import CircuitPort, VoltageLink, VoltageSource
from .Units import Volt
@@ -188,7 +189,7 @@ class DigitalSink(DigitalBase):
bridge_type = DigitalSinkBridge
@staticmethod
- def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink], *,
+ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink], *,
voltage_limit_abs: Optional[RangeLike] = None,
voltage_limit_tolerance: Optional[RangeLike] = None,
current_draw: RangeLike = RangeExpr.ZERO,
@@ -276,17 +277,17 @@ class DigitalSource(DigitalBase):
bridge_type = DigitalSourceBridge
@staticmethod
- def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink],
+ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink],
current_limits: RangeLike = RangeExpr.ALL, *,
output_threshold_offset: Optional[Tuple[FloatLike, FloatLike]] = None) -> DigitalSource:
supply_range = VoltageLink._supply_voltage_range(neg, pos)
if output_threshold_offset is not None:
output_offset_low = FloatExpr._to_expr_type(output_threshold_offset[0])
output_offset_high = FloatExpr._to_expr_type(output_threshold_offset[1])
- output_threshold = (VoltageLink._voltage_range(neg).upper() + output_offset_low,
+ output_threshold = (GroundLink._voltage_range(neg).lower() + output_offset_low,
VoltageLink._voltage_range(pos).lower() + output_offset_high)
else:
- output_threshold = (VoltageLink._voltage_range(neg).upper(), VoltageLink._voltage_range(pos).lower())
+ output_threshold = (GroundLink._voltage_range(neg).upper(), VoltageLink._voltage_range(pos).lower())
return DigitalSource(
voltage_out=supply_range,
@@ -365,7 +366,7 @@ class DigitalBidir(DigitalBase):
not_connected_type = DigitalBidirNotConnected
@staticmethod
- def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink],
+ def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink],
voltage_limit_abs: Optional[RangeLike] = None,
voltage_limit_tolerance: Optional[RangeLike] = None,
current_draw: RangeLike = RangeExpr.ZERO,
@@ -384,11 +385,13 @@ def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink],
else: # generic default
voltage_limit = supply_range + RangeExpr._to_expr_type((-0.3, 0.3))
+ neg_base = GroundLink._voltage_range(neg).upper()
input_threshold: RangeLike
if input_threshold_factor is not None:
assert input_threshold_abs is None, "can only specify one input threshold type"
input_threshold_factor = RangeExpr._to_expr_type(input_threshold_factor) # TODO avoid internal functions?
- input_threshold = VoltageLink._voltage_range(pos) * input_threshold_factor
+ input_range = VoltageLink._voltage_range(pos).lower() - neg_base
+ input_threshold = RangeExpr._to_expr_type(neg_base) + RangeExpr._to_expr_type(input_range) * input_threshold_factor
elif input_threshold_abs is not None:
assert input_threshold_factor is None, "can only specify one input threshold type"
input_threshold = RangeExpr._to_expr_type(input_threshold_abs) # TODO avoid internal functions?
@@ -400,14 +403,13 @@ def from_supply(neg: Port[VoltageLink], pos: Port[VoltageLink],
assert output_threshold_abs is None, "can only specify one output threshold type"
output_threshold_factor = RangeExpr._to_expr_type(output_threshold_factor)
# use a pessimistic range
- output_range = VoltageLink._voltage_range(pos).lower() - VoltageLink._voltage_range(neg).upper()
- output_threshold = (VoltageLink._voltage_range(neg).upper() + output_threshold_factor.lower() * output_range,
- VoltageLink._voltage_range(neg).upper() + output_threshold_factor.upper() * output_range)
+ output_range = VoltageLink._voltage_range(pos).lower() - neg_base
+ output_threshold = RangeExpr._to_expr_type(neg_base) + output_threshold_factor * RangeExpr._to_expr_type(output_range)
elif output_threshold_abs is not None:
assert output_threshold_factor is None, "can only specify one output threshold type"
output_threshold = RangeExpr._to_expr_type(output_threshold_abs) # TODO avoid internal functions?
else: # assumed ideal
- output_threshold = (VoltageLink._voltage_range(neg).upper(), VoltageLink._voltage_range(pos).lower())
+ output_threshold = (neg_base, VoltageLink._voltage_range(pos).lower())
return DigitalBidir( # TODO get rid of to_expr_type w/ dedicated Range conversion
voltage_limits=voltage_limit,
diff --git a/edg/electronics_model/Ground.py b/edg/electronics_model/Ground.py
deleted file mode 100644
index 4b74f3faa..000000000
--- a/edg/electronics_model/Ground.py
+++ /dev/null
@@ -1,31 +0,0 @@
-from __future__ import annotations
-
-from ..core import *
-from .Units import Volt, Amp
-from .VoltagePorts import VoltageSink, VoltageSource
-
-
-class GroundWrapper: # a wrapper around VoltageSink to have it behave as Ground
- def __call__(self, current_draw: RangeLike = RangeExpr.ZERO * Amp) -> VoltageSink:
- return VoltageSink(voltage_limits=RangeExpr.ZERO * Volt, current_draw=current_draw)
-
- def empty(self) -> VoltageSink:
- return VoltageSink.empty()
-
-
-class GroundSourceWrapper:
- def __call__(self) -> VoltageSource:
- return VoltageSource(voltage_out=RangeExpr.ZERO * Volt, current_limits=RangeExpr.ALL * Amp)
-
- def empty(self) -> VoltageSource:
- return VoltageSource.empty()
-
-
-# type checker doesn't recognize it if we use a @staticmethod __call__ and have this directly be Ground
-# so it's explicitly instantiated
-Ground = GroundWrapper()
-GroundSource = GroundSourceWrapper()
-
-
-# Standard port tags for implicit connection scopes / auto-connecting power supplies
-Common = PortTag(VoltageSink) # Common ground (0v) port
diff --git a/edg/electronics_model/GroundPort.py b/edg/electronics_model/GroundPort.py
new file mode 100644
index 000000000..1222e3768
--- /dev/null
+++ b/edg/electronics_model/GroundPort.py
@@ -0,0 +1,136 @@
+from __future__ import annotations
+
+from typing import TYPE_CHECKING
+from ..core import *
+from .CircuitBlock import CircuitPortBridge, CircuitPortAdapter, CircuitLink, CircuitPort
+from .Units import Volt, Ohm
+
+if TYPE_CHECKING:
+ from .VoltagePorts import VoltageSource
+ from .DigitalPorts import DigitalSource
+ from .AnalogPort import AnalogSource
+
+
+class GroundLink(CircuitLink):
+ @classmethod
+ def _voltage_range(cls, port: Port[GroundLink]):
+ if isinstance(port, Ground):
+ return port.is_connected().then_else(port.link().voltage,
+ RangeExpr._to_expr_type(RangeExpr.ZERO))
+ elif isinstance(port, GroundReference):
+ return port.voltage_out
+ else:
+ raise TypeError
+
+ def __init__(self) -> None:
+ super().__init__()
+
+ self.ref = self.Port(GroundReference(), optional=True)
+ self.gnds = self.Port(Vector(Ground()))
+
+ self.voltage = self.Parameter(RangeExpr())
+ self.voltage_limits = self.Parameter(RangeExpr())
+
+ def contents(self) -> None:
+ super().contents()
+
+ self.description = DescriptionString(
+ "voltage: ", DescriptionString.FormatUnits(self.voltage, "V"),
+ " of limits: ", DescriptionString.FormatUnits(self.voltage_limits, "V"))
+
+ self.assign(self.voltage, self.ref.is_connected().then_else(
+ self.ref.voltage_out, (0, 0)*Volt
+ ))
+ self.assign(self.voltage_limits, self.gnds.intersection(lambda x: x.voltage_limits))
+ self.require(self.voltage_limits.contains(self.voltage), "overvoltage")
+
+
+class GroundBridge(CircuitPortBridge):
+ def __init__(self) -> None:
+ super().__init__()
+
+ self.outer_port = self.Port(Ground())
+ self.inner_link = self.Port(GroundReference(voltage_out=RangeExpr()))
+
+ def contents(self) -> None:
+ super().contents()
+
+ self.assign(self.inner_link.voltage_out, self.outer_port.link().voltage)
+
+
+class GroundAdapterVoltageSource(CircuitPortAdapter['VoltageSource']):
+ @init_in_parent
+ def __init__(self):
+ from .VoltagePorts import VoltageSource
+ super().__init__()
+ self.src = self.Port(Ground())
+ self.dst = self.Port(VoltageSource(
+ voltage_out=self.src.link().voltage,
+ ))
+
+
+class GroundAdapterDigitalSource(CircuitPortAdapter['DigitalSource']):
+ @init_in_parent
+ def __init__(self):
+ from .DigitalPorts import DigitalSource
+ super().__init__()
+ self.src = self.Port(Ground())
+ self.dst = self.Port(DigitalSource(
+ voltage_out=self.src.link().voltage,
+ output_thresholds=(self.src.link().voltage.lower(), FloatExpr._to_expr_type(float('inf')))
+ ))
+
+
+class GroundAdapterAnalogSource(CircuitPortAdapter['AnalogSource']):
+ @init_in_parent
+ def __init__(self):
+ from .AnalogPort import AnalogSource
+
+ super().__init__()
+ self.src = self.Port(Ground())
+ self.dst = self.Port(AnalogSource(
+ voltage_out=self.src.link().voltage,
+ signal_out=self.src.link().voltage,
+ impedance=(0, 0)*Ohm,
+ ))
+
+
+class Ground(CircuitPort):
+ link_type = GroundLink
+ bridge_type = GroundBridge
+
+ def as_voltage_source(self) -> VoltageSource:
+ return self._convert(GroundAdapterVoltageSource())
+
+ def as_digital_source(self) -> DigitalSource:
+ return self._convert(GroundAdapterDigitalSource())
+
+ def as_analog_source(self) -> AnalogSource:
+ return self._convert(GroundAdapterAnalogSource())
+
+ @classmethod
+ def from_gnd(cls, gnd: Ground, voltage_limits: RangeLike = RangeExpr.ALL) -> Ground:
+ """Creates a ground with an optional voltage offset rating from some other ground"""
+ return Ground(voltage_limits=GroundLink._voltage_range(gnd) + voltage_limits)
+
+ def __init__(self, voltage_limits: RangeLike = Range.all()) -> None:
+ super().__init__()
+ self.voltage_limits = self.Parameter(RangeExpr(voltage_limits))
+
+
+class GroundReference(CircuitPort):
+ link_type = GroundLink
+
+ def __init__(self, voltage_out: RangeLike = RangeExpr.ZERO) -> None:
+ super().__init__()
+ self.voltage_out = self.Parameter(RangeExpr(voltage_out))
+
+
+from deprecated import deprecated
+@deprecated("Use Ground() or GroundReference(...), Ground is no longer directioned")
+def GroundSource(*args, **kwargs):
+ return Ground()
+
+
+# Standard port tags for implicit connection scopes / auto-connecting power supplies
+Common = PortTag(Ground) # Common ground (0v) port
diff --git a/edg/electronics_model/PassivePort.py b/edg/electronics_model/PassivePort.py
index 950dde64d..0be74fb13 100644
--- a/edg/electronics_model/PassivePort.py
+++ b/edg/electronics_model/PassivePort.py
@@ -3,6 +3,7 @@
from typing import TypeVar, Type, Dict
from ..core import *
+from .GroundPort import Ground
from .AnalogPort import AnalogSource, AnalogSink
from .CircuitBlock import CircuitLink, CircuitPortBridge, CircuitPortAdapter
from .DigitalPorts import DigitalSource, DigitalSink, DigitalBidir, DigitalSingleSource
@@ -16,6 +17,14 @@ def __init__(self):
self.passives = self.Port(Vector(Passive()))
+class PassiveAdapterGround(CircuitPortAdapter[Ground]):
+ @init_in_parent
+ def __init__(self, voltage_limits: RangeLike = RangeExpr.ALL):
+ super().__init__()
+ self.src = self.Port(Passive())
+ self.dst = self.Port(Ground(voltage_limits=voltage_limits))
+
+
class PassiveAdapterVoltageSource(CircuitPortAdapter[VoltageSource]):
# TODO we can't use **kwargs b/c init_in_parent needs the initializer list
@init_in_parent
@@ -132,6 +141,7 @@ def __init__(self) -> None:
class Passive(CircuitPort[PassiveLink]):
"""Basic copper-only port, which can be adapted to a more strongly typed Voltage/Digital/Analog* port"""
adapter_type_map: Dict[Type[Port], Type[CircuitPortAdapter]] = {
+ Ground: PassiveAdapterGround,
VoltageSource: PassiveAdapterVoltageSource,
VoltageSink: PassiveAdapterVoltageSink,
DigitalSink: PassiveAdapterDigitalSink,
diff --git a/edg/electronics_model/VoltagePorts.py b/edg/electronics_model/VoltagePorts.py
index f10f4eb4f..48b921886 100644
--- a/edg/electronics_model/VoltagePorts.py
+++ b/edg/electronics_model/VoltagePorts.py
@@ -2,8 +2,9 @@
from typing import *
from ..core import *
-from .CircuitBlock import CircuitPortBridge, CircuitLink, CircuitPortAdapter
-from .Units import Volt, Ohm
+from .CircuitBlock import CircuitPort, CircuitPortBridge, CircuitLink, CircuitPortAdapter
+from .GroundPort import GroundLink, GroundReference
+from .Units import Volt, Ohm, Amp
if TYPE_CHECKING:
from .DigitalPorts import DigitalSource
@@ -16,14 +17,15 @@ def _voltage_range(cls, port: Port[VoltageLink]):
"""Returns the voltage for a Voltage port, either sink or source"""
if isinstance(port, VoltageSource):
return port.voltage_out
- else:
- assert isinstance(port, VoltageSink)
+ elif isinstance(port, VoltageSink):
return port.link().voltage
+ else:
+ raise TypeError
@classmethod
- def _supply_voltage_range(cls, neg: Port[VoltageLink], pos: Port[VoltageLink]):
+ def _supply_voltage_range(cls, neg: Port[GroundLink], pos: Port[VoltageLink]):
"""For a negative and positive Voltage port (either sink or source), returns the voltage span."""
- return cls._voltage_range(neg).hull(cls._voltage_range(pos))
+ return GroundLink._voltage_range(neg).hull(cls._voltage_range(pos))
def __init__(self) -> None:
super().__init__()
@@ -100,18 +102,18 @@ def contents(self) -> None:
self.assign(self.inner_link.current_draw, self.outer_port.link().current_drawn)
-CircuitLinkType = TypeVar('CircuitLinkType', bound=Link)
-class CircuitPort(Port[CircuitLinkType], Generic[CircuitLinkType]):
- """Electrical connection that represents a single port into a single copper net"""
- pass
-
-
class VoltageBase(CircuitPort[VoltageLink]):
link_type = VoltageLink
# TODO: support isolation domains and offset grounds
# these are here (instead of in VoltageSource) since the port may be on the other side of a bridge
+ def as_ground(self, current_draw) -> GroundReference:
+ """Adapts this port to a ground. Current draw is the current drawn from this port, and is required
+ since ground does not model current draw.
+ """
+ return self._convert(VoltageSinkAdapterGroundReference(current_draw))
+
def as_digital_source(self) -> DigitalSource:
return self._convert(VoltageSinkAdapterDigitalSource())
@@ -123,7 +125,7 @@ class VoltageSink(VoltageBase):
bridge_type = VoltageSinkBridge
@staticmethod
- def from_gnd(gnd: VoltageSink, voltage_limits: RangeLike = RangeExpr.ALL,
+ def from_gnd(gnd: Port[GroundLink], voltage_limits: RangeLike = RangeExpr.ALL,
current_draw: RangeLike = RangeExpr.ZERO) -> 'VoltageSink':
return VoltageSink(
voltage_limits=gnd.link().voltage + voltage_limits,
@@ -137,6 +139,20 @@ def __init__(self, voltage_limits: RangeLike = RangeExpr.ALL,
self.current_draw: RangeExpr = self.Parameter(RangeExpr(current_draw))
+class VoltageSinkAdapterGroundReference(CircuitPortAdapter['GroundReference']):
+ @init_in_parent
+ def __init__(self, current_draw: RangeLike):
+ super().__init__()
+ from .GroundPort import GroundReference
+ self.src = self.Port(VoltageSink(
+ voltage_limits=RangeExpr.ALL * Volt,
+ current_draw=current_draw
+ ))
+ self.dst = self.Port(GroundReference(
+ voltage_out=self.src.link().voltage,
+ ))
+
+
class VoltageSinkAdapterDigitalSource(CircuitPortAdapter['DigitalSource']):
@init_in_parent
def __init__(self):
@@ -148,12 +164,7 @@ def __init__(self):
))
self.dst = self.Port(DigitalSource(
voltage_out=self.src.link().voltage,
- output_thresholds=( # use infinity for the other rail
- (self.src.link().voltage.lower() > 0).then_else(FloatExpr._to_expr_type(-float('inf')),
- self.src.link().voltage.upper()),
- (self.src.link().voltage.lower() > 0).then_else(self.src.link().voltage.lower(),
- FloatExpr._to_expr_type(float('inf')))
- )
+ output_thresholds=(FloatExpr._to_expr_type(-float('inf')), self.src.link().voltage.upper())
))
self.assign(self.src.current_draw, self.dst.link().current_drawn) # TODO might be an overestimate
diff --git a/edg/electronics_model/__init__.py b/edg/electronics_model/__init__.py
index a83938a10..0724f6906 100644
--- a/edg/electronics_model/__init__.py
+++ b/edg/electronics_model/__init__.py
@@ -11,8 +11,8 @@
# Need to export link and bridge types for library auto-detection
from .PassivePort import Passive, PassiveLink
+from .GroundPort import Ground, GroundSource, GroundReference, GroundLink, Common
from .VoltagePorts import VoltageSource, VoltageSink, Power, VoltageLink
-from .Ground import Ground, GroundSource, Common
from .DigitalPorts import DigitalSource, DigitalSink, DigitalBidir, DigitalSingleSource, DigitalLink
from .DigitalPorts import DigitalBidirAdapterOpenDrain, DigitalBidirNotConnected
from .AnalogPort import AnalogSource, AnalogSink, AnalogLink
@@ -32,7 +32,7 @@
from .ConnectedGenerator import VoltageSourceConnected, DigitalSourceConnected
-from .CircuitPackingBlock import NetPackingBlock, PackedPassive, PackedVoltageSource
+from .CircuitPackingBlock import NetPackingBlock, PackedPassive, PackedGround, PackedVoltageSource
from .PartParserUtil import PartParserUtil
diff --git a/edg/parts/Batteries.py b/edg/parts/Batteries.py
index c72a9e150..0e2710297 100644
--- a/edg/parts/Batteries.py
+++ b/edg/parts/Batteries.py
@@ -9,7 +9,7 @@ def __init__(self, voltage: RangeLike = (2.0, 3.0)*Volt, *args,
voltage_out=actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf
current_limits=(0, 10)*mAmp,
))
- self.gnd.init_from(GroundSource())
+ self.gnd.init_from(Ground())
def contents(self):
super().contents()
@@ -35,7 +35,7 @@ def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args,
voltage_out=actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf
current_limits=(0, 2)*Amp, # arbitrary assuming low capacity, 1 C discharge
))
- self.gnd.init_from(GroundSource())
+ self.gnd.init_from(Ground())
def contents(self):
super().contents()
@@ -61,7 +61,7 @@ def __init__(self, voltage: RangeLike = (1.3, 1.7)*Volt, *args,
voltage_out=actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf
current_limits=(0, 1)*Amp,
))
- self.gnd.init_from(GroundSource())
+ self.gnd.init_from(Ground())
def contents(self):
super().contents()
diff --git a/edg/parts/BatteryProtector_S8261A.py b/edg/parts/BatteryProtector_S8261A.py
index 7eb23688e..ba6b2368d 100644
--- a/edg/parts/BatteryProtector_S8261A.py
+++ b/edg/parts/BatteryProtector_S8261A.py
@@ -7,8 +7,9 @@ def __init__(self) -> None:
super().__init__()
self.vss = self.Port(Ground())
- self.vdd = self.Port(VoltageSink(
- voltage_limits=self.vss.voltage_limits + RangeExpr._to_expr_type((-0.3, 12) * Volt),
+ self.vdd = self.Port(VoltageSink.from_gnd(
+ self.vss,
+ voltage_limits=(-0.3, 12) * Volt,
current_draw=(0.7, 5.5) * uAmp
))
@@ -44,10 +45,10 @@ def __init__(self) -> None:
self.ic = self.Block(S8261A_Device())
- self.pwr_out = self.Port(VoltageSource.empty())
- self.gnd_out = self.Port(GroundSource.empty())
- self.pwr_in = self.Port(VoltageSink.empty())
self.gnd_in = self.Export(self.ic.vss)
+ self.pwr_in = self.Port(VoltageSink.empty())
+ self.gnd_out = self.Port(Ground.empty())
+ self.pwr_out = self.Port(VoltageSource.empty())
self.do_fet = self.Block(Fet.NFet(
drain_current=self.pwr_in.link().current_drawn,
@@ -87,9 +88,9 @@ def contents(self) -> None:
self.connect(self.do_fet.drain, self.co_fet.drain)
# co fet
- self.connect(self.gnd_out, self.co_fet.source.adapt_to(GroundSource()))
+ self.connect(self.gnd_out, self.co_fet.source.adapt_to(Ground()))
self.connect(self.ic.co, self.co_fet.gate)
- self.vm_res = self.Block(
- SeriesPowerResistor(2 * kOhm(tol=0.10))
- ).connected(self.gnd_out, self.ic.vm.adapt_to(VoltageSink()))
+ self.vm_res = self.Block(Resistor(2 * kOhm(tol=0.10)))
+ self.connect(self.vm_res.a.adapt_to(Ground()), self.gnd_out)
+ self.connect(self.vm_res.b, self.ic.vm)
diff --git a/edg/parts/Bldc_Drv8313.py b/edg/parts/Bldc_Drv8313.py
index 7f8b9ece4..a7ca91a15 100644
--- a/edg/parts/Bldc_Drv8313.py
+++ b/edg/parts/Bldc_Drv8313.py
@@ -1,4 +1,5 @@
import functools
+from typing import Optional
from ..abstract_parts import *
from .JlcPart import JlcPart
@@ -30,7 +31,7 @@ def __init__(self) -> None:
self.nsleep = self.Port(self.din_model) # required, though can be tied high
self.nfault = self.Port(DigitalSingleSource.low_from_supply(self.gnd), optional=True)
- self.pgnds = self.Port(Vector(VoltageSink.empty()))
+ self.pgnds = self.Port(Vector(Passive.empty()))
self.cpl = self.Port(Passive()) # connect Vm rated, 0.01uF ceramic capacitor
self.cph = self.Port(Passive())
@@ -40,17 +41,13 @@ def contents(self) -> None:
self.gnd, self.vm,
current_limits=(-2.5, 2.5)*Amp # peak current, section 1
)
- pgnd_model = VoltageSink(
- voltage_limits=(-0.5, 0.5)*Volt, # Table 6.3 PGNDx voltage
- current_draw=-self.vm.current_draw,
- )
channel_currents = []
out_connected = []
for i in ['1', '2', '3']:
en_i = self.ens.append_elt(self.din_model, i)
in_i = self.ins.append_elt(self.din_model, i)
out_i = self.outs.append_elt(out_model, i)
- self.pgnds.append_elt(pgnd_model, i)
+ self.pgnds.append_elt(Passive(), i)
self.require(out_i.is_connected().implies(en_i.is_connected() & in_i.is_connected()))
channel_currents.append(
@@ -104,8 +101,9 @@ def contents(self) -> None:
self.assign(self.lcsc_part, 'C92482')
-class Drv8313(BldcDriver, Block):
- def __init__(self) -> None:
+class Drv8313(BldcDriver, GeneratorBlock):
+ @init_in_parent
+ def __init__(self, *, risense_res: RangeLike = 100*mOhm(tol=0.05)) -> None:
super().__init__()
self.ic = self.Block(Drv8313_Device())
self.pwr = self.Export(self.ic.vm)
@@ -117,8 +115,10 @@ def __init__(self) -> None:
self.nsleep = self.Port(DigitalSink.empty(), optional=True) # tied high if not connected
self.nfault = self.Export(self.ic.nfault, optional=True)
- self.outs = self.Export(self.ic.outs)
- self.pgnds = self.Port(Vector(VoltageSink.empty()), optional=True) # connected in the generator if used
+ self.outs = self.Port(Vector(DigitalSource.empty()))
+ self.pgnd_sense = self.Port(Vector(AnalogSource.empty()), optional=True) # generates sense resistors if used
+ self.risense_res = self.ArgParameter(risense_res)
+ self.generator_param(self.pgnd_sense.requested())
def contents(self):
super().contents()
@@ -141,8 +141,23 @@ def contents(self):
self.nsleep_default = self.Block(DigitalSourceConnected()) \
.out_with_default(self.ic.nsleep, self.nsleep, self.ic.v3p3.as_digital_source())
- self.pgnd_defaults = ElementDict[VoltageSourceConnected]()
+ def generate(self):
+ super().generate()
+ pgnd_requested = self.get(self.pgnd_sense.requested())
+ gnd_voltage_source: Optional[VoltageSource] = None # only create one, if needed
+ self.pgnd_res = ElementDict[CurrentSenseResistor]()
+ self.pgnd_sense.defined()
+ self.outs.defined()
for i in ['1', '2', '3']:
- pgnd = self.pgnds.append_elt(VoltageSink.empty(), i)
- self.pgnd_defaults[i] = self.Block(VoltageSourceConnected())\
- .out_with_default(self.ic.pgnds.request(i), pgnd, self.gnd)
+ pgnd_pin = self.ic.pgnds.request(i)
+ out = self.outs.append_elt(DigitalSource.empty(), i)
+ self.connect(out, self.ic.outs.request(i))
+ if i in pgnd_requested:
+ if gnd_voltage_source is None:
+ gnd_voltage_source = self.gnd.as_voltage_source()
+ res = self.pgnd_res[i] = self.Block(CurrentSenseResistor(
+ resistance=self.risense_res, sense_in_reqd=False
+ )).connected(gnd_voltage_source, pgnd_pin.adapt_to(VoltageSink(current_draw=out.link().current_drawn)))
+ self.connect(self.pgnd_sense.append_elt(AnalogSource.empty(), i), res.sense_out)
+ else:
+ self.connect(pgnd_pin.adapt_to(Ground()), self.gnd)
diff --git a/edg/parts/Connectors.py b/edg/parts/Connectors.py
index 7a45a08dd..f8ee50226 100644
--- a/edg/parts/Connectors.py
+++ b/edg/parts/Connectors.py
@@ -12,7 +12,7 @@ def __init__(self,
super().__init__()
self.pwr = self.Port(VoltageSource(voltage_out=voltage_out, current_limits=current_limits))
- self.gnd = self.Port(GroundSource())
+ self.gnd = self.Port(Ground())
class Pj_102ah(PowerBarrelJack, FootprintBlock):
@@ -68,7 +68,7 @@ def __init__(self, voltage: RangeLike = (2.5, 4.2)*Volt, *args,
self.chg = self.Port(VoltageSink.empty(), optional=True) # ideal port for charging
self.conn = self.Block(PassiveConnector())
- self.connect(self.gnd, self.conn.pins.request('1').adapt_to(GroundSource()))
+ self.connect(self.gnd, self.conn.pins.request('1').adapt_to(Ground()))
pwr_pin = self.conn.pins.request('2')
self.connect(self.pwr, pwr_pin.adapt_to(VoltageSource(
voltage_out=actual_voltage, # arbitrary from https://www.mouser.com/catalog/additional/Adafruit_3262.pdf
diff --git a/edg/parts/Distance_Vl53l0x.py b/edg/parts/Distance_Vl53l0x.py
index 5bcea8f0f..64772e189 100644
--- a/edg/parts/Distance_Vl53l0x.py
+++ b/edg/parts/Distance_Vl53l0x.py
@@ -12,7 +12,7 @@ def _vdd_model() -> VoltageSink:
)
@staticmethod
- def _gpio_model(vss: Port[VoltageLink], vdd: Port[VoltageLink]) -> DigitalBidir:
+ def _gpio_model(vss: Port[GroundLink], vdd: Port[VoltageLink]) -> DigitalBidir:
# TODO: the datasheet references values to IOVDD, but the value of IOVDD is never stated.
# This model assumes that IOVDD = Vdd
return DigitalBidir.from_supply(
@@ -22,7 +22,7 @@ def _gpio_model(vss: Port[VoltageLink], vdd: Port[VoltageLink]) -> DigitalBidir:
)
@staticmethod
- def _i2c_io_model(vss: Port[VoltageLink], vdd: Port[VoltageLink]) -> DigitalBidir:
+ def _i2c_io_model(vss: Port[GroundLink], vdd: Port[VoltageLink]) -> DigitalBidir:
return DigitalBidir.from_supply(
vss, vdd,
voltage_limit_abs=(-0.5, 3.6), # not referenced to Vdd!
diff --git a/edg/parts/EInk_E2154fs091.py b/edg/parts/EInk_E2154fs091.py
index c6c8491a1..a2a38f1bc 100644
--- a/edg/parts/EInk_E2154fs091.py
+++ b/edg/parts/EInk_E2154fs091.py
@@ -118,7 +118,7 @@ def contents(self) -> None:
self.connect(self.boost_ind.b, self.boost_sw.drain, self.boot_cap.pos)
self.connect(self.boost_sw.gate, self.ic.gdr)
self.connect(self.boost_sw.source, self.boost_res.a, self.ic.rese)
- self.connect(self.boost_res.b.adapt_to(VoltageSink()), self.gnd)
+ self.connect(self.boost_res.b.adapt_to(Ground()), self.gnd)
self.vdd_cap0 = self.Block(DecouplingCapacitor(capacitance=0.11*uFarad(tol=0.2))).connected(self.gnd, self.pwr)
self.vdd_cap1 = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2))).connected(self.gnd, self.pwr)
diff --git a/edg/parts/EInk_Er_Epd027_2.py b/edg/parts/EInk_Er_Epd027_2.py
index 05718e8c7..7f082abd5 100644
--- a/edg/parts/EInk_Er_Epd027_2.py
+++ b/edg/parts/EInk_Er_Epd027_2.py
@@ -113,7 +113,7 @@ def contents(self):
self.vshr_cap = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2))) \
.connected(self.gnd, self.device.vshr)
self.vsl_cap = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2))) \
- .connected(self.device.vsl, self.gnd)
+ .connected(self.gnd, self.device.vsl)
self.vcom_cap = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2))) \
.connected(self.gnd, self.device.vcom)
diff --git a/edg/parts/EInk_WaveshareDriver.py b/edg/parts/EInk_WaveshareDriver.py
index b6645ec8f..396d093df 100644
--- a/edg/parts/EInk_WaveshareDriver.py
+++ b/edg/parts/EInk_WaveshareDriver.py
@@ -103,13 +103,13 @@ def contents(self):
.connected(self.gnd, self.device.vdd1v8)
self.vgl_cap = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2))) \
- .connected(self.device.vgl, self.gnd)
+ .connected(self.gnd, self.device.vgl)
self.vgh_cap = self.Block(DecouplingCapacitor(capacitance=4.7*uFarad(tol=0.2))) \
.connected(self.gnd, self.device.vgh)
self.vsh_cap = self.Block(DecouplingCapacitor(capacitance=4.7*uFarad(tol=0.2))) \
.connected(self.gnd, self.device.vsh)
self.vsl_cap = self.Block(DecouplingCapacitor(capacitance=4.7*uFarad(tol=0.2))) \
- .connected(self.device.vsl, self.gnd)
+ .connected(self.gnd, self.device.vsl)
self.vcom_cap = self.Block(DecouplingCapacitor(capacitance=1*uFarad(tol=0.2))) \
.connected(self.gnd, self.device.vcom)
diff --git a/edg/parts/Fpga_Ice40up.py b/edg/parts/Fpga_Ice40up.py
index 0e365b6d7..61a655bf0 100644
--- a/edg/parts/Fpga_Ice40up.py
+++ b/edg/parts/Fpga_Ice40up.py
@@ -41,7 +41,7 @@ class Ice40up_Device(BaseIoControllerPinmapGenerator, InternalSubcircuit, Genera
BITSTREAM_BITS: int = 0
@staticmethod
- def make_dio_model(gnd: VoltageSink, vccio: VoltageSink):
+ def make_dio_model(gnd: Ground, vccio: VoltageSink):
return DigitalBidir.from_supply(
gnd, vccio,
voltage_limit_tolerance=(-0.3, 0.2) * Volt, # table 4.13
diff --git a/edg/parts/GateDriver_Ir2301.py b/edg/parts/GateDriver_Ir2301.py
index 66becad1e..45d5606db 100644
--- a/edg/parts/GateDriver_Ir2301.py
+++ b/edg/parts/GateDriver_Ir2301.py
@@ -26,7 +26,7 @@ def __init__(self):
)
self.assign(self.vcc.current_draw, (50, 190)*uAmp + self.lo.link().current_drawn)
- self.vs = self.Port(VoltageSink.from_gnd(
+ self.vs = self.Port(Ground.from_gnd(
self.com,
voltage_limits=(-5, 600) # no current draw since this is a "ground" pin
))
diff --git a/edg/parts/GateDriver_Ncp3420.py b/edg/parts/GateDriver_Ncp3420.py
index c0e59ebc7..9b8b46bc0 100644
--- a/edg/parts/GateDriver_Ncp3420.py
+++ b/edg/parts/GateDriver_Ncp3420.py
@@ -25,7 +25,7 @@ def __init__(self):
current_limits=(-self.vcc.link().voltage.lower()/2.5, self.vcc.link().voltage.lower()/3.0)
))
- self.swn = self.Port(VoltageSink.from_gnd(
+ self.swn = self.Port(Ground.from_gnd(
self.pgnd,
voltage_limits=(-5, 35) # no current draw since this is a "ground" pin
))
diff --git a/edg/parts/GateDriver_Ucc27282.py b/edg/parts/GateDriver_Ucc27282.py
index 179bad5c0..b40f54ea2 100644
--- a/edg/parts/GateDriver_Ucc27282.py
+++ b/edg/parts/GateDriver_Ucc27282.py
@@ -25,7 +25,7 @@ def __init__(self):
current_limits=(-3, 3)*Amp # peak pullup and pulldown current
))
- self.hs = self.Port(VoltageSink.from_gnd(
+ self.hs = self.Port(Ground.from_gnd(
self.vss,
voltage_limits=(-8, 100) # looser negative rating possible with pulses
))
diff --git a/edg/parts/Isolator_Cbmud1200.py b/edg/parts/Isolator_Cbmud1200.py
index ea1790f9c..bba77217f 100644
--- a/edg/parts/Isolator_Cbmud1200.py
+++ b/edg/parts/Isolator_Cbmud1200.py
@@ -7,7 +7,7 @@
class Cbmud1200l_Device(InternalSubcircuit, JlcPart, FootprintBlock):
def __init__(self):
super().__init__()
- self.gnd1 = self.Port(VoltageSink()) # can be any voltage
+ self.gnd1 = self.Port(Ground())
self.vdd1 = self.Port(VoltageSink.from_gnd(
self.gnd1,
voltage_limits=(2.5, 5.5)*Volt,
@@ -21,7 +21,7 @@ def __init__(self):
self.via = self.Port(in_model)
self.vib = self.Port(in_model)
- self.gnd2 = self.Port(VoltageSink()) # can be any voltage
+ self.gnd2 = self.Port(Ground())
self.vdd2 = self.Port(VoltageSink.from_gnd( # assumed the same as vdd1 ratings
self.gnd2,
voltage_limits=(2.5, 5.5)*Volt,
diff --git a/edg/parts/Jacdac.py b/edg/parts/Jacdac.py
index 56c029e43..e01c475de 100644
--- a/edg/parts/Jacdac.py
+++ b/edg/parts/Jacdac.py
@@ -59,13 +59,12 @@ def __init__(self, is_power_provider: BoolLike = False) -> None:
self.is_power_provider = self.ArgParameter(is_power_provider)
# ports for power source mode
- self.gnd_src = self.Port(GroundSource(), optional=True)
+ self.gnd = self.Port(Ground(), [Common])
self.jd_pwr_src = self.Port(VoltageSource(
voltage_out=(3.5, 5.5)*Volt,
current_limits=(0, 900)*mAmp
), optional=True)
- self.gnd_sink = self.Port(Ground(), optional=True)
self.jd_pwr_sink = self.Port(VoltageSink(
# if not a power provider, extend the voltage range to directly connect to a power source edge
voltage_limits=self.is_power_provider.then_else((4.3, 5.5)*Volt, (3.5, 5.5)*Amp),
@@ -80,30 +79,27 @@ def __init__(self, is_power_provider: BoolLike = False) -> None:
output_thresholds=(0.3, 3.0)*Volt
))
- self.generator_param(self.jd_pwr_src.is_connected(), self.gnd_src.is_connected())
+ self.generator_param(self.jd_pwr_src.is_connected())
def contents(self):
super().contents()
self.require(self.jd_pwr_src.is_connected() | self.jd_pwr_sink.is_connected())
- self.require(self.jd_pwr_src.is_connected().implies(self.gnd_src.is_connected()))
- self.require(self.jd_pwr_sink.is_connected().implies(self.gnd_sink.is_connected()))
+ self.require(self.jd_pwr_src.is_connected().implies(~self.jd_pwr_sink.is_connected()))
def generate(self):
super().generate()
if self.get(self.jd_pwr_src.is_connected()):
pwr_node: CircuitPort = self.jd_pwr_src
- gnd_node: CircuitPort = self.gnd_src
else:
pwr_node = self.jd_pwr_sink
- gnd_node = self.gnd_sink
self.footprint( # EC refdes for edge connector
'EC', 'Jacdac:JD-PEC-02_Prerouted_recessed',
{
'1': self.jd_data,
- '2': gnd_node,
+ '2': self.gnd,
'3': pwr_node,
},
)
@@ -144,38 +140,31 @@ def __init__(self, is_power_provider: BoolLike = False) -> None:
self.is_power_provider = self.ArgParameter(is_power_provider)
# ports for power source mode
- self.gnd_src = self.Port(GroundSource.empty(), optional=True)
+ self.gnd = self.Port(Ground.empty(), [Common])
self.jd_pwr_src = self.Port(VoltageSource.empty(), optional=True)
-
- self.gnd_sink = self.Port(Ground.empty(), optional=True)
self.jd_pwr_sink = self.Port(VoltageSink.empty(), optional=True)
self.jd_data = self.Port(JacdacDataPort.empty())
self.jd_status = self.Port(DigitalSink.empty()) # for status LED
- self.generator_param(self.gnd_src.is_connected(), self.jd_pwr_src.is_connected(),
- self.gnd_sink.is_connected(), self.jd_pwr_sink.is_connected())
+ self.generator_param(self.jd_pwr_src.is_connected(), self.jd_pwr_sink.is_connected())
def generate(self):
super().contents()
- self.conn = self.Block(JacdacEdgeConnectorBare(self.is_power_provider))
- self.connect(self.jd_data.jd_data, self.conn.jd_data)
+ with self.implicit_connect(
+ ImplicitConnect(self.gnd, [Common]),
+ ) as imp:
+ self.conn = imp.Block(JacdacEdgeConnectorBare(self.is_power_provider))
- if self.get(self.gnd_src.is_connected()):
- gnd_node = self.connect(self.gnd_src, self.conn.gnd_src)
- else:
- gnd_node = self.connect(self.gnd_sink, self.conn.gnd_sink)
+ if self.get(self.jd_pwr_src.is_connected()):
+ jd_pwr_node = self.connect(self.jd_pwr_src, self.conn.jd_pwr_src)
+ else:
+ jd_pwr_node = self.connect(self.jd_pwr_sink, self.conn.jd_pwr_sink)
- if self.get(self.jd_pwr_src.is_connected()):
- jd_pwr_node = self.connect(self.jd_pwr_src, self.conn.jd_pwr_src)
- else:
- jd_pwr_node = self.connect(self.jd_pwr_sink, self.conn.jd_pwr_sink)
+ self.connect(self.jd_data.jd_data, self.conn.jd_data)
- with self.implicit_connect(
- ImplicitConnect(gnd_node, [Common]),
- ) as imp:
(self.status_led, ), _ = self.chain(self.jd_status, imp.Block(IndicatorLed(Led.Orange)))
(self.tvs_jd_pwr, ), _ = self.chain(jd_pwr_node,
imp.Block(ProtectionTvsDiode(working_voltage=(0, 5)*Volt)))
@@ -295,15 +284,15 @@ def contents(self):
self.jd_data = self.connect(self.edge.jd_data, self.jd_mh1.jd_data)
self.jd_pwr = self.connect(self.edge.jd_pwr_src, self.jd_mh3.jd_pwr)
- self.gnd = self.connect(self.edge.gnd_src, self.jd_mh2.gnd, self.jd_mh4.gnd)
+ self.gnd = self.connect(self.edge.gnd, self.jd_mh2.gnd, self.jd_mh4.gnd)
self.jd_status = self.connect(self.edge.jd_status)
def create_edge(self) -> JacdacEdgeConnector:
"""Utility function, creates a new edge connector (in power sink mode) and connects it to the net.
The edge connector Block is returned and must be assigned a name."""
new_edge = self.Block(JacdacEdgeConnector())
+ self.connect(self.gnd, new_edge.gnd)
+ self.connect(self.jd_pwr, new_edge.jd_pwr_sink)
self.connect(self.jd_data, new_edge.jd_data)
self.connect(self.jd_status, new_edge.jd_status)
- self.connect(self.jd_pwr, new_edge.jd_pwr_sink)
- self.connect(self.gnd, new_edge.gnd_sink)
return new_edge
diff --git a/edg/parts/Microcontroller_Esp32.py b/edg/parts/Microcontroller_Esp32.py
index 4c4bd3f2a..ef665d6e7 100644
--- a/edg/parts/Microcontroller_Esp32.py
+++ b/edg/parts/Microcontroller_Esp32.py
@@ -18,8 +18,8 @@ class Esp32_Ios(Esp32_Interfaces, BaseIoControllerPinmapGenerator):
RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name
@abstractmethod
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- """Returns GND and VDDIO (either can be VoltageSink or VoltageSource)."""
+ def _vddio(self) -> Port[VoltageLink]:
+ """Returns VDDIO (can be VoltageSink or VoltageSource)."""
...
def _vdd_model(self) -> VoltageSink:
@@ -28,9 +28,9 @@ def _vdd_model(self) -> VoltageSink:
current_draw=(0.001, 370)*mAmp + self.io_current_draw.upper() # from power off (table 8) to RF working (WRROM datasheet table 9)
)
- def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalBidir:
+ def _dio_model(self, pwr: Port[VoltageLink]) -> DigitalBidir:
return DigitalBidir.from_supply( # section 5.2, table 15
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(-0.3, 0.3) * Volt,
current_limits=(-28, 40)*mAmp,
current_draw=(0, 0)*Amp,
@@ -39,10 +39,10 @@ def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalB
)
def _io_pinmap(self) -> PinMapUtil:
- gnd, pwr = self._gnd_vddio()
- dio_model = self._dio_model(gnd, pwr)
+ pwr = self._vddio()
+ dio_model = self._dio_model(pwr)
sdio_model = DigitalBidir.from_supply( # section 5.2, table 15, for SDIO power domain pins
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(-0.3, 0.3) * Volt,
current_limits=(-28, 20)*mAmp, # reduced sourcing capability
current_draw=(0, 0)*Amp,
@@ -51,12 +51,12 @@ def _io_pinmap(self) -> PinMapUtil:
)
adc_model = AnalogSink.from_supply(
- gnd, pwr,
+ self.gnd, pwr,
signal_limit_abs=(0.1, 2.45)*Volt, # table 3-4, effective ADC range
# TODO: impedance / leakage - not specified by datasheet
)
- dac_model = AnalogSource.from_supply(gnd, pwr) # TODO: no specs in datasheet?!
+ dac_model = AnalogSource.from_supply(self.gnd, pwr) # TODO: no specs in datasheet?!
uart_model = UartPort(DigitalBidir.empty())
spi_model = SpiController(DigitalBidir.empty(), (0, 80) * MHertz) # section 4.1.17
@@ -153,7 +153,7 @@ def __init__(self, **kwargs) -> None:
self.pwr = self.Port(self._vdd_model(), [Power])
self.gnd = self.Port(Ground(), [Common])
- dio_model = self._dio_model(self.pwr, self.gnd)
+ dio_model = self._dio_model(self.pwr)
self.chip_pu = self.Port(dio_model) # power control, must NOT be left floating, table 1
# section 2.4, table 5: strapping IOs that need a fixed value to boot, TODO currently not allocatable post-boot
self.io0 = self.Port(dio_model, optional=True) # default pullup (SPI boot), set low to download boot
@@ -162,8 +162,8 @@ def __init__(self, **kwargs) -> None:
# similarly, the programming UART is fixed and allocated separately
self.uart0 = self.Port(UartPort(dio_model), optional=True)
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ return self.pwr
def _system_pinmap(self) -> Dict[str, CircuitPort]:
return VariantPinRemapper({
@@ -327,28 +327,25 @@ class Freenove_Esp32_Wrover(IoControllerUsbOut, IoControllerPowerOut, Esp32_Ios,
# 'GPIO23': '39', # camera CSI_HREF
}
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- if self.get(self.gnd.is_connected()): # board sinks power
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ if self.get(self.pwr.is_connected()): # board sinks power
+ return self.pwr
else:
- return self.gnd_out, self.pwr_out
+ return self.pwr_out
def _system_pinmap(self) -> Dict[str, CircuitPort]:
- if self.get(self.gnd.is_connected()): # board sinks power
- self.require(~self.vusb_out.is_connected(), "can't source USB power if source gnd not connected")
- self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if source gnd not connected")
- self.require(~self.gnd_out.is_connected(), "can't source gnd if source gnd not connected")
+ if self.get(self.pwr.is_connected()): # board sinks power
+ self.require(~self.vusb_out.is_connected(), "can't source USB power if power input connected")
+ self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if power input connected")
return VariantPinRemapper({
'Vdd': self.pwr,
'Vss': self.gnd,
'GPIO2': self.io2,
}).remap(self.SYSTEM_PIN_REMAP)
else: # board sources power (default)
- self.require(~self.pwr.is_connected(), "can't sink power if source gnd connected")
- self.require(~self.gnd.is_connected(), "can't sink gnd if source gnd connected")
return VariantPinRemapper({
'Vdd': self.pwr_out,
- 'Vss': self.gnd_out,
+ 'Vss': self.gnd,
'Vusb': self.vusb_out,
'GPIO2': self.io2,
}).remap(self.SYSTEM_PIN_REMAP)
@@ -359,7 +356,6 @@ def __init__(self, **kawrgs) -> None:
self.gnd.init_from(Ground())
self.pwr.init_from(self._vdd_model())
- self.gnd_out.init_from(GroundSource())
self.vusb_out.init_from(VoltageSource(
voltage_out=UsbConnector.USB2_VOLTAGE_RANGE,
current_limits=UsbConnector.USB2_CURRENT_LIMITS
@@ -371,13 +367,13 @@ def __init__(self, **kawrgs) -> None:
self.io2 = self.Port(DigitalBidir.empty(), optional=True) # default pulldown (enable download boot), ignored during SPI boot
- self.generator_param(self.gnd.is_connected())
+ self.generator_param(self.pwr.is_connected())
def generate(self) -> None:
super().generate()
gnd, pwr = self._gnd_vddio()
- self.io2.init_from(self._dio_model(gnd, pwr)) # TODO remove this hack
+ self.io2.init_from(self._dio_model(pwr)) # TODO remove this hack
self.footprint(
'U', 'edg:Freenove_ESP32-WROVER',
diff --git a/edg/parts/Microcontroller_Esp32c3.py b/edg/parts/Microcontroller_Esp32c3.py
index be4f72e22..05c5fe57e 100644
--- a/edg/parts/Microcontroller_Esp32c3.py
+++ b/edg/parts/Microcontroller_Esp32c3.py
@@ -18,8 +18,8 @@ class Esp32c3_Ios(Esp32c3_Interfaces, BaseIoControllerPinmapGenerator):
RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name
@abstractmethod
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- """Returns GND and VDDIO (either can be VoltageSink or VoltageSource)."""
+ def _vddio(self) -> Port[VoltageLink]:
+ """Returns VDDIO (can be VoltageSink or VoltageSource)."""
...
def _vdd_model(self) -> VoltageSink:
@@ -28,9 +28,9 @@ def _vdd_model(self) -> VoltageSink:
current_draw=(0.001, 335)*mAmp + self.io_current_draw.upper() # section 4.6, from power off to RF active
)
- def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalBidir:
+ def _dio_model(self, pwr: Port[VoltageLink]) -> DigitalBidir:
return DigitalBidir.from_supply( # table 4.4
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(-0.3, 0.3)*Volt,
current_limits=(-28, 40)*mAmp,
current_draw=(0, 0)*Amp,
@@ -39,11 +39,11 @@ def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalB
)
def _io_pinmap(self) -> PinMapUtil:
- gnd, pwr = self._gnd_vddio()
- dio_model = self._dio_model(gnd, pwr)
+ pwr = self._vddio()
+ dio_model = self._dio_model(pwr)
adc_model = AnalogSink.from_supply(
- gnd, pwr,
+ self.gnd, pwr,
signal_limit_abs=(0, 2.5)*Volt, # table 15, effective ADC range
# TODO: impedance / leakage - not specified by datasheet
)
@@ -95,8 +95,8 @@ class Esp32c3_Base(Esp32c3_Ios, BaseIoControllerPinmapGenerator):
"""
SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s)
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ return self.pwr
def _system_pinmap(self) -> Dict[str, CircuitPort]:
return {
@@ -117,7 +117,7 @@ def __init__(self, **kwargs) -> None:
self.gnd = self.Port(Ground(), [Common])
# section 2.4: strapping IOs that need a fixed value to boot, and currently can't be allocated as GPIO
- dio_model = self._dio_model(self.gnd, self.pwr)
+ dio_model = self._dio_model(self.pwr)
self.en = self.Port(dio_model) # needs external pullup
self.io2 = self.Port(dio_model) # needs external pullup
self.io8 = self.Port(dio_model) # needs external pullup, required for download boot
@@ -423,27 +423,24 @@ class Xiao_Esp32c3(IoControllerUsbOut, IoControllerPowerOut, Esp32c3_Ios, IoCont
'VDD_SPI': '11',
}
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- if self.get(self.gnd.is_connected()): # board sinks power
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ if self.get(self.pwr.is_connected()): # board sinks power
+ return self.pwr
else:
- return self.gnd_out, self.pwr_out
+ return self.pwr_out
def _system_pinmap(self) -> Dict[str, CircuitPort]:
- if self.get(self.gnd.is_connected()): # board sinks power
- self.require(~self.vusb_out.is_connected(), "can't source USB power if source gnd not connected")
- self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if source gnd not connected")
- self.require(~self.gnd_out.is_connected(), "can't source gnd if source gnd not connected")
+ if self.get(self.pwr.is_connected()): # board sinks power
+ self.require(~self.vusb_out.is_connected(), "can't source USB power if power input connected")
+ self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if power input connected")
return VariantPinRemapper({
'VDD': self.pwr,
'GND': self.gnd,
}).remap(self.SYSTEM_PIN_REMAP)
else: # board sources power (default)
- self.require(~self.pwr.is_connected(), "can't sink power if source gnd connected")
- self.require(~self.gnd.is_connected(), "can't sink gnd if source gnd connected")
return VariantPinRemapper({
'VDD': self.pwr_out,
- 'GND': self.gnd_out,
+ 'GND': self.gnd,
'VUSB': self.vusb_out,
}).remap(self.SYSTEM_PIN_REMAP)
@@ -453,7 +450,6 @@ def contents(self) -> None:
self.gnd.init_from(Ground())
self.pwr.init_from(self._vdd_model())
- self.gnd_out.init_from(GroundSource())
self.vusb_out.init_from(VoltageSource(
voltage_out=UsbConnector.USB2_VOLTAGE_RANGE,
current_limits=UsbConnector.USB2_CURRENT_LIMITS
@@ -463,7 +459,7 @@ def contents(self) -> None:
current_limits=UsbConnector.USB2_CURRENT_LIMITS
))
- self.generator_param(self.gnd.is_connected())
+ self.generator_param(self.pwr.is_connected())
def generate(self) -> None:
super().generate()
diff --git a/edg/parts/Microcontroller_Esp32s3.py b/edg/parts/Microcontroller_Esp32s3.py
index 5c9c07035..6b7c60f4b 100644
--- a/edg/parts/Microcontroller_Esp32s3.py
+++ b/edg/parts/Microcontroller_Esp32s3.py
@@ -19,8 +19,8 @@ class Esp32s3_Ios(Esp32s3_Interfaces, BaseIoControllerPinmapGenerator):
RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name
@abstractmethod
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- """Returns GND and VDDIO (either can be VoltageSink or VoltageSource)."""
+ def _vddio(self) -> Port[VoltageLink]:
+ """Returns VDDIO (can be VoltageSink or VoltageSource)."""
...
def _vdd_model(self) -> VoltageSink:
@@ -29,9 +29,9 @@ def _vdd_model(self) -> VoltageSink:
current_draw=(0.001, 355)*mAmp + self.io_current_draw.upper() # from power off (table 4-8) to RF working (table 12 on WROOM datasheet)
)
- def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalBidir:
+ def _dio_model(self, pwr: Port[VoltageLink]) -> DigitalBidir:
return DigitalBidir.from_supply( # table 4-4
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(-0.3, 0.3) * Volt,
current_limits=(-28, 40)*mAmp,
input_threshold_factor=(0.25, 0.75),
@@ -39,11 +39,11 @@ def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalB
)
def _io_pinmap(self) -> PinMapUtil:
- gnd, pwr = self._gnd_vddio()
- dio_model = self._dio_model(gnd, pwr)
+ pwr = self._vddio()
+ dio_model = self._dio_model(pwr)
adc_model = AnalogSink.from_supply(
- gnd, pwr,
+ self.gnd, pwr,
signal_limit_abs=(0, 2.9)*Volt, # table 4-5, effective ADC range at max attenuation
# TODO: impedance / leakage - not specified by datasheet
)
@@ -154,8 +154,8 @@ class Esp32s3_Base(Esp32s3_Ios, GeneratorBlock):
"""
SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s)
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ return self.pwr
def _system_pinmap(self) -> Dict[str, CircuitPort]:
return VariantPinRemapper({
@@ -174,7 +174,7 @@ def __init__(self, **kwargs) -> None:
self.pwr = self.Port(self._vdd_model(), [Power])
self.gnd = self.Port(Ground(), [Common])
- dio_model = self._dio_model(self.gnd, self.pwr)
+ dio_model = self._dio_model(self.pwr)
self.chip_pu = self.Port(dio_model) # table 2-5, power up/down control, do NOT leave floating
self.io0 = self.Port(dio_model, optional=True) # table 2-11, default pullup (SPI boot), set low to download boot
self.uart0 = self.Port(UartPort(dio_model), optional=True) # programming
@@ -337,34 +337,31 @@ class Freenove_Esp32s3_Wroom(IoControllerUsbOut, IoControllerPowerOut, Esp32s3_I
'GPIO1': '38',
}
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- if self.get(self.gnd.is_connected()): # board sinks power
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ if self.get(self.pwr.is_connected()): # board sinks power
+ return self.pwr
else:
- return self.gnd_out, self.pwr_out
+ return self.pwr_out
def _system_pinmap(self) -> Dict[str, CircuitPort]:
- if self.get(self.gnd.is_connected()): # board sinks power
- self.require(~self.vusb_out.is_connected(), "can't source USB power if source gnd not connected")
- self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if source gnd not connected")
- self.require(~self.gnd_out.is_connected(), "can't source gnd if source gnd not connected")
+ if self.get(self.pwr.is_connected()): # board sinks power
+ self.require(~self.vusb_out.is_connected(), "can't source USB power if power input connected")
+ self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if power input connected")
return VariantPinRemapper({
'VDD': self.pwr,
'GND': self.gnd,
}).remap(self.SYSTEM_PIN_REMAP)
else: # board sources power (default)
- self.require(~self.pwr.is_connected(), "can't sink power if source gnd connected")
- self.require(~self.gnd.is_connected(), "can't sink gnd if source gnd connected")
return VariantPinRemapper({
'VDD': self.pwr_out,
- 'GND': self.gnd_out,
+ 'GND': self.gnd,
'VUSB': self.vusb_out,
}).remap(self.SYSTEM_PIN_REMAP)
def _io_pinmap(self) -> PinMapUtil: # allow the camera I2C pins to be used externally
- gnd, pwr = self._gnd_vddio()
+ pwr = self._vddio()
return super()._io_pinmap().add([
- PeripheralFixedPin('CAM_SCCB', I2cController(self._dio_model(gnd, pwr), has_pullup=True), {
+ PeripheralFixedPin('CAM_SCCB', I2cController(self._dio_model(pwr), has_pullup=True), {
'scl': '4', 'sda': '3'
})
])
@@ -375,7 +372,6 @@ def contents(self) -> None:
self.gnd.init_from(Ground())
self.pwr.init_from(self._vdd_model())
- self.gnd_out.init_from(GroundSource())
self.vusb_out.init_from(VoltageSource(
voltage_out=UsbConnector.USB2_VOLTAGE_RANGE,
current_limits=UsbConnector.USB2_CURRENT_LIMITS
@@ -385,7 +381,7 @@ def contents(self) -> None:
current_limits=UsbConnector.USB2_CURRENT_LIMITS
))
- self.generator_param(self.gnd.is_connected())
+ self.generator_param(self.pwr.is_connected())
def generate(self) -> None:
super().generate()
diff --git a/edg/parts/Microcontroller_Rp2040.py b/edg/parts/Microcontroller_Rp2040.py
index 468c0a716..77557da2d 100644
--- a/edg/parts/Microcontroller_Rp2040.py
+++ b/edg/parts/Microcontroller_Rp2040.py
@@ -16,8 +16,8 @@ class Rp2040_Ios(Rp2040_Interfaces, BaseIoControllerPinmapGenerator):
RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name
@abstractmethod
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- """Returns GND and VDDIO (either can be VoltageSink or VoltageSource)."""
+ def _vddio(self) -> Port[VoltageLink]:
+ """Returns VDDIO (can be VoltageSink or VoltageSource)."""
...
def _iovdd_model(self):
@@ -26,9 +26,9 @@ def _iovdd_model(self):
current_draw=(1.2, 4.3)*mAmp + self.io_current_draw.upper() # Table 629
)
- def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalBidir:
+ def _dio_model(self, pwr: Port[VoltageLink]) -> DigitalBidir:
return DigitalBidir.from_supply( # table 4.4
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(-0.3, 0.3) * Volt,
current_limits=(-12, 12)*mAmp, # by IOH / IOL modes
input_threshold_abs=(0.8, 2.0)*Volt, # for IOVdd=3.3, TODO other IOVdd ranges
@@ -36,11 +36,11 @@ def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalB
)
def _io_pinmap(self) -> PinMapUtil:
- gnd, pwr = self._gnd_vddio()
- dio_usb_model = dio_ft_model = dio_std_model = self._dio_model(gnd, pwr)
+ pwr = self._vddio()
+ dio_usb_model = dio_ft_model = dio_std_model = self._dio_model(pwr)
adc_model = AnalogSink.from_supply( # Table 626
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(0, 0), # ADC input voltage range
signal_limit_tolerance=(0, 0), # ADC input voltage range
impedance=(100, float('inf')) * kOhm
@@ -177,8 +177,8 @@ class Rp2040_Device(Rp2040_Ios, BaseIoControllerPinmapGenerator, InternalSubcirc
'SWCLK': '24',
}
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- return self.gnd, self.iovdd
+ def _vddio(self) -> Port[VoltageLink]:
+ return self.iovdd
def __init__(self, **kwargs) -> None:
super().__init__(**kwargs)
@@ -225,7 +225,7 @@ def contents(self) -> None:
super().contents()
# Port models
- dio_ft_model = dio_std_model = self._dio_model(self.gnd, self.iovdd)
+ dio_ft_model = dio_std_model = self._dio_model(self.iovdd)
self.qspi.init_from(SpiController(dio_std_model))
self.qspi_cs.init_from(dio_std_model)
self.qspi_sd2.init_from(dio_std_model)
@@ -403,27 +403,24 @@ class Xiao_Rp2040(IoControllerUsbOut, IoControllerPowerOut, Rp2040_Ios, IoContro
'GPIO3': '11',
}
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- if self.get(self.gnd.is_connected()): # board sinks power
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ if self.get(self.pwr.is_connected()): # board sinks power
+ return self.pwr
else:
- return self.gnd_out, self.pwr_out
+ return self.pwr_out
def _system_pinmap(self) -> Dict[str, CircuitPort]:
- if self.get(self.gnd.is_connected()): # board sinks power
- self.require(~self.vusb_out.is_connected(), "can't source USB power if source gnd not connected")
- self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if source gnd not connected")
- self.require(~self.gnd_out.is_connected(), "can't source gnd if source gnd not connected")
+ if self.get(self.pwr.is_connected()): # board sinks power
+ self.require(~self.vusb_out.is_connected(), "can't source USB power if power input connected")
+ self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if power input connected")
return VariantPinRemapper({
'VDD': self.pwr,
'GND': self.gnd,
}).remap(self.SYSTEM_PIN_REMAP)
else: # board sources power (default)
- self.require(~self.pwr.is_connected(), "can't sink power if source gnd connected")
- self.require(~self.gnd.is_connected(), "can't sink gnd if source gnd connected")
return VariantPinRemapper({
'VDD': self.pwr_out,
- 'GND': self.gnd_out,
+ 'GND': self.gnd,
'VUSB': self.vusb_out,
}).remap(self.SYSTEM_PIN_REMAP)
@@ -433,7 +430,6 @@ def contents(self) -> None:
self.gnd.init_from(Ground())
self.pwr.init_from(self._iovdd_model())
- self.gnd_out.init_from(GroundSource())
self.vusb_out.init_from(VoltageSource(
voltage_out=UsbConnector.USB2_VOLTAGE_RANGE,
current_limits=UsbConnector.USB2_CURRENT_LIMITS
@@ -443,7 +439,7 @@ def contents(self) -> None:
current_limits=UsbConnector.USB2_CURRENT_LIMITS
))
- self.generator_param(self.gnd.is_connected())
+ self.generator_param(self.pwr.is_connected())
def generate(self) -> None:
super().generate()
diff --git a/edg/parts/Microcontroller_Stm32f303.py b/edg/parts/Microcontroller_Stm32f303.py
index 46b89e602..a5846ff14 100644
--- a/edg/parts/Microcontroller_Stm32f303.py
+++ b/edg/parts/Microcontroller_Stm32f303.py
@@ -12,8 +12,8 @@ class Stm32f303_Ios(IoControllerI2cTarget, IoControllerDac, IoControllerCan, Bas
RESOURCE_PIN_REMAP: Dict[str, str]
@abstractmethod
- def _gnd_vddio_vdda(self) -> Tuple[Port[VoltageLink], Port[VoltageLink], Port[VoltageLink]]:
- """Returns GND, VDDIO, VDDA (either can be VoltageSink or VoltageSource)."""
+ def _vddio_vdda(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
+ """Returns VDDIO, VDDA (either can be VoltageSink or VoltageSource)."""
...
def _vdd_model(self) -> VoltageSink:
@@ -26,40 +26,40 @@ def _io_pinmap(self) -> PinMapUtil:
"""Returns the mappable for a STM32F303 device with the input power and ground references.
This allows a shared definition between discrete chips and microcontroller boards"""
# these are common to all IO blocks
- gnd, vdd, vdda = self._gnd_vddio_vdda()
+ vdd, vdda = self._vddio_vdda()
input_threshold_factor = (0.3, 0.7) # TODO relaxed (but more complex) bounds available for different IO blocks
current_limits = (-20, 20)*mAmp # Section 6.3.14, TODO loose with relaxed VOL/VOH
dio_tc_model = DigitalBidir.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_abs=(-0.3, 0.3) * Volt, # Table 19
current_draw=(0, 0)*Amp, current_limits=current_limits,
input_threshold_factor=input_threshold_factor,
pullup_capable=True, pulldown_capable=True
)
dio_tc_switch_model = DigitalBidir.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_abs=(-0.3, 0.3) * Volt, # Table 19
current_draw=(0, 0)*Amp, current_limits=(-3, 0), # Table 13, note 1, can sink 3 mA and should not source current
input_threshold_factor=input_threshold_factor,
pullup_capable=True, pulldown_capable=True
)
dio_tt_model = DigitalBidir.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_abs=(-0.3, 3.6) * Volt, # Table 19
current_draw=(0, 0)*Amp, current_limits=current_limits,
input_threshold_factor=input_threshold_factor,
pullup_capable=True, pulldown_capable=True
)
dio_tta_model = DigitalBidir.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_abs=(-0.3 * Volt, vdda.link().voltage.lower() + 0.3 * Volt), # Table 19
current_draw=(0, 0)*Amp, current_limits=current_limits,
input_threshold_factor=input_threshold_factor,
pullup_capable=True, pulldown_capable=True
)
dio_ft_model = DigitalBidir.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_abs=(-0.3, 5.5) * Volt, # Table 19
current_draw=(0, 0)*Amp, current_limits=current_limits,
input_threshold_factor=input_threshold_factor,
@@ -67,7 +67,7 @@ def _io_pinmap(self) -> PinMapUtil:
)
dio_ftf_model = dio_ft_model
dio_boot0_model = DigitalBidir.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_abs=(-0.3, 5.5) * Volt, # Table 19
current_draw=(0, 0)*Amp, current_limits=current_limits,
input_threshold_factor=input_threshold_factor,
@@ -75,13 +75,13 @@ def _io_pinmap(self) -> PinMapUtil:
)
adc_model = AnalogSink.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
voltage_limit_tolerance=(-0.3, 0.3) * Volt,
signal_limit_tolerance=(0, 0), # Table 60 conversion voltage range
impedance=100*kOhm(tol=0) # TODO: actually spec'd as maximum external impedance; internal impedance not given
)
dac_model = AnalogSource.from_supply(
- gnd, vdd,
+ self.gnd, vdd,
signal_out_bound=(0.2*Volt, -0.2*Volt),
impedance=15*kOhm(tol=0) # assumes buffer off
)
@@ -217,27 +217,24 @@ class Nucleo_F303k8(IoControllerUsbOut, IoControllerPowerOut, IoController, Stm3
'PB3': '30', # CN4.15, D13
}
- def _gnd_vddio_vdda(self) -> Tuple[Port[VoltageLink], Port[VoltageLink], Port[VoltageLink]]:
- if self.get(self.gnd.is_connected()): # board sinks power
- return self.gnd, self.pwr, self.pwr
+ def _vddio_vdda(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
+ if self.get(self.pwr.is_connected()): # board sinks power
+ return self.pwr, self.pwr
else:
- return self.gnd_out, self.pwr_out, self.pwr_out
+ return self.pwr_out, self.pwr_out
def _system_pinmap(self) -> Dict[str, CircuitPort]:
- if self.get(self.gnd.is_connected()): # board sinks power
- self.require(~self.vusb_out.is_connected(), "can't source USB power if source gnd not connected")
- self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if source gnd not connected")
- self.require(~self.gnd_out.is_connected(), "can't source gnd if source gnd not connected")
+ if self.get(self.pwr.is_connected()): # board sinks power
+ self.require(~self.vusb_out.is_connected(), "can't source USB power if power input connected")
+ self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if power input connected")
return VariantPinRemapper({
'Vdd': self.pwr,
'Vss': self.gnd,
}).remap(self.SYSTEM_PIN_REMAP)
else: # board sources power (default)
- self.require(~self.pwr.is_connected(), "can't sink power if source gnd connected")
- self.require(~self.gnd.is_connected(), "can't sink gnd if source gnd connected")
return VariantPinRemapper({
'Vdd': self.pwr_out,
- 'Vss': self.gnd_out,
+ 'Vss': self.gnd,
'Vusb': self.vusb_out,
}).remap(self.SYSTEM_PIN_REMAP)
@@ -247,7 +244,6 @@ def __init__(self):
self.gnd.init_from(Ground())
self.pwr.init_from(self._vdd_model())
- self.gnd_out.init_from(GroundSource())
self.vusb_out.init_from(VoltageSource(
voltage_out=(4.75 - 0.58, 5.1) * Volt, # 4.75V USB - 0.58v BAT60JFILM drop to 5.1 from LD1117S50TR, ignoring ST890CDR
current_limits=(0, 0.5) * Amp # max USB draw # TODO higher from external power
@@ -257,7 +253,7 @@ def __init__(self):
current_limits=(0, 0.5) * Amp # max USB current draw, LDO also guarantees 500mA output current
))
- self.generator_param(self.gnd.is_connected())
+ self.generator_param(self.pwr.is_connected())
def generate(self) -> None:
super().generate()
diff --git a/edg/parts/Microcontroller_nRF52840.py b/edg/parts/Microcontroller_nRF52840.py
index 272f8fe01..1a74b481f 100644
--- a/edg/parts/Microcontroller_nRF52840.py
+++ b/edg/parts/Microcontroller_nRF52840.py
@@ -18,7 +18,7 @@ class Nrf52840_Ios(Nrf52840_Interfaces, BaseIoControllerPinmapGenerator, Generat
RESOURCE_PIN_REMAP: Dict[str, str] # resource name in base -> pin name
@abstractmethod
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
+ def _vddio(self) -> Port[VoltageLink]:
...
def _vdd_model(self) -> VoltageSink:
@@ -27,9 +27,9 @@ def _vdd_model(self) -> VoltageSink:
current_draw=(0, 212 / 64 + 4.8)*mAmp + self.io_current_draw.upper() # CPU @ max 212 Coremarks + 4.8mA in RF transmit
)
- def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalBidir:
+ def _dio_model(self, pwr: Port[VoltageLink]) -> DigitalBidir:
return DigitalBidir.from_supply(
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(-0.3, 0.3) * Volt,
current_limits=(-6, 6)*mAmp, # minimum current, high drive, Vdd>2.7
current_draw=(0, 0)*Amp,
@@ -40,12 +40,12 @@ def _dio_model(self, gnd: Port[VoltageLink], pwr: Port[VoltageLink]) -> DigitalB
def _io_pinmap(self) -> PinMapUtil:
"""Returns the mappable for given the input power and ground references.
This separates the system pins definition from the IO pins definition."""
- gnd, pwr = self._gnd_vddio()
- dio_model = self._dio_model(gnd, pwr)
+ pwr = self._vddio()
+ dio_model = self._dio_model(pwr)
dio_lf_model = dio_model # "standard drive, low frequency IO only" (differences not modeled)
adc_model = AnalogSink.from_supply(
- gnd, pwr,
+ self.gnd, pwr,
voltage_limit_tolerance=(0, 0), # datasheet 6.23.2, analog inputs cannot exceed Vdd or be lower than Vss
signal_limit_tolerance=(0, 0),
impedance=Range.from_lower(1)*MOhm
@@ -173,8 +173,8 @@ def _io_pinmap(self) -> PinMapUtil:
class Nrf52840_Base(Nrf52840_Ios, GeneratorBlock):
SYSTEM_PIN_REMAP: Dict[str, Union[str, List[str]]] # pin name in base -> pin name(s)
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ return self.pwr
def _system_pinmap(self) -> Dict[str, CircuitPort]:
return VariantPinRemapper({
@@ -187,8 +187,8 @@ def _system_pinmap(self) -> Dict[str, CircuitPort]:
def __init__(self, **kwargs) -> None:
super().__init__(**kwargs)
- self.pwr = self.Port(self._vdd_model(), [Power])
self.gnd = self.Port(Ground(), [Common])
+ self.pwr = self.Port(self._vdd_model(), [Power])
self.pwr_usb = self.Port(VoltageSink(
voltage_limits=(4.35, 5.5)*Volt,
@@ -206,7 +206,7 @@ def __init__(self, **kwargs) -> None:
optional=True)
self.swd = self.Port(SwdTargetPort.empty())
- self.nreset = self.Port(DigitalSink.from_bidir(self._dio_model(self.gnd, self.pwr)), optional=True)
+ self.nreset = self.Port(DigitalSink.from_bidir(self._dio_model(self.pwr)), optional=True)
self._io_ports.insert(0, self.swd)
@@ -462,27 +462,24 @@ class Feather_Nrf52840(IoControllerUsbOut, IoControllerPowerOut, Nrf52840_Ios, I
# note onboard VBAT sense divider at P0.29
}
- def _gnd_vddio(self) -> Tuple[Port[VoltageLink], Port[VoltageLink]]:
- if self.get(self.gnd.is_connected()): # board sinks power
- return self.gnd, self.pwr
+ def _vddio(self) -> Port[VoltageLink]:
+ if self.get(self.pwr.is_connected()): # board sinks power
+ return self.pwr
else:
- return self.gnd_out, self.pwr_out
+ return self.pwr_out
def _system_pinmap(self) -> Dict[str, CircuitPort]:
- if self.get(self.gnd.is_connected()): # board sinks power
- self.require(~self.vusb_out.is_connected(), "can't source USB power if source gnd not connected")
- self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if source gnd not connected")
- self.require(~self.gnd_out.is_connected(), "can't source gnd if source gnd not connected")
+ if self.get(self.pwr.is_connected()): # board sinks power
+ self.require(~self.vusb_out.is_connected(), "can't source USB power if power input connected")
+ self.require(~self.pwr_out.is_connected(), "can't source 3v3 power if power input connected")
return VariantPinRemapper({
'Vdd': self.pwr,
'Vss': self.gnd,
}).remap(self.SYSTEM_PIN_REMAP)
else: # board sources power (default)
- self.require(~self.pwr.is_connected(), "can't sink power if source gnd connected")
- self.require(~self.gnd.is_connected(), "can't sink gnd if source gnd connected")
return VariantPinRemapper({
'Vdd': self.pwr_out,
- 'Vss': self.gnd_out,
+ 'Vss': self.gnd,
'Vbus': self.vusb_out,
}).remap(self.SYSTEM_PIN_REMAP)
@@ -494,7 +491,6 @@ def contents(self):
mbr120_drop = (0, 0.340)*Volt
ap2112_3v3_out = 3.3*Volt(tol=0.015) # note dropout voltage up to 400mV, current up to 600mA
- self.gnd_out.init_from(GroundSource())
self.vusb_out.init_from(VoltageSource(
voltage_out=UsbConnector.USB2_VOLTAGE_RANGE - mbr120_drop,
current_limits=UsbConnector.USB2_CURRENT_LIMITS
@@ -504,7 +500,7 @@ def contents(self):
current_limits=UsbConnector.USB2_CURRENT_LIMITS
))
- self.generator_param(self.gnd.is_connected())
+ self.generator_param(self.pwr.is_connected())
def generate(self) -> None:
super().generate()
diff --git a/edg/parts/UsbPorts.py b/edg/parts/UsbPorts.py
index c7bb7f582..e0fd9345e 100644
--- a/edg/parts/UsbPorts.py
+++ b/edg/parts/UsbPorts.py
@@ -41,7 +41,7 @@ def __init__(self, voltage_out: RangeLike = UsbConnector.USB2_VOLTAGE_RANGE, #
cc_pullup_capable: BoolLike = False) -> None:
super().__init__()
self.pwr = self.Port(VoltageSource(voltage_out=voltage_out, current_limits=current_limits), optional=True)
- self.gnd = self.Port(GroundSource())
+ self.gnd = self.Port(Ground())
self.usb = self.Port(UsbHostPort(), optional=True)
self.shield = self.Port(Passive(), optional=True)
@@ -126,7 +126,7 @@ def contents(self):
voltage_out=self.USB2_VOLTAGE_RANGE,
current_limits=self.USB2_CURRENT_LIMITS
))
- self.gnd.init_from(GroundSource())
+ self.gnd.init_from(Ground())
self.usb.init_from(UsbHostPort())
self.footprint(
@@ -151,7 +151,7 @@ def contents(self):
voltage_out=self.USB2_VOLTAGE_RANGE,
current_limits=self.USB2_CURRENT_LIMITS
))
- self.gnd.init_from(GroundSource())
+ self.gnd.init_from(Ground())
self.usb.init_from(UsbHostPort())
self.footprint(
diff --git a/edg/parts/resources/EInkBoostPowerPath.kicad_sch b/edg/parts/resources/EInkBoostPowerPath.kicad_sch
index 9d167aa15..4908bea53 100644
--- a/edg/parts/resources/EInkBoostPowerPath.kicad_sch
+++ b/edg/parts/resources/EInkBoostPowerPath.kicad_sch
@@ -713,16 +713,16 @@
)
)
- (symbol (lib_id "Device:C_Polarized") (at 167.64 95.25 180) (unit 1)
+ (symbol (lib_id "Device:C_Polarized") (at 167.64 95.25 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid 711b23a3-9e4b-407c-98bf-b83d983fc254)
- (property "Reference" "neg_out_cap" (at 168.91 92.71 0)
+ (property "Reference" "neg_out_cap" (at 180.34 97.79 0)
(effects (font (size 1.27 1.27)) (justify right))
)
- (property "Value" "~" (at 171.45 97.4089 0)
+ (property "Value" "~" (at 163.83 93.0911 0)
(effects (font (size 1.27 1.27)) (justify right))
)
- (property "Footprint" "" (at 166.6748 91.44 0)
+ (property "Footprint" "" (at 168.6052 99.06 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (at 167.64 95.25 0)
@@ -871,7 +871,7 @@
(symbol (lib_id "Device:D") (at 161.29 99.06 180) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid c6008751-7ab3-4ec8-a283-86da5aced9e3)
- (property "Reference" "boot_gnd_diode" (at 161.29 96.52 0)
+ (property "Reference" "boot_gnd_diode" (at 161.29 101.6 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "~" (at 161.29 95.25 0)
diff --git a/examples/BasicKeyboard/BasicKeyboard.net b/examples/BasicKeyboard/BasicKeyboard.net
index ff6a1ef1e..64431a0c0 100644
--- a/examples/BasicKeyboard/BasicKeyboard.net
+++ b/examples/BasicKeyboard/BasicKeyboard.net
@@ -168,7 +168,7 @@
(node (ref sw.d[1,2]) (pin 2)))
(net (code 6) (name "mcu.pwr_out")
(node (ref mcu) (pin 12)))
-(net (code 7) (name "mcu.gnd_out")
+(net (code 7) (name "mcu.gnd")
(node (ref mcu) (pin 13)))
(net (code 8) (name "mcu.vusb_out")
(node (ref mcu) (pin 14)))
diff --git a/examples/BasicKeyboard/BasicKeyboard.ref.net b/examples/BasicKeyboard/BasicKeyboard.ref.net
index 9900a66ec..93fdf0616 100644
--- a/examples/BasicKeyboard/BasicKeyboard.ref.net
+++ b/examples/BasicKeyboard/BasicKeyboard.ref.net
@@ -168,7 +168,7 @@
(node (ref D6) (pin 2)))
(net (code 6) (name "mcu.pwr_out")
(node (ref U1) (pin 12)))
-(net (code 7) (name "mcu.gnd_out")
+(net (code 7) (name "mcu.gnd")
(node (ref U1) (pin 13)))
(net (code 8) (name "mcu.vusb_out")
(node (ref U1) (pin 14)))
diff --git a/examples/BldcController/BldcController.net b/examples/BldcController/BldcController.net
index e891d5de8..eb5cdb610 100644
--- a/examples/BldcController/BldcController.net
+++ b/examples/BldcController/BldcController.net
@@ -528,6 +528,39 @@
(property (name "edg_part") (value "CC0603KRX7R9BB104 (YAGEO)"))
(sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
(tstamps "0b9a02dd"))
+(comp (ref "bldc_drv.pgnd_res[1]")
+ (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
+ (footprint "Resistor_SMD:R_2512_6332Metric")
+ (property (name "Sheetname") (value "bldc_drv"))
+ (property (name "Sheetfile") (value "edg.parts.Bldc_Drv8313.Drv8313"))
+ (property (name "edg_path") (value "bldc_drv.pgnd_res[1].res.res"))
+ (property (name "edg_short_path") (value "bldc_drv.pgnd_res[1]"))
+ (property (name "edg_refdes") (value "R19"))
+ (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
+ (sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
+ (tstamps "1ab9043c"))
+(comp (ref "bldc_drv.pgnd_res[2]")
+ (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
+ (footprint "Resistor_SMD:R_2512_6332Metric")
+ (property (name "Sheetname") (value "bldc_drv"))
+ (property (name "Sheetfile") (value "edg.parts.Bldc_Drv8313.Drv8313"))
+ (property (name "edg_path") (value "bldc_drv.pgnd_res[2].res.res"))
+ (property (name "edg_short_path") (value "bldc_drv.pgnd_res[2]"))
+ (property (name "edg_refdes") (value "R20"))
+ (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
+ (sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
+ (tstamps "1abb043d"))
+(comp (ref "bldc_drv.pgnd_res[3]")
+ (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
+ (footprint "Resistor_SMD:R_2512_6332Metric")
+ (property (name "Sheetname") (value "bldc_drv"))
+ (property (name "Sheetfile") (value "edg.parts.Bldc_Drv8313.Drv8313"))
+ (property (name "edg_path") (value "bldc_drv.pgnd_res[3].res.res"))
+ (property (name "edg_short_path") (value "bldc_drv.pgnd_res[3]"))
+ (property (name "edg_refdes") (value "R21"))
+ (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
+ (sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
+ (tstamps "1abd043e"))
(comp (ref "bldc_fault_tp")
(value "_mcu_gpio_bldc_fault_link")
(footprint "edg:TestPoint_TE_RCT_0805")
@@ -616,17 +649,6 @@
(property (name "edg_part") (value "B3B-PH-K (JST)"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "03fb0196"))
-(comp (ref "curr[1]")
- (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
- (footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "curr[1].res.res"))
- (property (name "edg_short_path") (value "curr[1]"))
- (property (name "edg_refdes") (value "R19"))
- (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "0b4c02a6"))
(comp (ref "curr_amp[1].amp.ic")
(value "LMV321")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -656,7 +678,7 @@
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[1].r1"))
(property (name "edg_short_path") (value "curr_amp[1].r1"))
- (property (name "edg_refdes") (value "R20"))
+ (property (name "edg_refdes") (value "R22"))
(property (name "edg_part") (value "0603WAF3903T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[1]/") (tstamps "/1b000443/"))
(tstamps "011700a4"))
@@ -667,7 +689,7 @@
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[1].r2"))
(property (name "edg_short_path") (value "curr_amp[1].r2"))
- (property (name "edg_refdes") (value "R21"))
+ (property (name "edg_refdes") (value "R23"))
(property (name "edg_part") (value "0603WAF2002T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[1]/") (tstamps "/1b000443/"))
(tstamps "011800a5"))
@@ -682,17 +704,6 @@
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "16c103e9"))
-(comp (ref "curr[2]")
- (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
- (footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "curr[2].res.res"))
- (property (name "edg_short_path") (value "curr[2]"))
- (property (name "edg_refdes") (value "R22"))
- (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "0b4e02a7"))
(comp (ref "curr_amp[2].amp.ic")
(value "LMV321")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -722,7 +733,7 @@
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[2].r1"))
(property (name "edg_short_path") (value "curr_amp[2].r1"))
- (property (name "edg_refdes") (value "R23"))
+ (property (name "edg_refdes") (value "R24"))
(property (name "edg_part") (value "0603WAF3903T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[2]/") (tstamps "/1b020444/"))
(tstamps "011700a4"))
@@ -733,7 +744,7 @@
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[2].r2"))
(property (name "edg_short_path") (value "curr_amp[2].r2"))
- (property (name "edg_refdes") (value "R24"))
+ (property (name "edg_refdes") (value "R25"))
(property (name "edg_part") (value "0603WAF2002T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[2]/") (tstamps "/1b020444/"))
(tstamps "011800a5"))
@@ -748,17 +759,6 @@
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "16c303ea"))
-(comp (ref "curr[3]")
- (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
- (footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "curr[3].res.res"))
- (property (name "edg_short_path") (value "curr[3]"))
- (property (name "edg_refdes") (value "R25"))
- (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "0b5002a8"))
(comp (ref "curr_amp[3].amp.ic")
(value "LMV321")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -837,6 +837,7 @@
(node (ref curr_amp[3].amp.vdd_cap) (pin 1)))
(net (code 3) (name "gnd")
(node (ref mcu) (pin 4))
+ (node (ref motor_pwr) (pin 1))
(node (ref sw1) (pin 2))
(node (ref ledr.res) (pin 2))
(node (ref ledg.res) (pin 2))
@@ -854,11 +855,7 @@
(node (ref ref_div.bottom_res) (pin 2))
(node (ref ref_buf.ic) (pin 2))
(node (ref vsense.bottom_res) (pin 2))
- (node (ref curr[1]) (pin 1))
- (node (ref curr[2]) (pin 1))
- (node (ref curr[3]) (pin 1))
(node (ref isense.amp.amp.ic) (pin 4))
- (node (ref motor_pwr) (pin 1))
(node (ref curr_amp[1].r2) (pin 2))
(node (ref curr_amp[2].r2) (pin 2))
(node (ref curr_amp[3].r2) (pin 2))
@@ -871,6 +868,9 @@
(node (ref curr_amp[3].amp.ic) (pin 2))
(node (ref ref_buf.vdd_cap) (pin 2))
(node (ref isense.amp.amp.vdd_cap) (pin 2))
+ (node (ref bldc_drv.pgnd_res[1]) (pin 1))
+ (node (ref bldc_drv.pgnd_res[2]) (pin 1))
+ (node (ref bldc_drv.pgnd_res[3]) (pin 1))
(node (ref curr_amp[1].amp.vdd_cap) (pin 2))
(node (ref curr_amp[2].amp.vdd_cap) (pin 2))
(node (ref curr_amp[3].amp.vdd_cap) (pin 2)))
@@ -989,28 +989,28 @@
(net (code 30) (name "bldc_drv.outs.3")
(node (ref bldc_drv.ic) (pin 9))
(node (ref bldc) (pin 3)))
-(net (code 31) (name "curr[1].pwr_out")
- (node (ref bldc_drv.ic) (pin 6))
- (node (ref curr[1]) (pin 2))
- (node (ref curr_amp[1].amp.ic) (pin 1)))
+(net (code 31) (name "curr_amp[1].input")
+ (node (ref curr_amp[1].amp.ic) (pin 1))
+ (node (ref bldc_drv.pgnd_res[1]) (pin 2))
+ (node (ref bldc_drv.ic) (pin 6)))
(net (code 32) (name "curr_amp[1].output")
(node (ref mcu) (pin 10))
(node (ref curr_tp[1]) (pin 1))
(node (ref curr_amp[1].r1) (pin 1))
(node (ref curr_amp[1].amp.ic) (pin 4)))
-(net (code 33) (name "curr[2].pwr_out")
- (node (ref bldc_drv.ic) (pin 7))
- (node (ref curr[2]) (pin 2))
- (node (ref curr_amp[2].amp.ic) (pin 1)))
+(net (code 33) (name "curr_amp[2].input")
+ (node (ref curr_amp[2].amp.ic) (pin 1))
+ (node (ref bldc_drv.pgnd_res[2]) (pin 2))
+ (node (ref bldc_drv.ic) (pin 7)))
(net (code 34) (name "curr_amp[2].output")
(node (ref mcu) (pin 9))
(node (ref curr_tp[2]) (pin 1))
(node (ref curr_amp[2].r1) (pin 1))
(node (ref curr_amp[2].amp.ic) (pin 4)))
-(net (code 35) (name "curr[3].pwr_out")
- (node (ref bldc_drv.ic) (pin 10))
- (node (ref curr[3]) (pin 2))
- (node (ref curr_amp[3].amp.ic) (pin 1)))
+(net (code 35) (name "curr_amp[3].input")
+ (node (ref curr_amp[3].amp.ic) (pin 1))
+ (node (ref bldc_drv.pgnd_res[3]) (pin 2))
+ (node (ref bldc_drv.ic) (pin 10)))
(net (code 36) (name "curr_amp[3].output")
(node (ref mcu) (pin 8))
(node (ref curr_tp[3]) (pin 1))
diff --git a/examples/BldcController/BldcController.ref.net b/examples/BldcController/BldcController.ref.net
index 4ad372fe9..4bb9412f3 100644
--- a/examples/BldcController/BldcController.ref.net
+++ b/examples/BldcController/BldcController.ref.net
@@ -528,6 +528,39 @@
(property (name "edg_part") (value "CC0603KRX7R9BB104 (YAGEO)"))
(sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
(tstamps "0b9a02dd"))
+(comp (ref "R19")
+ (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
+ (footprint "Resistor_SMD:R_2512_6332Metric")
+ (property (name "Sheetname") (value "bldc_drv"))
+ (property (name "Sheetfile") (value "edg.parts.Bldc_Drv8313.Drv8313"))
+ (property (name "edg_path") (value "bldc_drv.pgnd_res[1].res.res"))
+ (property (name "edg_short_path") (value "bldc_drv.pgnd_res[1]"))
+ (property (name "edg_refdes") (value "R19"))
+ (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
+ (sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
+ (tstamps "1ab9043c"))
+(comp (ref "R20")
+ (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
+ (footprint "Resistor_SMD:R_2512_6332Metric")
+ (property (name "Sheetname") (value "bldc_drv"))
+ (property (name "Sheetfile") (value "edg.parts.Bldc_Drv8313.Drv8313"))
+ (property (name "edg_path") (value "bldc_drv.pgnd_res[2].res.res"))
+ (property (name "edg_short_path") (value "bldc_drv.pgnd_res[2]"))
+ (property (name "edg_refdes") (value "R20"))
+ (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
+ (sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
+ (tstamps "1abb043d"))
+(comp (ref "R21")
+ (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
+ (footprint "Resistor_SMD:R_2512_6332Metric")
+ (property (name "Sheetname") (value "bldc_drv"))
+ (property (name "Sheetfile") (value "edg.parts.Bldc_Drv8313.Drv8313"))
+ (property (name "edg_path") (value "bldc_drv.pgnd_res[3].res.res"))
+ (property (name "edg_short_path") (value "bldc_drv.pgnd_res[3]"))
+ (property (name "edg_refdes") (value "R21"))
+ (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
+ (sheetpath (names "/bldc_drv/") (tstamps "/0e550341/"))
+ (tstamps "1abd043e"))
(comp (ref "TP9")
(value "_mcu_gpio_bldc_fault_link")
(footprint "edg:TestPoint_TE_RCT_0805")
@@ -616,17 +649,6 @@
(property (name "edg_part") (value "B3B-PH-K (JST)"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "03fb0196"))
-(comp (ref "R19")
- (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
- (footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "curr[1].res.res"))
- (property (name "edg_short_path") (value "curr[1]"))
- (property (name "edg_refdes") (value "R19"))
- (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "0b4c02a6"))
(comp (ref "U5")
(value "LMV321")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -649,25 +671,25 @@
(property (name "edg_part") (value "CC0603KRX7R9BB104 (YAGEO)"))
(sheetpath (names "/curr_amp[1]/amp/") (tstamps "/1b000443/0270013f/"))
(tstamps "0b6402d2"))
-(comp (ref "R20")
+(comp (ref "R22")
(value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 390kΩ 0603 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_0603_1608Metric")
(property (name "Sheetname") (value "curr_amp[1]"))
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[1].r1"))
(property (name "edg_short_path") (value "curr_amp[1].r1"))
- (property (name "edg_refdes") (value "R20"))
+ (property (name "edg_refdes") (value "R22"))
(property (name "edg_part") (value "0603WAF3903T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[1]/") (tstamps "/1b000443/"))
(tstamps "011700a4"))
-(comp (ref "R21")
+(comp (ref "R23")
(value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 20kΩ 0603 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_0603_1608Metric")
(property (name "Sheetname") (value "curr_amp[1]"))
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[1].r2"))
(property (name "edg_short_path") (value "curr_amp[1].r2"))
- (property (name "edg_refdes") (value "R21"))
+ (property (name "edg_refdes") (value "R23"))
(property (name "edg_part") (value "0603WAF2002T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[1]/") (tstamps "/1b000443/"))
(tstamps "011800a5"))
@@ -682,17 +704,6 @@
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "16c103e9"))
-(comp (ref "R22")
- (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
- (footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "curr[2].res.res"))
- (property (name "edg_short_path") (value "curr[2]"))
- (property (name "edg_refdes") (value "R22"))
- (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "0b4e02a7"))
(comp (ref "U6")
(value "LMV321")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -715,25 +726,25 @@
(property (name "edg_part") (value "CC0603KRX7R9BB104 (YAGEO)"))
(sheetpath (names "/curr_amp[2]/amp/") (tstamps "/1b020444/0270013f/"))
(tstamps "0b6402d2"))
-(comp (ref "R23")
+(comp (ref "R24")
(value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 390kΩ 0603 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_0603_1608Metric")
(property (name "Sheetname") (value "curr_amp[2]"))
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[2].r1"))
(property (name "edg_short_path") (value "curr_amp[2].r1"))
- (property (name "edg_refdes") (value "R23"))
+ (property (name "edg_refdes") (value "R24"))
(property (name "edg_part") (value "0603WAF3903T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[2]/") (tstamps "/1b020444/"))
(tstamps "011700a4"))
-(comp (ref "R24")
+(comp (ref "R25")
(value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 20kΩ 0603 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_0603_1608Metric")
(property (name "Sheetname") (value "curr_amp[2]"))
(property (name "Sheetfile") (value "edg.abstract_parts.OpampCircuits.Amplifier"))
(property (name "edg_path") (value "curr_amp[2].r2"))
(property (name "edg_short_path") (value "curr_amp[2].r2"))
- (property (name "edg_refdes") (value "R24"))
+ (property (name "edg_refdes") (value "R25"))
(property (name "edg_part") (value "0603WAF2002T5E (UNI-ROYAL(Uniroyal Elec))"))
(sheetpath (names "/curr_amp[2]/") (tstamps "/1b020444/"))
(tstamps "011800a5"))
@@ -748,17 +759,6 @@
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
(tstamps "16c303ea"))
-(comp (ref "R25")
- (value "±5% 1W Thick Film Resistors 200V ±800ppm/℃ -55℃~+155℃ 50mΩ 2512 Chip Resistor - Surface Mount ROHS")
- (footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "curr[3].res.res"))
- (property (name "edg_short_path") (value "curr[3]"))
- (property (name "edg_refdes") (value "R25"))
- (property (name "edg_part") (value "25121WJ050LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "0b5002a8"))
(comp (ref "U7")
(value "LMV321")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -837,6 +837,7 @@
(node (ref C11) (pin 1)))
(net (code 3) (name "gnd")
(node (ref U1) (pin 4))
+ (node (ref J1) (pin 1))
(node (ref SW1) (pin 2))
(node (ref R1) (pin 2))
(node (ref R2) (pin 2))
@@ -854,13 +855,9 @@
(node (ref R7) (pin 2))
(node (ref U2) (pin 2))
(node (ref R12) (pin 2))
- (node (ref R19) (pin 1))
- (node (ref R22) (pin 1))
- (node (ref R25) (pin 1))
(node (ref U3) (pin 4))
- (node (ref J1) (pin 1))
- (node (ref R21) (pin 2))
- (node (ref R24) (pin 2))
+ (node (ref R23) (pin 2))
+ (node (ref R25) (pin 2))
(node (ref R27) (pin 2))
(node (ref C3) (pin 2))
(node (ref C4) (pin 2))
@@ -871,6 +868,9 @@
(node (ref U7) (pin 2))
(node (ref C1) (pin 2))
(node (ref C2) (pin 2))
+ (node (ref R19) (pin 1))
+ (node (ref R20) (pin 1))
+ (node (ref R21) (pin 1))
(node (ref C9) (pin 2))
(node (ref C10) (pin 2))
(node (ref C11) (pin 2)))
@@ -989,28 +989,28 @@
(net (code 30) (name "bldc_drv.outs.3")
(node (ref U4) (pin 9))
(node (ref J4) (pin 3)))
-(net (code 31) (name "curr[1].pwr_out")
- (node (ref U4) (pin 6))
+(net (code 31) (name "curr_amp[1].input")
+ (node (ref U5) (pin 1))
(node (ref R19) (pin 2))
- (node (ref U5) (pin 1)))
+ (node (ref U4) (pin 6)))
(net (code 32) (name "curr_amp[1].output")
(node (ref U1) (pin 10))
(node (ref TP16) (pin 1))
- (node (ref R20) (pin 1))
+ (node (ref R22) (pin 1))
(node (ref U5) (pin 4)))
-(net (code 33) (name "curr[2].pwr_out")
- (node (ref U4) (pin 7))
- (node (ref R22) (pin 2))
- (node (ref U6) (pin 1)))
+(net (code 33) (name "curr_amp[2].input")
+ (node (ref U6) (pin 1))
+ (node (ref R20) (pin 2))
+ (node (ref U4) (pin 7)))
(net (code 34) (name "curr_amp[2].output")
(node (ref U1) (pin 9))
(node (ref TP17) (pin 1))
- (node (ref R23) (pin 1))
+ (node (ref R24) (pin 1))
(node (ref U6) (pin 4)))
-(net (code 35) (name "curr[3].pwr_out")
- (node (ref U4) (pin 10))
- (node (ref R25) (pin 2))
- (node (ref U7) (pin 1)))
+(net (code 35) (name "curr_amp[3].input")
+ (node (ref U7) (pin 1))
+ (node (ref R21) (pin 2))
+ (node (ref U4) (pin 10)))
(net (code 36) (name "curr_amp[3].output")
(node (ref U1) (pin 8))
(node (ref TP18) (pin 1))
@@ -1048,13 +1048,13 @@
(node (ref U4) (pin 3)))
(net (code 46) (name "bldc_drv.nsleep"))
(net (code 47) (name "curr_amp[1].r2.a")
- (node (ref R21) (pin 1))
+ (node (ref R23) (pin 1))
(node (ref U5) (pin 3))
- (node (ref R20) (pin 2)))
+ (node (ref R22) (pin 2)))
(net (code 48) (name "curr_amp[2].r2.a")
- (node (ref R24) (pin 1))
+ (node (ref R25) (pin 1))
(node (ref U6) (pin 3))
- (node (ref R23) (pin 2)))
+ (node (ref R24) (pin 2)))
(net (code 49) (name "curr_amp[3].r2.a")
(node (ref R27) (pin 1))
(node (ref U7) (pin 3))
diff --git a/examples/Datalogger/Datalogger.net b/examples/Datalogger/Datalogger.net
index bbe5b4dfe..75f4201ef 100644
--- a/examples/Datalogger/Datalogger.net
+++ b/examples/Datalogger/Datalogger.net
@@ -1168,13 +1168,17 @@
(tstamps "175b043f")))
(nets
(net (code 1) (name "gnd")
+ (node (ref pwr_conn) (pin 1))
+ (node (ref pwr_conn) (pin 3))
+ (node (ref bat) (pin 2))
(node (ref sd) (pin 3))
(node (ref sd) (pin 6))
(node (ref sd) (pin SH))
(node (ref ext) (pin 3))
- (node (ref pwr_conn) (pin 1))
- (node (ref pwr_conn) (pin 3))
- (node (ref bat) (pin 2))
+ (node (ref usb_conn.conn) (pin A1))
+ (node (ref usb_conn.conn) (pin B12))
+ (node (ref usb_conn.conn) (pin B1))
+ (node (ref usb_conn.conn) (pin A12))
(node (ref pwr_5v.ic) (pin 1))
(node (ref buffer.cap) (pin 2))
(node (ref pwr_3v3.ic) (pin 1))
@@ -1197,10 +1201,7 @@
(node (ref v12sense.bottom_res) (pin 2))
(node (ref v5sense.bottom_res) (pin 2))
(node (ref vscsense.bottom_res) (pin 2))
- (node (ref usb_conn.conn) (pin A1))
- (node (ref usb_conn.conn) (pin B12))
- (node (ref usb_conn.conn) (pin B1))
- (node (ref usb_conn.conn) (pin A12))
+ (node (ref usb_conn.conn) (pin S1))
(node (ref eink.boost_res) (pin 2))
(node (ref eink.vslr_cap) (pin 2))
(node (ref eink.vdhr_cap) (pin 2))
@@ -1241,7 +1242,8 @@
(node (ref buffer.set.bottom_res) (pin 2))
(node (ref mcu.swd_pull.swclk) (pin 1))
(node (ref can.transceiver.logic_cap) (pin 2))
- (node (ref usb_conn.conn) (pin S1))
+ (node (ref usb_conn.cc_pull.cc1) (pin 1))
+ (node (ref usb_conn.cc_pull.cc2) (pin 1))
(node (ref mcu.swd) (pin 3))
(node (ref mcu.swd) (pin 5))
(node (ref mcu.swd) (pin 9))
@@ -1249,9 +1251,7 @@
(node (ref mcu.crystal.cap_b) (pin 2))
(node (ref pwr_5v.power_path.in_cap) (pin 2))
(node (ref pwr_5v.power_path.out_cap) (pin 2))
- (node (ref buffer.amp.vdd_cap) (pin 2))
- (node (ref usb_conn.cc_pull.cc1) (pin 1))
- (node (ref usb_conn.cc_pull.cc2) (pin 1)))
+ (node (ref buffer.amp.vdd_cap) (pin 2)))
(net (code 2) (name "vin")
(node (ref pwr_conn) (pin 2))
(node (ref pwr_5v.ic) (pin 3))
@@ -1334,205 +1334,205 @@
(net (code 8) (name "can.controller.rxd")
(node (ref mcu.ic) (pin 53))
(node (ref can.transceiver.ic) (pin 2)))
-(net (code 9) (name "can.can_gnd")
- (node (ref can.conn) (pin 3))
- (node (ref can.esd) (pin 3))
- (node (ref can.reg.ic) (pin 2))
- (node (ref can.transceiver.ic) (pin 5))
- (node (ref can.reg.in_cap) (pin 2))
- (node (ref can.reg.out_cap) (pin 2))
- (node (ref can.transceiver.can_cap) (pin 2)))
-(net (code 10) (name "can.can_pwr")
- (node (ref can.conn) (pin 2))
- (node (ref can.can_fuse) (pin 1)))
-(net (code 11) (name "sd.spi.sck")
+(net (code 9) (name "sd.spi.sck")
(node (ref mcu.ic) (pin 17))
(node (ref sd) (pin 5)))
-(net (code 12) (name "sd.spi.mosi")
+(net (code 10) (name "sd.spi.mosi")
(node (ref mcu.ic) (pin 15))
(node (ref sd) (pin 2)))
-(net (code 13) (name "sd.spi.miso")
+(net (code 11) (name "sd.spi.miso")
(node (ref mcu.ic) (pin 19))
(node (ref sd) (pin 7)))
-(net (code 14) (name "sd.cs")
+(net (code 12) (name "sd.cs")
(node (ref mcu.ic) (pin 11))
(node (ref sd) (pin 1)))
-(net (code 15) (name "cd_pull.io")
+(net (code 13) (name "cd_pull.io")
(node (ref mcu.ic) (pin 16))
(node (ref sd) (pin 10))
(node (ref cd_pull) (pin 2)))
-(net (code 16) (name "xbee.data.rx")
+(net (code 14) (name "xbee.data.rx")
(node (ref mcu.ic) (pin 58))
(node (ref xbee.ic) (pin 3)))
-(net (code 17) (name "xbee.data.tx")
+(net (code 15) (name "xbee.data.tx")
(node (ref mcu.ic) (pin 50))
(node (ref xbee.ic) (pin 2)))
-(net (code 18) (name "xbee.associate")
+(net (code 16) (name "xbee.associate")
(node (ref xbee.ic) (pin 15))
(node (ref xbee_assoc.package) (pin 2)))
-(net (code 19) (name "rtc.spi.sck")
+(net (code 17) (name "rtc.spi.sck")
(node (ref mcu.ic) (pin 5))
(node (ref rtc.ic) (pin 1))
(node (ref eink.ic) (pin 12)))
-(net (code 20) (name "rtc.spi.mosi")
+(net (code 18) (name "rtc.spi.mosi")
(node (ref mcu.ic) (pin 6))
(node (ref rtc.ic) (pin 2))
(node (ref eink.ic) (pin 11)))
-(net (code 21) (name "rtc.spi.miso")
+(net (code 19) (name "rtc.spi.miso")
(node (ref mcu.ic) (pin 7))
(node (ref rtc.ic) (pin 3)))
-(net (code 22) (name "rtc.cs")
+(net (code 20) (name "rtc.cs")
(node (ref mcu.ic) (pin 64))
(node (ref rtc.ic) (pin 4)))
-(net (code 23) (name "bat.pwr")
+(net (code 21) (name "bat.pwr")
(node (ref bat) (pin 1))
(node (ref rtc.ic) (pin 15))
(node (ref rtc.vbat_cap) (pin 1)))
-(net (code 24) (name "eink.busy")
+(net (code 22) (name "eink.busy")
(node (ref mcu.ic) (pin 1))
(node (ref eink.ic) (pin 16)))
-(net (code 25) (name "eink.reset")
+(net (code 23) (name "eink.reset")
(node (ref mcu.ic) (pin 2))
(node (ref eink.ic) (pin 15)))
-(net (code 26) (name "eink.dc")
+(net (code 24) (name "eink.dc")
(node (ref mcu.ic) (pin 3))
(node (ref eink.ic) (pin 14)))
-(net (code 27) (name "eink.cs")
+(net (code 25) (name "eink.cs")
(node (ref mcu.ic) (pin 4))
(node (ref eink.ic) (pin 13)))
-(net (code 28) (name "ext.data.rx")
+(net (code 26) (name "ext.data.rx")
(node (ref mcu.ic) (pin 60))
(node (ref ext) (pin 5)))
-(net (code 29) (name "ext.data.tx")
+(net (code 27) (name "ext.data.tx")
(node (ref mcu.ic) (pin 61))
(node (ref ext) (pin 4)))
-(net (code 30) (name "ext.cts")
+(net (code 28) (name "ext.cts")
(node (ref mcu.ic) (pin 62))
(node (ref ext) (pin 1)))
-(net (code 31) (name "ext.rts")
+(net (code 29) (name "ext.rts")
(node (ref mcu.ic) (pin 59))
(node (ref ext) (pin 6)))
-(net (code 32) (name "mcu.gpio.rgb1_red")
+(net (code 30) (name "mcu.gpio.rgb1_red")
(node (ref mcu.ic) (pin 31))
(node (ref rgb1.red_res) (pin 2)))
-(net (code 33) (name "mcu.gpio.rgb1_green")
+(net (code 31) (name "mcu.gpio.rgb1_green")
(node (ref mcu.ic) (pin 32))
(node (ref rgb1.green_res) (pin 2)))
-(net (code 34) (name "mcu.gpio.rgb1_blue")
+(net (code 32) (name "mcu.gpio.rgb1_blue")
(node (ref mcu.ic) (pin 30))
(node (ref rgb1.blue_res) (pin 2)))
-(net (code 35) (name "mcu.gpio.rgb2_red")
+(net (code 33) (name "mcu.gpio.rgb2_red")
(node (ref mcu.ic) (pin 28))
(node (ref rgb2.red_res) (pin 2)))
-(net (code 36) (name "mcu.gpio.rgb2_green")
+(net (code 34) (name "mcu.gpio.rgb2_green")
(node (ref mcu.ic) (pin 29))
(node (ref rgb2.green_res) (pin 2)))
-(net (code 37) (name "mcu.gpio.rgb2_blue")
+(net (code 35) (name "mcu.gpio.rgb2_blue")
(node (ref mcu.ic) (pin 25))
(node (ref rgb2.blue_res) (pin 2)))
-(net (code 38) (name "mcu.gpio.rgb3_red")
+(net (code 36) (name "mcu.gpio.rgb3_red")
(node (ref mcu.ic) (pin 46))
(node (ref rgb3.red_res) (pin 2)))
-(net (code 39) (name "mcu.gpio.rgb3_green")
+(net (code 37) (name "mcu.gpio.rgb3_green")
(node (ref mcu.ic) (pin 39))
(node (ref rgb3.green_res) (pin 2)))
-(net (code 40) (name "mcu.gpio.rgb3_blue")
+(net (code 38) (name "mcu.gpio.rgb3_blue")
(node (ref mcu.ic) (pin 34))
(node (ref rgb3.blue_res) (pin 2)))
-(net (code 41) (name "sw1.out")
+(net (code 39) (name "sw1.out")
(node (ref mcu.ic) (pin 33))
(node (ref sw1) (pin 1))
(node (ref sw1_pull) (pin 2)))
-(net (code 42) (name "sw2.out")
+(net (code 40) (name "sw2.out")
(node (ref mcu.ic) (pin 23))
(node (ref sw2) (pin 1))
(node (ref sw2_pull) (pin 2)))
-(net (code 43) (name "v12sense.output")
+(net (code 41) (name "v12sense.output")
(node (ref mcu.ic) (pin 10))
(node (ref v12sense.top_res) (pin 2))
(node (ref v12sense.bottom_res) (pin 1)))
-(net (code 44) (name "v5sense.output")
+(net (code 42) (name "v5sense.output")
(node (ref mcu.ic) (pin 9))
(node (ref v5sense.top_res) (pin 2))
(node (ref v5sense.bottom_res) (pin 1)))
-(net (code 45) (name "buffer.sc_out")
+(net (code 43) (name "buffer.sc_out")
(node (ref buffer.cap) (pin 1))
(node (ref vscsense.top_res) (pin 1))
(node (ref buffer.fet) (pin 2))
(node (ref buffer.diode) (pin 2)))
-(net (code 46) (name "vscsense.output")
+(net (code 44) (name "vscsense.output")
(node (ref mcu.ic) (pin 8))
(node (ref vscsense.top_res) (pin 2))
(node (ref vscsense.bottom_res) (pin 1)))
-(net (code 47) (name "usb_conn.conn.cc.cc1")
+(net (code 45) (name "usb_conn.conn.cc.cc1")
(node (ref usb_conn.conn) (pin A5))
(node (ref usb_conn.cc_pull.cc1) (pin 2)))
-(net (code 48) (name "usb_conn.conn.cc.cc2")
+(net (code 46) (name "usb_conn.conn.cc.cc2")
(node (ref usb_conn.conn) (pin B5))
(node (ref usb_conn.cc_pull.cc2) (pin 2)))
-(net (code 49) (name "pwr_5v.fb.output")
+(net (code 47) (name "pwr_5v.fb.output")
(node (ref pwr_5v.ic) (pin 4))
(node (ref pwr_5v.fb.top_res) (pin 2))
(node (ref pwr_5v.fb.bottom_res) (pin 1)))
-(net (code 50) (name "pwr_5v.vbst_cap.neg")
+(net (code 48) (name "pwr_5v.vbst_cap.neg")
(node (ref pwr_5v.vbst_cap) (pin 2))
(node (ref pwr_5v.ic) (pin 2))
(node (ref pwr_5v.power_path.inductor) (pin 1)))
-(net (code 51) (name "pwr_5v.vbst_cap.pos")
+(net (code 49) (name "pwr_5v.vbst_cap.pos")
(node (ref pwr_5v.vbst_cap) (pin 1))
(node (ref pwr_5v.ic) (pin 6)))
-(net (code 52) (name "buffer.fet.source")
+(net (code 50) (name "buffer.fet.source")
(node (ref buffer.fet) (pin 3))
(node (ref buffer.sense) (pin 2))
(node (ref buffer.amp.ic) (pin 4)))
-(net (code 53) (name "buffer.set.output")
+(net (code 51) (name "buffer.set.output")
(node (ref buffer.amp.ic) (pin 3))
(node (ref buffer.set.top_res) (pin 2))
(node (ref buffer.set.bottom_res) (pin 1)))
-(net (code 54) (name "buffer.fet.gate")
+(net (code 52) (name "buffer.fet.gate")
(node (ref buffer.fet) (pin 1))
(node (ref buffer.amp.ic) (pin 1)))
-(net (code 55) (name "mcu.xtal_node.xi")
+(net (code 53) (name "mcu.xtal_node.xi")
(node (ref mcu.ic) (pin 36))
(node (ref mcu.crystal.package) (pin 1))
(node (ref mcu.crystal.cap_a) (pin 1)))
-(net (code 56) (name "mcu.xtal_node.xo")
+(net (code 54) (name "mcu.xtal_node.xo")
(node (ref mcu.ic) (pin 35))
(node (ref mcu.crystal.package) (pin 3))
(node (ref mcu.crystal.cap_b) (pin 1)))
-(net (code 57) (name "mcu.swd_node.swdio")
+(net (code 55) (name "mcu.swd_node.swdio")
(node (ref mcu.ic) (pin 44))
(node (ref mcu.swd) (pin 2))
(node (ref mcu.swd_pull.swdio) (pin 2)))
-(net (code 58) (name "mcu.swd_node.swclk")
+(net (code 56) (name "mcu.swd_node.swclk")
(node (ref mcu.ic) (pin 40))
(node (ref mcu.swd) (pin 4))
(node (ref mcu.swd_pull.swclk) (pin 2)))
-(net (code 59) (name "mcu.reset_node")
+(net (code 57) (name "mcu.reset_node")
(node (ref mcu.ic) (pin 45))
(node (ref mcu.swd) (pin 10)))
-(net (code 60) (name "mcu.swd.swo")
+(net (code 58) (name "mcu.swd.swo")
(node (ref mcu.ic) (pin 12))
(node (ref mcu.swd) (pin 6)))
-(net (code 61) (name "mcu.swd.tdi")
+(net (code 59) (name "mcu.swd.tdi")
(node (ref mcu.swd) (pin 8)))
-(net (code 62) (name "mcu.ic.xtal_rtc.xtal_in")
+(net (code 60) (name "mcu.ic.xtal_rtc.xtal_in")
(node (ref mcu.ic) (pin 42)))
-(net (code 63) (name "mcu.ic.xtal_rtc.xtal_out")
+(net (code 61) (name "mcu.ic.xtal_rtc.xtal_out")
(node (ref mcu.ic) (pin 43)))
-(net (code 64) (name "can.can.canh")
+(net (code 62) (name "can.can.canh")
(node (ref can.conn) (pin 4))
(node (ref can.esd) (pin 2))
(node (ref can.transceiver.ic) (pin 7)))
-(net (code 65) (name "can.can.canl")
+(net (code 63) (name "can.can.canl")
(node (ref can.conn) (pin 5))
(node (ref can.esd) (pin 1))
(node (ref can.transceiver.ic) (pin 6)))
-(net (code 66) (name "can.can_fuse.pwr_out")
+(net (code 64) (name "can.conn.pwr")
+ (node (ref can.conn) (pin 2))
+ (node (ref can.can_fuse) (pin 1)))
+(net (code 65) (name "can.can_fuse.pwr_out")
(node (ref can.can_fuse) (pin 2))
(node (ref can.reg.ic) (pin 1))
(node (ref can.reg.ic) (pin 3))
(node (ref can.reg.in_cap) (pin 1)))
+(net (code 66) (name "can.conn.gnd")
+ (node (ref can.conn) (pin 3))
+ (node (ref can.esd) (pin 3))
+ (node (ref can.reg.ic) (pin 2))
+ (node (ref can.transceiver.ic) (pin 5))
+ (node (ref can.reg.in_cap) (pin 2))
+ (node (ref can.reg.out_cap) (pin 2))
+ (node (ref can.transceiver.can_cap) (pin 2)))
(net (code 67) (name "can.transceiver.can_pwr")
(node (ref can.transceiver.ic) (pin 8))
(node (ref can.reg.ic) (pin 5))
diff --git a/examples/Datalogger/Datalogger.ref.net b/examples/Datalogger/Datalogger.ref.net
index e32914a3e..2d5dffe52 100644
--- a/examples/Datalogger/Datalogger.ref.net
+++ b/examples/Datalogger/Datalogger.ref.net
@@ -1168,13 +1168,17 @@
(tstamps "175b043f")))
(nets
(net (code 1) (name "gnd")
+ (node (ref J1) (pin 1))
+ (node (ref J1) (pin 3))
+ (node (ref U1) (pin 2))
(node (ref J5) (pin 3))
(node (ref J5) (pin 6))
(node (ref J5) (pin SH))
(node (ref U12) (pin 3))
- (node (ref J1) (pin 1))
- (node (ref J1) (pin 3))
- (node (ref U1) (pin 2))
+ (node (ref J2) (pin A1))
+ (node (ref J2) (pin B12))
+ (node (ref J2) (pin B1))
+ (node (ref J2) (pin A12))
(node (ref U2) (pin 1))
(node (ref C6) (pin 2))
(node (ref U4) (pin 1))
@@ -1197,10 +1201,7 @@
(node (ref R26) (pin 2))
(node (ref R28) (pin 2))
(node (ref R30) (pin 2))
- (node (ref J2) (pin A1))
- (node (ref J2) (pin B12))
- (node (ref J2) (pin B1))
- (node (ref J2) (pin A12))
+ (node (ref J2) (pin S1))
(node (ref R13) (pin 2))
(node (ref C36) (pin 2))
(node (ref C37) (pin 2))
@@ -1241,7 +1242,8 @@
(node (ref R7) (pin 2))
(node (ref R9) (pin 1))
(node (ref C25) (pin 2))
- (node (ref J2) (pin S1))
+ (node (ref R1) (pin 1))
+ (node (ref R2) (pin 1))
(node (ref J3) (pin 3))
(node (ref J3) (pin 5))
(node (ref J3) (pin 9))
@@ -1249,9 +1251,7 @@
(node (ref C22) (pin 2))
(node (ref C3) (pin 2))
(node (ref C4) (pin 2))
- (node (ref C5) (pin 2))
- (node (ref R1) (pin 1))
- (node (ref R2) (pin 1)))
+ (node (ref C5) (pin 2)))
(net (code 2) (name "vin")
(node (ref J1) (pin 2))
(node (ref U2) (pin 3))
@@ -1334,205 +1334,205 @@
(net (code 8) (name "can.controller.rxd")
(node (ref U5) (pin 53))
(node (ref U8) (pin 2)))
-(net (code 9) (name "can.can_gnd")
- (node (ref J4) (pin 3))
- (node (ref U7) (pin 3))
- (node (ref U6) (pin 2))
- (node (ref U8) (pin 5))
- (node (ref C23) (pin 2))
- (node (ref C24) (pin 2))
- (node (ref C26) (pin 2)))
-(net (code 10) (name "can.can_pwr")
- (node (ref J4) (pin 2))
- (node (ref F1) (pin 1)))
-(net (code 11) (name "sd.spi.sck")
+(net (code 9) (name "sd.spi.sck")
(node (ref U5) (pin 17))
(node (ref J5) (pin 5)))
-(net (code 12) (name "sd.spi.mosi")
+(net (code 10) (name "sd.spi.mosi")
(node (ref U5) (pin 15))
(node (ref J5) (pin 2)))
-(net (code 13) (name "sd.spi.miso")
+(net (code 11) (name "sd.spi.miso")
(node (ref U5) (pin 19))
(node (ref J5) (pin 7)))
-(net (code 14) (name "sd.cs")
+(net (code 12) (name "sd.cs")
(node (ref U5) (pin 11))
(node (ref J5) (pin 1)))
-(net (code 15) (name "cd_pull.io")
+(net (code 13) (name "cd_pull.io")
(node (ref U5) (pin 16))
(node (ref J5) (pin 10))
(node (ref R10) (pin 2)))
-(net (code 16) (name "xbee.data.rx")
+(net (code 14) (name "xbee.data.rx")
(node (ref U5) (pin 58))
(node (ref U9) (pin 3)))
-(net (code 17) (name "xbee.data.tx")
+(net (code 15) (name "xbee.data.tx")
(node (ref U5) (pin 50))
(node (ref U9) (pin 2)))
-(net (code 18) (name "xbee.associate")
+(net (code 16) (name "xbee.associate")
(node (ref U9) (pin 15))
(node (ref D2) (pin 2)))
-(net (code 19) (name "rtc.spi.sck")
+(net (code 17) (name "rtc.spi.sck")
(node (ref U5) (pin 5))
(node (ref U10) (pin 1))
(node (ref U11) (pin 12)))
-(net (code 20) (name "rtc.spi.mosi")
+(net (code 18) (name "rtc.spi.mosi")
(node (ref U5) (pin 6))
(node (ref U10) (pin 2))
(node (ref U11) (pin 11)))
-(net (code 21) (name "rtc.spi.miso")
+(net (code 19) (name "rtc.spi.miso")
(node (ref U5) (pin 7))
(node (ref U10) (pin 3)))
-(net (code 22) (name "rtc.cs")
+(net (code 20) (name "rtc.cs")
(node (ref U5) (pin 64))
(node (ref U10) (pin 4)))
-(net (code 23) (name "bat.pwr")
+(net (code 21) (name "bat.pwr")
(node (ref U1) (pin 1))
(node (ref U10) (pin 15))
(node (ref C31) (pin 1)))
-(net (code 24) (name "eink.busy")
+(net (code 22) (name "eink.busy")
(node (ref U5) (pin 1))
(node (ref U11) (pin 16)))
-(net (code 25) (name "eink.reset")
+(net (code 23) (name "eink.reset")
(node (ref U5) (pin 2))
(node (ref U11) (pin 15)))
-(net (code 26) (name "eink.dc")
+(net (code 24) (name "eink.dc")
(node (ref U5) (pin 3))
(node (ref U11) (pin 14)))
-(net (code 27) (name "eink.cs")
+(net (code 25) (name "eink.cs")
(node (ref U5) (pin 4))
(node (ref U11) (pin 13)))
-(net (code 28) (name "ext.data.rx")
+(net (code 26) (name "ext.data.rx")
(node (ref U5) (pin 60))
(node (ref U12) (pin 5)))
-(net (code 29) (name "ext.data.tx")
+(net (code 27) (name "ext.data.tx")
(node (ref U5) (pin 61))
(node (ref U12) (pin 4)))
-(net (code 30) (name "ext.cts")
+(net (code 28) (name "ext.cts")
(node (ref U5) (pin 62))
(node (ref U12) (pin 1)))
-(net (code 31) (name "ext.rts")
+(net (code 29) (name "ext.rts")
(node (ref U5) (pin 59))
(node (ref U12) (pin 6)))
-(net (code 32) (name "mcu.gpio.rgb1_red")
+(net (code 30) (name "mcu.gpio.rgb1_red")
(node (ref U5) (pin 31))
(node (ref R14) (pin 2)))
-(net (code 33) (name "mcu.gpio.rgb1_green")
+(net (code 31) (name "mcu.gpio.rgb1_green")
(node (ref U5) (pin 32))
(node (ref R15) (pin 2)))
-(net (code 34) (name "mcu.gpio.rgb1_blue")
+(net (code 32) (name "mcu.gpio.rgb1_blue")
(node (ref U5) (pin 30))
(node (ref R16) (pin 2)))
-(net (code 35) (name "mcu.gpio.rgb2_red")
+(net (code 33) (name "mcu.gpio.rgb2_red")
(node (ref U5) (pin 28))
(node (ref R17) (pin 2)))
-(net (code 36) (name "mcu.gpio.rgb2_green")
+(net (code 34) (name "mcu.gpio.rgb2_green")
(node (ref U5) (pin 29))
(node (ref R18) (pin 2)))
-(net (code 37) (name "mcu.gpio.rgb2_blue")
+(net (code 35) (name "mcu.gpio.rgb2_blue")
(node (ref U5) (pin 25))
(node (ref R19) (pin 2)))
-(net (code 38) (name "mcu.gpio.rgb3_red")
+(net (code 36) (name "mcu.gpio.rgb3_red")
(node (ref U5) (pin 46))
(node (ref R20) (pin 2)))
-(net (code 39) (name "mcu.gpio.rgb3_green")
+(net (code 37) (name "mcu.gpio.rgb3_green")
(node (ref U5) (pin 39))
(node (ref R21) (pin 2)))
-(net (code 40) (name "mcu.gpio.rgb3_blue")
+(net (code 38) (name "mcu.gpio.rgb3_blue")
(node (ref U5) (pin 34))
(node (ref R22) (pin 2)))
-(net (code 41) (name "sw1.out")
+(net (code 39) (name "sw1.out")
(node (ref U5) (pin 33))
(node (ref SW1) (pin 1))
(node (ref R23) (pin 2)))
-(net (code 42) (name "sw2.out")
+(net (code 40) (name "sw2.out")
(node (ref U5) (pin 23))
(node (ref SW2) (pin 1))
(node (ref R24) (pin 2)))
-(net (code 43) (name "v12sense.output")
+(net (code 41) (name "v12sense.output")
(node (ref U5) (pin 10))
(node (ref R25) (pin 2))
(node (ref R26) (pin 1)))
-(net (code 44) (name "v5sense.output")
+(net (code 42) (name "v5sense.output")
(node (ref U5) (pin 9))
(node (ref R27) (pin 2))
(node (ref R28) (pin 1)))
-(net (code 45) (name "buffer.sc_out")
+(net (code 43) (name "buffer.sc_out")
(node (ref C6) (pin 1))
(node (ref R29) (pin 1))
(node (ref Q1) (pin 2))
(node (ref D1) (pin 2)))
-(net (code 46) (name "vscsense.output")
+(net (code 44) (name "vscsense.output")
(node (ref U5) (pin 8))
(node (ref R29) (pin 2))
(node (ref R30) (pin 1)))
-(net (code 47) (name "usb_conn.conn.cc.cc1")
+(net (code 45) (name "usb_conn.conn.cc.cc1")
(node (ref J2) (pin A5))
(node (ref R1) (pin 2)))
-(net (code 48) (name "usb_conn.conn.cc.cc2")
+(net (code 46) (name "usb_conn.conn.cc.cc2")
(node (ref J2) (pin B5))
(node (ref R2) (pin 2)))
-(net (code 49) (name "pwr_5v.fb.output")
+(net (code 47) (name "pwr_5v.fb.output")
(node (ref U2) (pin 4))
(node (ref R3) (pin 2))
(node (ref R4) (pin 1)))
-(net (code 50) (name "pwr_5v.vbst_cap.neg")
+(net (code 48) (name "pwr_5v.vbst_cap.neg")
(node (ref C2) (pin 2))
(node (ref U2) (pin 2))
(node (ref L1) (pin 1)))
-(net (code 51) (name "pwr_5v.vbst_cap.pos")
+(net (code 49) (name "pwr_5v.vbst_cap.pos")
(node (ref C2) (pin 1))
(node (ref U2) (pin 6)))
-(net (code 52) (name "buffer.fet.source")
+(net (code 50) (name "buffer.fet.source")
(node (ref Q1) (pin 3))
(node (ref R5) (pin 2))
(node (ref U3) (pin 4)))
-(net (code 53) (name "buffer.set.output")
+(net (code 51) (name "buffer.set.output")
(node (ref U3) (pin 3))
(node (ref R6) (pin 2))
(node (ref R7) (pin 1)))
-(net (code 54) (name "buffer.fet.gate")
+(net (code 52) (name "buffer.fet.gate")
(node (ref Q1) (pin 1))
(node (ref U3) (pin 1)))
-(net (code 55) (name "mcu.xtal_node.xi")
+(net (code 53) (name "mcu.xtal_node.xi")
(node (ref U5) (pin 36))
(node (ref X1) (pin 1))
(node (ref C21) (pin 1)))
-(net (code 56) (name "mcu.xtal_node.xo")
+(net (code 54) (name "mcu.xtal_node.xo")
(node (ref U5) (pin 35))
(node (ref X1) (pin 3))
(node (ref C22) (pin 1)))
-(net (code 57) (name "mcu.swd_node.swdio")
+(net (code 55) (name "mcu.swd_node.swdio")
(node (ref U5) (pin 44))
(node (ref J3) (pin 2))
(node (ref R8) (pin 2)))
-(net (code 58) (name "mcu.swd_node.swclk")
+(net (code 56) (name "mcu.swd_node.swclk")
(node (ref U5) (pin 40))
(node (ref J3) (pin 4))
(node (ref R9) (pin 2)))
-(net (code 59) (name "mcu.reset_node")
+(net (code 57) (name "mcu.reset_node")
(node (ref U5) (pin 45))
(node (ref J3) (pin 10)))
-(net (code 60) (name "mcu.swd.swo")
+(net (code 58) (name "mcu.swd.swo")
(node (ref U5) (pin 12))
(node (ref J3) (pin 6)))
-(net (code 61) (name "mcu.swd.tdi")
+(net (code 59) (name "mcu.swd.tdi")
(node (ref J3) (pin 8)))
-(net (code 62) (name "mcu.ic.xtal_rtc.xtal_in")
+(net (code 60) (name "mcu.ic.xtal_rtc.xtal_in")
(node (ref U5) (pin 42)))
-(net (code 63) (name "mcu.ic.xtal_rtc.xtal_out")
+(net (code 61) (name "mcu.ic.xtal_rtc.xtal_out")
(node (ref U5) (pin 43)))
-(net (code 64) (name "can.can.canh")
+(net (code 62) (name "can.can.canh")
(node (ref J4) (pin 4))
(node (ref U7) (pin 2))
(node (ref U8) (pin 7)))
-(net (code 65) (name "can.can.canl")
+(net (code 63) (name "can.can.canl")
(node (ref J4) (pin 5))
(node (ref U7) (pin 1))
(node (ref U8) (pin 6)))
-(net (code 66) (name "can.can_fuse.pwr_out")
+(net (code 64) (name "can.conn.pwr")
+ (node (ref J4) (pin 2))
+ (node (ref F1) (pin 1)))
+(net (code 65) (name "can.can_fuse.pwr_out")
(node (ref F1) (pin 2))
(node (ref U6) (pin 1))
(node (ref U6) (pin 3))
(node (ref C23) (pin 1)))
+(net (code 66) (name "can.conn.gnd")
+ (node (ref J4) (pin 3))
+ (node (ref U7) (pin 3))
+ (node (ref U6) (pin 2))
+ (node (ref U8) (pin 5))
+ (node (ref C23) (pin 2))
+ (node (ref C24) (pin 2))
+ (node (ref C26) (pin 2)))
(net (code 67) (name "can.transceiver.can_pwr")
(node (ref U8) (pin 8))
(node (ref U6) (pin 5))
diff --git a/examples/Fcml/Fcml.net b/examples/Fcml/Fcml.net
index 4f4039f72..9b1058679 100644
--- a/examples/Fcml/Fcml.net
+++ b/examples/Fcml/Fcml.net
@@ -1956,6 +1956,15 @@
(net (code 2) (name "gnd")
(node (ref usb_fpga_esd) (pin 3))
(node (ref usb_mcu_esd) (pin 3))
+ (node (ref usb_mcu.conn) (pin A1))
+ (node (ref usb_mcu.conn) (pin B12))
+ (node (ref usb_mcu.conn) (pin B1))
+ (node (ref usb_mcu.conn) (pin A12))
+ (node (ref usb_fpga.conn) (pin A1))
+ (node (ref usb_fpga.conn) (pin B12))
+ (node (ref usb_fpga.conn) (pin B1))
+ (node (ref usb_fpga.conn) (pin A12))
+ (node (ref conv_in) (pin 1))
(node (ref tp_gnd) (pin 1))
(node (ref reg_3v3.ic) (pin 1))
(node (ref prot_3v3) (pin 2))
@@ -1971,15 +1980,8 @@
(node (ref mcu_sw) (pin 2))
(node (ref conv_in_sense.bottom_res) (pin 2))
(node (ref conv_out_sense.bottom_res) (pin 2))
- (node (ref usb_mcu.conn) (pin A1))
- (node (ref usb_mcu.conn) (pin B12))
- (node (ref usb_mcu.conn) (pin B1))
- (node (ref usb_mcu.conn) (pin A12))
- (node (ref usb_fpga.conn) (pin A1))
- (node (ref usb_fpga.conn) (pin B12))
- (node (ref usb_fpga.conn) (pin B1))
- (node (ref usb_fpga.conn) (pin A12))
- (node (ref conv_in) (pin 1))
+ (node (ref usb_mcu.conn) (pin S1))
+ (node (ref usb_fpga.conn) (pin S1))
(node (ref reg_3v3.in_cap) (pin 2))
(node (ref reg_3v3.out_cap) (pin 2))
(node (ref fpga.vcc_reg.ic) (pin 2))
@@ -2023,8 +2025,8 @@
(node (ref tp_pwm.elts[1H].c) (pin 2))
(node (ref tp_pwm.elts[2L].c) (pin 2))
(node (ref tp_pwm.elts[2H].c) (pin 2))
- (node (ref usb_mcu.conn) (pin S1))
- (node (ref usb_fpga.conn) (pin S1))
+ (node (ref usb_mcu.cc_pull.cc1) (pin 1))
+ (node (ref usb_mcu.cc_pull.cc2) (pin 1))
(node (ref conv.sw[0].low_fet) (pin 1))
(node (ref conv.sw[0].low_fet) (pin 2))
(node (ref conv.sw[0].low_fet) (pin 3))
@@ -2036,6 +2038,8 @@
(node (ref mcu.swd) (pin 9))
(node (ref mcu.crystal.cap_a) (pin 2))
(node (ref mcu.crystal.cap_b) (pin 2))
+ (node (ref usb_fpga.cc_pull.cc1) (pin 1))
+ (node (ref usb_fpga.cc_pull.cc2) (pin 1))
(node (ref reg_vgate.power_path.in_cap) (pin 2))
(node (ref reg_vgate.power_path.out_cap) (pin 2))
(node (ref conv.sw[0].driver.ic) (pin 4))
@@ -2045,10 +2049,6 @@
(node (ref mcu.mem.vcc_cap) (pin 2))
(node (ref conv.sw[1].iso.cap_a) (pin 2))
(node (ref conv.sw[2].iso.cap_a) (pin 2))
- (node (ref usb_mcu.cc_pull.cc1) (pin 1))
- (node (ref usb_mcu.cc_pull.cc2) (pin 1))
- (node (ref usb_fpga.cc_pull.cc1) (pin 1))
- (node (ref usb_fpga.cc_pull.cc2) (pin 1))
(node (ref conv.power_path.in_cap.c[0]) (pin 2))
(node (ref conv.power_path.in_cap.c[1]) (pin 2))
(node (ref conv.power_path.in_cap.c[2]) (pin 2))
@@ -2296,7 +2296,7 @@
(node (ref reg_vgate.ic) (pin 1))
(node (ref reg_vgate.power_path.inductor) (pin 2))
(node (ref reg_vgate.rect) (pin 2)))
-(net (code 50) (name "conv.sw[1].low_in")
+(net (code 50) (name "conv.sw[0].low_out")
(node (ref conv.sw[0].low_fet) (pin 5))
(node (ref conv.sw[0].low_fet) (pin 6))
(node (ref conv.sw[0].low_fet) (pin 7))
@@ -2333,7 +2333,7 @@
(node (ref conv.sw[1].high_boot_diode) (pin 1))
(node (ref conv.sw[1].driver.ic) (pin 8))
(node (ref conv.sw[1].driver.high_cap) (pin 1)))
-(net (code 53) (name "conv.sw[2].low_in")
+(net (code 53) (name "conv.sw[1].low_out")
(node (ref conv.sw[1].low_fet) (pin 5))
(node (ref conv.sw[1].low_fet) (pin 6))
(node (ref conv.sw[1].low_fet) (pin 7))
diff --git a/examples/Fcml/Fcml.ref.net b/examples/Fcml/Fcml.ref.net
index 72971a55b..c1885ed26 100644
--- a/examples/Fcml/Fcml.ref.net
+++ b/examples/Fcml/Fcml.ref.net
@@ -1956,6 +1956,15 @@
(net (code 2) (name "gnd")
(node (ref U13) (pin 3))
(node (ref U16) (pin 3))
+ (node (ref J1) (pin A1))
+ (node (ref J1) (pin B12))
+ (node (ref J1) (pin B1))
+ (node (ref J1) (pin A12))
+ (node (ref J2) (pin A1))
+ (node (ref J2) (pin B12))
+ (node (ref J2) (pin B1))
+ (node (ref J2) (pin A12))
+ (node (ref J3) (pin 1))
(node (ref TP2) (pin 1))
(node (ref U1) (pin 1))
(node (ref D1) (pin 2))
@@ -1971,15 +1980,8 @@
(node (ref SW2) (pin 2))
(node (ref R37) (pin 2))
(node (ref R39) (pin 2))
- (node (ref J1) (pin A1))
- (node (ref J1) (pin B12))
- (node (ref J1) (pin B1))
- (node (ref J1) (pin A12))
- (node (ref J2) (pin A1))
- (node (ref J2) (pin B12))
- (node (ref J2) (pin B1))
- (node (ref J2) (pin A12))
- (node (ref J3) (pin 1))
+ (node (ref J1) (pin S1))
+ (node (ref J2) (pin S1))
(node (ref C1) (pin 2))
(node (ref C2) (pin 2))
(node (ref U11) (pin 2))
@@ -2023,8 +2025,8 @@
(node (ref C65) (pin 2))
(node (ref C66) (pin 2))
(node (ref C67) (pin 2))
- (node (ref J1) (pin S1))
- (node (ref J2) (pin S1))
+ (node (ref R1) (pin 1))
+ (node (ref R2) (pin 1))
(node (ref Q2) (pin 1))
(node (ref Q2) (pin 2))
(node (ref Q2) (pin 3))
@@ -2036,6 +2038,8 @@
(node (ref J6) (pin 9))
(node (ref C60) (pin 2))
(node (ref C61) (pin 2))
+ (node (ref R3) (pin 1))
+ (node (ref R4) (pin 1))
(node (ref C3) (pin 2))
(node (ref C4) (pin 2))
(node (ref U3) (pin 4))
@@ -2045,10 +2049,6 @@
(node (ref C56) (pin 2))
(node (ref C19) (pin 2))
(node (ref C29) (pin 2))
- (node (ref R1) (pin 1))
- (node (ref R2) (pin 1))
- (node (ref R3) (pin 1))
- (node (ref R4) (pin 1))
(node (ref C5) (pin 2))
(node (ref C6) (pin 2))
(node (ref C7) (pin 2))
@@ -2296,7 +2296,7 @@
(node (ref U2) (pin 1))
(node (ref L1) (pin 2))
(node (ref D2) (pin 2)))
-(net (code 50) (name "conv.sw[1].low_in")
+(net (code 50) (name "conv.sw[0].low_out")
(node (ref Q2) (pin 5))
(node (ref Q2) (pin 6))
(node (ref Q2) (pin 7))
@@ -2333,7 +2333,7 @@
(node (ref D5) (pin 1))
(node (ref U6) (pin 8))
(node (ref C22) (pin 1)))
-(net (code 53) (name "conv.sw[2].low_in")
+(net (code 53) (name "conv.sw[1].low_out")
(node (ref Q4) (pin 5))
(node (ref Q4) (pin 6))
(node (ref Q4) (pin 7))
diff --git a/examples/HighSwitch/HighSwitch.net b/examples/HighSwitch/HighSwitch.net
index 19fed393b..75f2864b6 100644
--- a/examples/HighSwitch/HighSwitch.net
+++ b/examples/HighSwitch/HighSwitch.net
@@ -1106,127 +1106,127 @@
(net (code 5) (name "can_chain_0.rxd")
(node (ref mcu.ic) (pin 44))
(node (ref can.transceiver.ic) (pin 2)))
-(net (code 6) (name "can.can_gnd")
- (node (ref can.conn) (pin 3))
- (node (ref can.esd) (pin 3))
- (node (ref can.reg.ic) (pin 2))
- (node (ref can.transceiver.ic) (pin 5))
- (node (ref can.reg.in_cap) (pin 2))
- (node (ref can.reg.out_cap) (pin 2))
- (node (ref can.transceiver.can_cap) (pin 2)))
-(net (code 7) (name "can.can_pwr")
- (node (ref can.conn) (pin 2))
- (node (ref can.can_fuse) (pin 1)))
-(net (code 8) (name "vsense.output")
+(net (code 6) (name "vsense.output")
(node (ref mcu.ic) (pin 21))
(node (ref vsense.top_res) (pin 2))
(node (ref vsense.bottom_res) (pin 1)))
-(net (code 9) (name "mcu.gpio.rgb1_red")
+(net (code 7) (name "mcu.gpio.rgb1_red")
(node (ref mcu.ic) (pin 28))
(node (ref rgb1.red_res) (pin 2)))
-(net (code 10) (name "mcu.gpio.rgb1_green")
+(net (code 8) (name "mcu.gpio.rgb1_green")
(node (ref mcu.ic) (pin 23))
(node (ref rgb1.green_res) (pin 2)))
-(net (code 11) (name "mcu.gpio.rgb1_blue")
+(net (code 9) (name "mcu.gpio.rgb1_blue")
(node (ref mcu.ic) (pin 22))
(node (ref rgb1.blue_res) (pin 2)))
-(net (code 12) (name "mcu.gpio.rgb2_red")
+(net (code 10) (name "mcu.gpio.rgb2_red")
(node (ref mcu.ic) (pin 18))
(node (ref rgb2.red_res) (pin 2)))
-(net (code 13) (name "mcu.gpio.rgb2_green")
+(net (code 11) (name "mcu.gpio.rgb2_green")
(node (ref mcu.ic) (pin 15))
(node (ref rgb2.green_res) (pin 2)))
-(net (code 14) (name "mcu.gpio.rgb2_blue")
+(net (code 12) (name "mcu.gpio.rgb2_blue")
(node (ref mcu.ic) (pin 13))
(node (ref rgb2.blue_res) (pin 2)))
-(net (code 15) (name "light[0].control[0]")
+(net (code 13) (name "light[0].control[0]")
(node (ref mcu.ic) (pin 12))
(node (ref light[0].drv[0].pre) (pin 1)))
-(net (code 16) (name "light[0].control[1]")
+(net (code 14) (name "light[0].control[1]")
(node (ref mcu.ic) (pin 8))
(node (ref light[0].drv[1].pre) (pin 1)))
-(net (code 17) (name "light[1].control[0]")
+(net (code 15) (name "light[1].control[0]")
(node (ref mcu.ic) (pin 7))
(node (ref light[1].drv[0].pre) (pin 1)))
-(net (code 18) (name "light[1].control[1]")
+(net (code 16) (name "light[1].control[1]")
(node (ref mcu.ic) (pin 6))
(node (ref light[1].drv[1].pre) (pin 1)))
-(net (code 19) (name "light[2].control[0]")
+(net (code 17) (name "light[2].control[0]")
(node (ref mcu.ic) (pin 4))
(node (ref light[2].drv[0].pre) (pin 1)))
-(net (code 20) (name "light[2].control[1]")
+(net (code 18) (name "light[2].control[1]")
(node (ref mcu.ic) (pin 3))
(node (ref light[2].drv[1].pre) (pin 1)))
-(net (code 21) (name "light[3].control[0]")
+(net (code 19) (name "light[3].control[0]")
(node (ref mcu.ic) (pin 2))
(node (ref light[3].drv[0].pre) (pin 1)))
-(net (code 22) (name "light[3].control[1]")
+(net (code 20) (name "light[3].control[1]")
(node (ref mcu.ic) (pin 1))
(node (ref light[3].drv[1].pre) (pin 1)))
-(net (code 23) (name "light[4].control[0]")
+(net (code 21) (name "light[4].control[0]")
(node (ref mcu.ic) (pin 48))
(node (ref light[4].drv[0].pre) (pin 1)))
-(net (code 24) (name "light[4].control[1]")
+(net (code 22) (name "light[4].control[1]")
(node (ref mcu.ic) (pin 47))
(node (ref light[4].drv[1].pre) (pin 1)))
-(net (code 25) (name "light[5].control[0]")
+(net (code 23) (name "light[5].control[0]")
(node (ref mcu.ic) (pin 46))
(node (ref light[5].drv[0].pre) (pin 1)))
-(net (code 26) (name "light[5].control[1]")
+(net (code 24) (name "light[5].control[1]")
(node (ref mcu.ic) (pin 45))
(node (ref light[5].drv[1].pre) (pin 1)))
-(net (code 27) (name "pwr.fb.output")
+(net (code 25) (name "pwr.fb.output")
(node (ref pwr.ic) (pin 4))
(node (ref pwr.fb.top_res) (pin 2))
(node (ref pwr.fb.bottom_res) (pin 1)))
-(net (code 28) (name "pwr.vbst_cap.neg")
+(net (code 26) (name "pwr.vbst_cap.neg")
(node (ref pwr.vbst_cap) (pin 2))
(node (ref pwr.ic) (pin 2))
(node (ref pwr.power_path.inductor) (pin 1)))
-(net (code 29) (name "pwr.vbst_cap.pos")
+(net (code 27) (name "pwr.vbst_cap.pos")
(node (ref pwr.vbst_cap) (pin 1))
(node (ref pwr.ic) (pin 6)))
-(net (code 30) (name "mcu.xtal_node.xi")
+(net (code 28) (name "mcu.xtal_node.xi")
(node (ref mcu.ic) (pin 26))
(node (ref mcu.crystal.package) (pin 1))
(node (ref mcu.crystal.cap_a) (pin 1)))
-(net (code 31) (name "mcu.xtal_node.xo")
+(net (code 29) (name "mcu.xtal_node.xo")
(node (ref mcu.ic) (pin 25))
(node (ref mcu.crystal.package) (pin 3))
(node (ref mcu.crystal.cap_b) (pin 1)))
-(net (code 32) (name "mcu.swd_node.swdio")
+(net (code 30) (name "mcu.swd_node.swdio")
(node (ref mcu.ic) (pin 33))
(node (ref mcu.swd) (pin 2))
(node (ref mcu.swd_pull.swdio) (pin 2)))
-(net (code 33) (name "mcu.swd_node.swclk")
+(net (code 31) (name "mcu.swd_node.swclk")
(node (ref mcu.ic) (pin 29))
(node (ref mcu.swd) (pin 4))
(node (ref mcu.swd_pull.swclk) (pin 2)))
-(net (code 34) (name "mcu.reset_node")
+(net (code 32) (name "mcu.reset_node")
(node (ref mcu.ic) (pin 34))
(node (ref mcu.swd) (pin 10)))
-(net (code 35) (name "mcu.swd.swo")
+(net (code 33) (name "mcu.swd.swo")
(node (ref mcu.ic) (pin 9))
(node (ref mcu.swd) (pin 6)))
-(net (code 36) (name "mcu.swd.tdi")
+(net (code 34) (name "mcu.swd.tdi")
(node (ref mcu.swd) (pin 8)))
-(net (code 37) (name "mcu.ic.xtal_rtc.xtal_in")
+(net (code 35) (name "mcu.ic.xtal_rtc.xtal_in")
(node (ref mcu.ic) (pin 31)))
-(net (code 38) (name "mcu.ic.xtal_rtc.xtal_out")
+(net (code 36) (name "mcu.ic.xtal_rtc.xtal_out")
(node (ref mcu.ic) (pin 32)))
-(net (code 39) (name "can.can.canh")
+(net (code 37) (name "can.can.canh")
(node (ref can.conn) (pin 4))
(node (ref can.esd) (pin 2))
(node (ref can.transceiver.ic) (pin 7)))
-(net (code 40) (name "can.can.canl")
+(net (code 38) (name "can.can.canl")
(node (ref can.conn) (pin 5))
(node (ref can.esd) (pin 1))
(node (ref can.transceiver.ic) (pin 6)))
-(net (code 41) (name "can.can_fuse.pwr_out")
+(net (code 39) (name "can.conn.pwr")
+ (node (ref can.conn) (pin 2))
+ (node (ref can.can_fuse) (pin 1)))
+(net (code 40) (name "can.can_fuse.pwr_out")
(node (ref can.can_fuse) (pin 2))
(node (ref can.reg.ic) (pin 1))
(node (ref can.reg.ic) (pin 3))
(node (ref can.reg.in_cap) (pin 1)))
+(net (code 41) (name "can.conn.gnd")
+ (node (ref can.conn) (pin 3))
+ (node (ref can.esd) (pin 3))
+ (node (ref can.reg.ic) (pin 2))
+ (node (ref can.transceiver.ic) (pin 5))
+ (node (ref can.reg.in_cap) (pin 2))
+ (node (ref can.reg.out_cap) (pin 2))
+ (node (ref can.transceiver.can_cap) (pin 2)))
(net (code 42) (name "can.transceiver.can_pwr")
(node (ref can.transceiver.ic) (pin 8))
(node (ref can.reg.ic) (pin 5))
diff --git a/examples/HighSwitch/HighSwitch.ref.net b/examples/HighSwitch/HighSwitch.ref.net
index 1182d4a45..419e071e5 100644
--- a/examples/HighSwitch/HighSwitch.ref.net
+++ b/examples/HighSwitch/HighSwitch.ref.net
@@ -1106,127 +1106,127 @@
(net (code 5) (name "can_chain_0.rxd")
(node (ref U2) (pin 44))
(node (ref U5) (pin 2)))
-(net (code 6) (name "can.can_gnd")
- (node (ref J3) (pin 3))
- (node (ref U4) (pin 3))
- (node (ref U3) (pin 2))
- (node (ref U5) (pin 5))
- (node (ref C19) (pin 2))
- (node (ref C20) (pin 2))
- (node (ref C22) (pin 2)))
-(net (code 7) (name "can.can_pwr")
- (node (ref J3) (pin 2))
- (node (ref F1) (pin 1)))
-(net (code 8) (name "vsense.output")
+(net (code 6) (name "vsense.output")
(node (ref U2) (pin 21))
(node (ref R5) (pin 2))
(node (ref R6) (pin 1)))
-(net (code 9) (name "mcu.gpio.rgb1_red")
+(net (code 7) (name "mcu.gpio.rgb1_red")
(node (ref U2) (pin 28))
(node (ref R7) (pin 2)))
-(net (code 10) (name "mcu.gpio.rgb1_green")
+(net (code 8) (name "mcu.gpio.rgb1_green")
(node (ref U2) (pin 23))
(node (ref R8) (pin 2)))
-(net (code 11) (name "mcu.gpio.rgb1_blue")
+(net (code 9) (name "mcu.gpio.rgb1_blue")
(node (ref U2) (pin 22))
(node (ref R9) (pin 2)))
-(net (code 12) (name "mcu.gpio.rgb2_red")
+(net (code 10) (name "mcu.gpio.rgb2_red")
(node (ref U2) (pin 18))
(node (ref R10) (pin 2)))
-(net (code 13) (name "mcu.gpio.rgb2_green")
+(net (code 11) (name "mcu.gpio.rgb2_green")
(node (ref U2) (pin 15))
(node (ref R11) (pin 2)))
-(net (code 14) (name "mcu.gpio.rgb2_blue")
+(net (code 12) (name "mcu.gpio.rgb2_blue")
(node (ref U2) (pin 13))
(node (ref R12) (pin 2)))
-(net (code 15) (name "light[0].control[0]")
+(net (code 13) (name "light[0].control[0]")
(node (ref U2) (pin 12))
(node (ref Q1) (pin 1)))
-(net (code 16) (name "light[0].control[1]")
+(net (code 14) (name "light[0].control[1]")
(node (ref U2) (pin 8))
(node (ref Q3) (pin 1)))
-(net (code 17) (name "light[1].control[0]")
+(net (code 15) (name "light[1].control[0]")
(node (ref U2) (pin 7))
(node (ref Q5) (pin 1)))
-(net (code 18) (name "light[1].control[1]")
+(net (code 16) (name "light[1].control[1]")
(node (ref U2) (pin 6))
(node (ref Q7) (pin 1)))
-(net (code 19) (name "light[2].control[0]")
+(net (code 17) (name "light[2].control[0]")
(node (ref U2) (pin 4))
(node (ref Q9) (pin 1)))
-(net (code 20) (name "light[2].control[1]")
+(net (code 18) (name "light[2].control[1]")
(node (ref U2) (pin 3))
(node (ref Q11) (pin 1)))
-(net (code 21) (name "light[3].control[0]")
+(net (code 19) (name "light[3].control[0]")
(node (ref U2) (pin 2))
(node (ref Q13) (pin 1)))
-(net (code 22) (name "light[3].control[1]")
+(net (code 20) (name "light[3].control[1]")
(node (ref U2) (pin 1))
(node (ref Q15) (pin 1)))
-(net (code 23) (name "light[4].control[0]")
+(net (code 21) (name "light[4].control[0]")
(node (ref U2) (pin 48))
(node (ref Q17) (pin 1)))
-(net (code 24) (name "light[4].control[1]")
+(net (code 22) (name "light[4].control[1]")
(node (ref U2) (pin 47))
(node (ref Q19) (pin 1)))
-(net (code 25) (name "light[5].control[0]")
+(net (code 23) (name "light[5].control[0]")
(node (ref U2) (pin 46))
(node (ref Q21) (pin 1)))
-(net (code 26) (name "light[5].control[1]")
+(net (code 24) (name "light[5].control[1]")
(node (ref U2) (pin 45))
(node (ref Q23) (pin 1)))
-(net (code 27) (name "pwr.fb.output")
+(net (code 25) (name "pwr.fb.output")
(node (ref U1) (pin 4))
(node (ref R1) (pin 2))
(node (ref R2) (pin 1)))
-(net (code 28) (name "pwr.vbst_cap.neg")
+(net (code 26) (name "pwr.vbst_cap.neg")
(node (ref C2) (pin 2))
(node (ref U1) (pin 2))
(node (ref L1) (pin 1)))
-(net (code 29) (name "pwr.vbst_cap.pos")
+(net (code 27) (name "pwr.vbst_cap.pos")
(node (ref C2) (pin 1))
(node (ref U1) (pin 6)))
-(net (code 30) (name "mcu.xtal_node.xi")
+(net (code 28) (name "mcu.xtal_node.xi")
(node (ref U2) (pin 26))
(node (ref X1) (pin 1))
(node (ref C17) (pin 1)))
-(net (code 31) (name "mcu.xtal_node.xo")
+(net (code 29) (name "mcu.xtal_node.xo")
(node (ref U2) (pin 25))
(node (ref X1) (pin 3))
(node (ref C18) (pin 1)))
-(net (code 32) (name "mcu.swd_node.swdio")
+(net (code 30) (name "mcu.swd_node.swdio")
(node (ref U2) (pin 33))
(node (ref J2) (pin 2))
(node (ref R3) (pin 2)))
-(net (code 33) (name "mcu.swd_node.swclk")
+(net (code 31) (name "mcu.swd_node.swclk")
(node (ref U2) (pin 29))
(node (ref J2) (pin 4))
(node (ref R4) (pin 2)))
-(net (code 34) (name "mcu.reset_node")
+(net (code 32) (name "mcu.reset_node")
(node (ref U2) (pin 34))
(node (ref J2) (pin 10)))
-(net (code 35) (name "mcu.swd.swo")
+(net (code 33) (name "mcu.swd.swo")
(node (ref U2) (pin 9))
(node (ref J2) (pin 6)))
-(net (code 36) (name "mcu.swd.tdi")
+(net (code 34) (name "mcu.swd.tdi")
(node (ref J2) (pin 8)))
-(net (code 37) (name "mcu.ic.xtal_rtc.xtal_in")
+(net (code 35) (name "mcu.ic.xtal_rtc.xtal_in")
(node (ref U2) (pin 31)))
-(net (code 38) (name "mcu.ic.xtal_rtc.xtal_out")
+(net (code 36) (name "mcu.ic.xtal_rtc.xtal_out")
(node (ref U2) (pin 32)))
-(net (code 39) (name "can.can.canh")
+(net (code 37) (name "can.can.canh")
(node (ref J3) (pin 4))
(node (ref U4) (pin 2))
(node (ref U5) (pin 7)))
-(net (code 40) (name "can.can.canl")
+(net (code 38) (name "can.can.canl")
(node (ref J3) (pin 5))
(node (ref U4) (pin 1))
(node (ref U5) (pin 6)))
-(net (code 41) (name "can.can_fuse.pwr_out")
+(net (code 39) (name "can.conn.pwr")
+ (node (ref J3) (pin 2))
+ (node (ref F1) (pin 1)))
+(net (code 40) (name "can.can_fuse.pwr_out")
(node (ref F1) (pin 2))
(node (ref U3) (pin 1))
(node (ref U3) (pin 3))
(node (ref C19) (pin 1)))
+(net (code 41) (name "can.conn.gnd")
+ (node (ref J3) (pin 3))
+ (node (ref U4) (pin 3))
+ (node (ref U3) (pin 2))
+ (node (ref U5) (pin 5))
+ (node (ref C19) (pin 2))
+ (node (ref C20) (pin 2))
+ (node (ref C22) (pin 2)))
(net (code 42) (name "can.transceiver.can_pwr")
(node (ref U5) (pin 8))
(node (ref U3) (pin 5))
diff --git a/examples/IotDisplay/IotDisplay.net b/examples/IotDisplay/IotDisplay.net
index e91946a57..ce5da5a5a 100644
--- a/examples/IotDisplay/IotDisplay.net
+++ b/examples/IotDisplay/IotDisplay.net
@@ -830,6 +830,11 @@
(node (ref usb_esd) (pin 3))
(node (ref sd) (pin 6))
(node (ref sd) (pin 11))
+ (node (ref usb) (pin A1))
+ (node (ref usb) (pin B12))
+ (node (ref usb) (pin B1))
+ (node (ref usb) (pin A12))
+ (node (ref batt) (pin 1))
(node (ref tp_gnd) (pin 1))
(node (ref vbat_prot) (pin 1))
(node (ref reg_3v3.ic) (pin 1))
@@ -843,11 +848,7 @@
(node (ref sw) (pin 2))
(node (ref flash.ic) (pin 4))
(node (ref vbat_sense.bottom_res) (pin 2))
- (node (ref usb) (pin A1))
- (node (ref usb) (pin B12))
- (node (ref usb) (pin B1))
- (node (ref usb) (pin A12))
- (node (ref batt) (pin 1))
+ (node (ref usb) (pin S1))
(node (ref epd.gate_pdr) (pin 2))
(node (ref reg_3v3.hf_in_cap) (pin 2))
(node (ref mcu.vcc_cap0) (pin 2))
@@ -856,23 +857,22 @@
(node (ref mcu.boot) (pin 2))
(node (ref epd.vdd_cap) (pin 2))
(node (ref epd.vdd1v8_cap) (pin 2))
- (node (ref epd.vgl_cap) (pin 1))
+ (node (ref epd.vgl_cap) (pin 2))
(node (ref epd.vgh_cap) (pin 2))
(node (ref epd.vsh_cap) (pin 2))
- (node (ref epd.vsl_cap) (pin 1))
+ (node (ref epd.vsl_cap) (pin 2))
(node (ref epd.vcom_cap) (pin 2))
(node (ref flash.vcc_cap) (pin 2))
(node (ref reg_3v3.fb.bottom_res) (pin 2))
(node (ref mcu.en_pull.c) (pin 2))
(node (ref epd.device) (pin 8))
- (node (ref usb) (pin S1))
(node (ref epd.boost.sense) (pin 2))
(node (ref epd.boost.boot_gnd_diode) (pin 1))
(node (ref reg_3v3.power_path.in_cap) (pin 2))
(node (ref reg_3v3.power_path.out_cap) (pin 2))
(node (ref epd.boost.in_cap) (pin 2))
(node (ref epd.boost.out_cap) (pin 2))
- (node (ref epd.boost.neg_out_cap) (pin 1))
+ (node (ref epd.boost.neg_out_cap) (pin 2))
(node (ref epd.device) (pin 17)))
(net (code 2) (name "vbat")
(node (ref vbat_prot) (pin 2))
@@ -1060,7 +1060,7 @@
(node (ref epd.vdd1v8_cap) (pin 1)))
(net (code 48) (name "epd.device.vgl")
(node (ref epd.device) (pin 21))
- (node (ref epd.vgl_cap) (pin 2)))
+ (node (ref epd.vgl_cap) (pin 1)))
(net (code 49) (name "epd.device.vgh")
(node (ref epd.device) (pin 20))
(node (ref epd.vgh_cap) (pin 1)))
@@ -1069,7 +1069,7 @@
(node (ref epd.vsh_cap) (pin 1)))
(net (code 51) (name "epd.device.vsl")
(node (ref epd.device) (pin 3))
- (node (ref epd.vsl_cap) (pin 2)))
+ (node (ref epd.vsl_cap) (pin 1)))
(net (code 52) (name "epd.device.vcom")
(node (ref epd.device) (pin 1))
(node (ref epd.vcom_cap) (pin 1)))
@@ -1088,7 +1088,7 @@
(net (code 56) (name "epd.boost.neg_out")
(node (ref epd.device) (pin 2))
(node (ref epd.boost.boot_neg_diode) (pin 2))
- (node (ref epd.boost.neg_out_cap) (pin 2)))
+ (node (ref epd.boost.neg_out_cap) (pin 1)))
(net (code 57) (name "epd.boost.inductor.b")
(node (ref epd.boost.inductor) (pin 2))
(node (ref epd.boost.fet) (pin 3))
diff --git a/examples/IotDisplay/IotDisplay.ref.net b/examples/IotDisplay/IotDisplay.ref.net
index 5a587c37d..0e1e2edfa 100644
--- a/examples/IotDisplay/IotDisplay.ref.net
+++ b/examples/IotDisplay/IotDisplay.ref.net
@@ -830,6 +830,11 @@
(node (ref U3) (pin 3))
(node (ref J5) (pin 6))
(node (ref J5) (pin 11))
+ (node (ref J1) (pin A1))
+ (node (ref J1) (pin B12))
+ (node (ref J1) (pin B1))
+ (node (ref J1) (pin A12))
+ (node (ref J2) (pin 1))
(node (ref TP2) (pin 1))
(node (ref Q1) (pin 1))
(node (ref U1) (pin 1))
@@ -843,11 +848,7 @@
(node (ref SW2) (pin 2))
(node (ref U6) (pin 4))
(node (ref R10) (pin 2))
- (node (ref J1) (pin A1))
- (node (ref J1) (pin B12))
- (node (ref J1) (pin B1))
- (node (ref J1) (pin A12))
- (node (ref J2) (pin 1))
+ (node (ref J1) (pin S1))
(node (ref R12) (pin 2))
(node (ref C1) (pin 2))
(node (ref C5) (pin 2))
@@ -856,23 +857,22 @@
(node (ref SW1) (pin 2))
(node (ref C8) (pin 2))
(node (ref C9) (pin 2))
- (node (ref C10) (pin 1))
+ (node (ref C10) (pin 2))
(node (ref C11) (pin 2))
(node (ref C12) (pin 2))
- (node (ref C13) (pin 1))
+ (node (ref C13) (pin 2))
(node (ref C14) (pin 2))
(node (ref C19) (pin 2))
(node (ref R2) (pin 2))
(node (ref C7) (pin 2))
(node (ref J4) (pin 8))
- (node (ref J1) (pin S1))
(node (ref R11) (pin 2))
(node (ref D6) (pin 1))
(node (ref C3) (pin 2))
(node (ref C4) (pin 2))
(node (ref C15) (pin 2))
(node (ref C17) (pin 2))
- (node (ref C18) (pin 1))
+ (node (ref C18) (pin 2))
(node (ref J4) (pin 17)))
(net (code 2) (name "vbat")
(node (ref Q1) (pin 2))
@@ -1060,7 +1060,7 @@
(node (ref C9) (pin 1)))
(net (code 48) (name "epd.device.vgl")
(node (ref J4) (pin 21))
- (node (ref C10) (pin 2)))
+ (node (ref C10) (pin 1)))
(net (code 49) (name "epd.device.vgh")
(node (ref J4) (pin 20))
(node (ref C11) (pin 1)))
@@ -1069,7 +1069,7 @@
(node (ref C12) (pin 1)))
(net (code 51) (name "epd.device.vsl")
(node (ref J4) (pin 3))
- (node (ref C13) (pin 2)))
+ (node (ref C13) (pin 1)))
(net (code 52) (name "epd.device.vcom")
(node (ref J4) (pin 1))
(node (ref C14) (pin 1)))
@@ -1088,7 +1088,7 @@
(net (code 56) (name "epd.boost.neg_out")
(node (ref J4) (pin 2))
(node (ref D5) (pin 2))
- (node (ref C18) (pin 2)))
+ (node (ref C18) (pin 1)))
(net (code 57) (name "epd.boost.inductor.b")
(node (ref L2) (pin 2))
(node (ref Q6) (pin 3))
diff --git a/examples/IotIron/IotIron.net b/examples/IotIron/IotIron.net
index 0567fb5f9..e8216a31d 100644
--- a/examples/IotIron/IotIron.net
+++ b/examples/IotIron/IotIron.net
@@ -825,28 +825,28 @@
(property (name "edg_part") (value ""))
(sheetpath (names "/") (tstamps "/"))
(tstamps "176f0438"))
-(comp (ref "iron")
+(comp (ref "iron.conn")
(value "PinHeader2.54 1x3")
(footprint "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
+ (property (name "Sheetname") (value "iron"))
+ (property (name "Sheetfile") (value "examples.test_iot_iron.IronConnector"))
(property (name "edg_path") (value "iron.conn"))
- (property (name "edg_short_path") (value "iron"))
+ (property (name "edg_short_path") (value "iron.conn"))
(property (name "edg_refdes") (value "IJ5"))
(property (name "edg_part") (value "PinHeader2.54 1x3 (Generic)"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "044a01b9"))
-(comp (ref "isense")
+ (sheetpath (names "/iron/") (tstamps "/044a01b9/"))
+ (tstamps "042701af"))
+(comp (ref "iron.isense_res")
(value "±5% 1W Thick Film Resistors 200V ±1000ppm/℃ -55℃~+155℃ 22mΩ 2512 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "isense.res.res"))
- (property (name "edg_short_path") (value "isense"))
+ (property (name "Sheetname") (value "iron"))
+ (property (name "Sheetfile") (value "examples.test_iot_iron.IronConnector"))
+ (property (name "edg_path") (value "iron.isense_res.res.res"))
+ (property (name "edg_short_path") (value "iron.isense_res"))
(property (name "edg_refdes") (value "IR17"))
(property (name "edg_part") (value "25121WJ022LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "08e40288"))
+ (sheetpath (names "/iron/") (tstamps "/044a01b9/"))
+ (tstamps "17130431"))
(comp (ref "vsense.top_res")
(value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 22kΩ 0603 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_0603_1608Metric")
@@ -1084,7 +1084,6 @@
(node (ref vusb_sense.bottom_res) (pin 2))
(node (ref low_rc.c) (pin 2))
(node (ref high_rc.c) (pin 2))
- (node (ref isense) (pin 1))
(node (ref vsense.bottom_res) (pin 2))
(node (ref vfilt.c) (pin 2))
(node (ref tp_i.c) (pin 2))
@@ -1109,6 +1108,7 @@
(node (ref packed_opamp.ic) (pin 4))
(node (ref reg_3v3.fb.bottom_res) (pin 2))
(node (ref mcu.en_pull.c) (pin 2))
+ (node (ref iron.isense_res) (pin 1))
(node (ref tamp.rg) (pin 1))
(node (ref oled.device) (pin 8))
(node (ref oled.device) (pin 29))
@@ -1177,7 +1177,7 @@
(node (ref conv.sw.driver.cap) (pin 1)))
(net (code 5) (name "Iconv_out")
(node (ref tp_conv) (pin 1))
- (node (ref iron) (pin 2))
+ (node (ref iron.conn) (pin 2))
(node (ref vsense.top_res) (pin 1))
(node (ref conv.power_path.inductor) (pin 2))
(node (ref conv.power_path.out_cap) (pin 1)))
@@ -1271,20 +1271,20 @@
(net (code 28) (name "Itouch_sink.pad")
(node (ref mcu.ic) (pin 15))
(node (ref touch_sink) (pin 1)))
-(net (code 29) (name "Iisense_force")
- (node (ref isense) (pin 2))
- (node (ref iron) (pin 1))
- (node (ref packed_opamp.ic) (pin 3))
- (node (ref tamp.r1) (pin 1)))
-(net (code 30) (name "Ivsense.output")
+(net (code 29) (name "Ivsense.output")
(node (ref tp_v) (pin 1))
(node (ref vfilt.r) (pin 1))
(node (ref vsense.top_res) (pin 2))
(node (ref vsense.bottom_res) (pin 1)))
-(net (code 31) (name "Ivfilt.output")
+(net (code 30) (name "Ivfilt.output")
(node (ref mcu.ic) (pin 6))
(node (ref vfilt.r) (pin 2))
(node (ref vfilt.c) (pin 1)))
+(net (code 31) (name "Iiron.isense")
+ (node (ref packed_opamp.ic) (pin 3))
+ (node (ref tamp.r1) (pin 1))
+ (node (ref iron.isense_res) (pin 2))
+ (node (ref iron.conn) (pin 1)))
(net (code 32) (name "Iifilt.output")
(node (ref tp_i.r) (pin 1))
(node (ref ifilt.r1) (pin 1))
@@ -1296,7 +1296,7 @@
(node (ref tp_i.c) (pin 1)))
(net (code 34) (name "Itamp.input_positive")
(node (ref tamp.r2) (pin 1))
- (node (ref iron) (pin 3))
+ (node (ref iron.conn) (pin 3))
(node (ref tp_t) (pin 1)))
(net (code 35) (name "Itamp.output")
(node (ref mcu.ic) (pin 12))
@@ -1374,8 +1374,8 @@
(node (ref conv.sw.high_fet) (pin 1))
(node (ref conv.sw.high_fet) (pin 2))
(node (ref conv.sw.high_fet) (pin 3))
- (node (ref conv.sw.driver.ic) (pin 4))
(node (ref conv.power_path.inductor) (pin 1))
+ (node (ref conv.sw.driver.ic) (pin 4))
(node (ref conv.sw.driver.boot_cap) (pin 2)))
(net (code 56) (name "Iconv.sw.low_gate_res.a")
(node (ref conv.sw.low_gate_res) (pin 1))
diff --git a/examples/IotIron/IotIron.ref.net b/examples/IotIron/IotIron.ref.net
index 8585d37fb..fe32f4176 100644
--- a/examples/IotIron/IotIron.ref.net
+++ b/examples/IotIron/IotIron.ref.net
@@ -828,25 +828,25 @@
(comp (ref "IJ5")
(value "PinHeader2.54 1x3")
(footprint "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
+ (property (name "Sheetname") (value "iron"))
+ (property (name "Sheetfile") (value "examples.test_iot_iron.IronConnector"))
(property (name "edg_path") (value "iron.conn"))
- (property (name "edg_short_path") (value "iron"))
+ (property (name "edg_short_path") (value "iron.conn"))
(property (name "edg_refdes") (value "IJ5"))
(property (name "edg_part") (value "PinHeader2.54 1x3 (Generic)"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "044a01b9"))
+ (sheetpath (names "/iron/") (tstamps "/044a01b9/"))
+ (tstamps "042701af"))
(comp (ref "IR17")
(value "±5% 1W Thick Film Resistors 200V ±1000ppm/℃ -55℃~+155℃ 22mΩ 2512 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_2512_6332Metric")
- (property (name "Sheetname") (value ""))
- (property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "isense.res.res"))
- (property (name "edg_short_path") (value "isense"))
+ (property (name "Sheetname") (value "iron"))
+ (property (name "Sheetfile") (value "examples.test_iot_iron.IronConnector"))
+ (property (name "edg_path") (value "iron.isense_res.res.res"))
+ (property (name "edg_short_path") (value "iron.isense_res"))
(property (name "edg_refdes") (value "IR17"))
(property (name "edg_part") (value "25121WJ022LT4E (UNI-ROYAL(Uniroyal Elec))"))
- (sheetpath (names "/") (tstamps "/"))
- (tstamps "08e40288"))
+ (sheetpath (names "/iron/") (tstamps "/044a01b9/"))
+ (tstamps "17130431"))
(comp (ref "IR18")
(value "±1% 1/10W Thick Film Resistors 75V ±100ppm/℃ -55℃~+155℃ 22kΩ 0603 Chip Resistor - Surface Mount ROHS")
(footprint "Resistor_SMD:R_0603_1608Metric")
@@ -1084,7 +1084,6 @@
(node (ref IR8) (pin 2))
(node (ref IC27) (pin 2))
(node (ref IC28) (pin 2))
- (node (ref IR17) (pin 1))
(node (ref IR19) (pin 2))
(node (ref IC29) (pin 2))
(node (ref IC30) (pin 2))
@@ -1109,6 +1108,7 @@
(node (ref IU11) (pin 4))
(node (ref IR2) (pin 2))
(node (ref IC10) (pin 2))
+ (node (ref IR17) (pin 1))
(node (ref IR27) (pin 1))
(node (ref IJ3) (pin 8))
(node (ref IJ3) (pin 29))
@@ -1271,20 +1271,20 @@
(net (code 28) (name "Itouch_sink.pad")
(node (ref IU3) (pin 15))
(node (ref IU10) (pin 1)))
-(net (code 29) (name "Iisense_force")
- (node (ref IR17) (pin 2))
- (node (ref IJ5) (pin 1))
- (node (ref IU11) (pin 3))
- (node (ref IR24) (pin 1)))
-(net (code 30) (name "Ivsense.output")
+(net (code 29) (name "Ivsense.output")
(node (ref ITP8) (pin 1))
(node (ref IR20) (pin 1))
(node (ref IR18) (pin 2))
(node (ref IR19) (pin 1)))
-(net (code 31) (name "Ivfilt.output")
+(net (code 30) (name "Ivfilt.output")
(node (ref IU3) (pin 6))
(node (ref IR20) (pin 2))
(node (ref IC29) (pin 1)))
+(net (code 31) (name "Iiron.isense")
+ (node (ref IU11) (pin 3))
+ (node (ref IR24) (pin 1))
+ (node (ref IR17) (pin 2))
+ (node (ref IJ5) (pin 1)))
(net (code 32) (name "Iifilt.output")
(node (ref IR23) (pin 1))
(node (ref IR21) (pin 1))
@@ -1374,8 +1374,8 @@
(node (ref IQ2) (pin 1))
(node (ref IQ2) (pin 2))
(node (ref IQ2) (pin 3))
- (node (ref IU9) (pin 4))
(node (ref IL2) (pin 1))
+ (node (ref IU9) (pin 4))
(node (ref IC26) (pin 2)))
(net (code 56) (name "Iconv.sw.low_gate_res.a")
(node (ref IR11) (pin 1))
diff --git a/examples/JacdacKeyswitch/JacdacKeyswitch.net b/examples/JacdacKeyswitch/JacdacKeyswitch.net
index e73a16b40..cf7048e9c 100644
--- a/examples/JacdacKeyswitch/JacdacKeyswitch.net
+++ b/examples/JacdacKeyswitch/JacdacKeyswitch.net
@@ -187,28 +187,28 @@
(property (name "edg_part") (value ""))
(sheetpath (names "/edge2/") (tstamps "/05bf01c8/"))
(tstamps "1bbb0484"))
-(comp (ref "tp_jd_pwr")
- (value "jd_pwr")
+(comp (ref "tp_gnd")
+ (value "gnd")
(footprint "TestPoint:TestPoint_Keystone_5015_Micro-Minature")
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "tp_jd_pwr.tp"))
- (property (name "edg_short_path") (value "tp_jd_pwr"))
+ (property (name "edg_path") (value "tp_gnd.tp"))
+ (property (name "edg_short_path") (value "tp_gnd"))
(property (name "edg_refdes") (value "TP1"))
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
- (tstamps "12d203ca"))
-(comp (ref "tp_gnd")
- (value "gnd")
+ (tstamps "08df027d"))
+(comp (ref "tp_jd_pwr")
+ (value "jd_pwr")
(footprint "TestPoint:TestPoint_Keystone_5015_Micro-Minature")
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "tp_gnd.tp"))
- (property (name "edg_short_path") (value "tp_gnd"))
+ (property (name "edg_path") (value "tp_jd_pwr.tp"))
+ (property (name "edg_short_path") (value "tp_jd_pwr"))
(property (name "edg_refdes") (value "TP2"))
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
- (tstamps "08df027d"))
+ (tstamps "12d203ca"))
(comp (ref "reg_3v3.ic")
(value "XC6209F332MR-G")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
diff --git a/examples/JacdacKeyswitch/JacdacKeyswitch.ref.net b/examples/JacdacKeyswitch/JacdacKeyswitch.ref.net
index 3606a60c7..322c6180d 100644
--- a/examples/JacdacKeyswitch/JacdacKeyswitch.ref.net
+++ b/examples/JacdacKeyswitch/JacdacKeyswitch.ref.net
@@ -188,27 +188,27 @@
(sheetpath (names "/edge2/") (tstamps "/05bf01c8/"))
(tstamps "1bbb0484"))
(comp (ref "TP1")
- (value "jd_pwr")
+ (value "gnd")
(footprint "TestPoint:TestPoint_Keystone_5015_Micro-Minature")
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "tp_jd_pwr.tp"))
- (property (name "edg_short_path") (value "tp_jd_pwr"))
+ (property (name "edg_path") (value "tp_gnd.tp"))
+ (property (name "edg_short_path") (value "tp_gnd"))
(property (name "edg_refdes") (value "TP1"))
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
- (tstamps "12d203ca"))
+ (tstamps "08df027d"))
(comp (ref "TP2")
- (value "gnd")
+ (value "jd_pwr")
(footprint "TestPoint:TestPoint_Keystone_5015_Micro-Minature")
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value ""))
- (property (name "edg_path") (value "tp_gnd.tp"))
- (property (name "edg_short_path") (value "tp_gnd"))
+ (property (name "edg_path") (value "tp_jd_pwr.tp"))
+ (property (name "edg_short_path") (value "tp_jd_pwr"))
(property (name "edg_refdes") (value "TP2"))
(property (name "edg_part") (value "5015 (Keystone)"))
(sheetpath (names "/") (tstamps "/"))
- (tstamps "08df027d"))
+ (tstamps "12d203ca"))
(comp (ref "U1")
(value "XC6209F332MR-G")
(footprint "Package_TO_SOT_SMD:SOT-23-5")
@@ -419,7 +419,7 @@
(node (ref MH3) (pin MH3))
(node (ref EC1) (pin 3))
(node (ref EC2) (pin 3))
- (node (ref TP1) (pin 1))
+ (node (ref TP2) (pin 1))
(node (ref U1) (pin 1))
(node (ref D2) (pin 1))
(node (ref U1) (pin 3))
@@ -430,7 +430,7 @@
(node (ref MH4) (pin MH4))
(node (ref EC1) (pin 2))
(node (ref EC2) (pin 2))
- (node (ref TP2) (pin 1))
+ (node (ref TP1) (pin 1))
(node (ref U1) (pin 2))
(node (ref U2) (pin 4))
(node (ref SW1) (pin 2))
diff --git a/examples/Multimeter/Multimeter.net b/examples/Multimeter/Multimeter.net
index 0ef06e597..7a2adfd99 100644
--- a/examples/Multimeter/Multimeter.net
+++ b/examples/Multimeter/Multimeter.net
@@ -1179,8 +1179,12 @@
(tstamps "00640064")))
(nets
(net (code 1) (name "gnd")
- (node (ref usb_esd) (pin 3))
(node (ref bat) (pin 2))
+ (node (ref usb_esd) (pin 3))
+ (node (ref data_usb.conn) (pin A1))
+ (node (ref data_usb.conn) (pin B12))
+ (node (ref data_usb.conn) (pin B1))
+ (node (ref data_usb.conn) (pin A12))
(node (ref reg_5v.ic) (pin 2))
(node (ref prot_5v) (pin 2))
(node (ref reg_3v3.ic) (pin 2))
@@ -1206,10 +1210,7 @@
(node (ref inn_mux.ic) (pin 2))
(node (ref measure_buffer.ic) (pin 2))
(node (ref driver_dac.c) (pin 2))
- (node (ref data_usb.conn) (pin A1))
- (node (ref data_usb.conn) (pin B12))
- (node (ref data_usb.conn) (pin B1))
- (node (ref data_usb.conn) (pin A12))
+ (node (ref data_usb.conn) (pin S1))
(node (ref spk_drv.inn_cap) (pin 2))
(node (ref gate.pwr_gate.amp_res) (pin 1))
(node (ref gate.pwr_gate.amp_fet) (pin 2))
@@ -1235,13 +1236,14 @@
(node (ref inn_mux.vdd_cap) (pin 2))
(node (ref measure_buffer.vdd_cap) (pin 2))
(node (ref driver.sw.ic) (pin 2))
- (node (ref data_usb.conn) (pin S1))
(node (ref measure.range.switch.sw[0_0].ic) (pin 2))
(node (ref measure.range.switch.sw[0_1].ic) (pin 2))
(node (ref measure.range.switch.sw[1_0].ic) (pin 2))
(node (ref mcu.swd) (pin 2))
(node (ref mcu.swd) (pin 3))
(node (ref mcu.swd) (pin 5))
+ (node (ref data_usb.cc_pull.cc1) (pin 1))
+ (node (ref data_usb.cc_pull.cc2) (pin 1))
(node (ref reg_5v.power_path.in_cap) (pin 2))
(node (ref reg_5v.power_path.out_cap) (pin 2))
(node (ref driver.amp.vdd_cap) (pin 2))
@@ -1252,8 +1254,6 @@
(node (ref measure.range.switch.sw[0_0].vdd_cap) (pin 2))
(node (ref measure.range.switch.sw[0_1].vdd_cap) (pin 2))
(node (ref measure.range.switch.sw[1_0].vdd_cap) (pin 2))
- (node (ref data_usb.cc_pull.cc1) (pin 1))
- (node (ref data_usb.cc_pull.cc2) (pin 1))
(node (ref driver.range.switch.sw[0_0].vdd_cap) (pin 2))
(node (ref driver.range.switch.sw[0_1].vdd_cap) (pin 2))
(node (ref driver.range.switch.sw[1_0].vdd_cap) (pin 2)))
diff --git a/examples/Multimeter/Multimeter.ref.net b/examples/Multimeter/Multimeter.ref.net
index 72d4b23a2..73a5f909d 100644
--- a/examples/Multimeter/Multimeter.ref.net
+++ b/examples/Multimeter/Multimeter.ref.net
@@ -1179,8 +1179,12 @@
(tstamps "00640064")))
(nets
(net (code 1) (name "gnd")
- (node (ref U6) (pin 3))
(node (ref U1) (pin 2))
+ (node (ref U6) (pin 3))
+ (node (ref J1) (pin A1))
+ (node (ref J1) (pin B12))
+ (node (ref J1) (pin B1))
+ (node (ref J1) (pin A12))
(node (ref U2) (pin 2))
(node (ref D3) (pin 2))
(node (ref U3) (pin 2))
@@ -1206,10 +1210,7 @@
(node (ref U9) (pin 2))
(node (ref U13) (pin 2))
(node (ref C31) (pin 2))
- (node (ref J1) (pin A1))
- (node (ref J1) (pin B12))
- (node (ref J1) (pin B1))
- (node (ref J1) (pin A12))
+ (node (ref J1) (pin S1))
(node (ref C14) (pin 2))
(node (ref R4) (pin 1))
(node (ref Q2) (pin 2))
@@ -1235,13 +1236,14 @@
(node (ref C16) (pin 2))
(node (ref C20) (pin 2))
(node (ref U19) (pin 2))
- (node (ref J1) (pin S1))
(node (ref U10) (pin 2))
(node (ref U11) (pin 2))
(node (ref U12) (pin 2))
(node (ref J2) (pin 2))
(node (ref J2) (pin 3))
(node (ref J2) (pin 5))
+ (node (ref R1) (pin 1))
+ (node (ref R2) (pin 1))
(node (ref C1) (pin 2))
(node (ref C2) (pin 2))
(node (ref C26) (pin 2))
@@ -1252,8 +1254,6 @@
(node (ref C17) (pin 2))
(node (ref C18) (pin 2))
(node (ref C19) (pin 2))
- (node (ref R1) (pin 1))
- (node (ref R2) (pin 1))
(node (ref C27) (pin 2))
(node (ref C28) (pin 2))
(node (ref C29) (pin 2)))
diff --git a/examples/PcbBot/PcbBot.net b/examples/PcbBot/PcbBot.net
index a6fb75783..2e1d2e020 100644
--- a/examples/PcbBot/PcbBot.net
+++ b/examples/PcbBot/PcbBot.net
@@ -1192,6 +1192,11 @@
(net (code 2) (name "gnd")
(node (ref usb_esd) (pin 3))
(node (ref npx_key) (pin 3))
+ (node (ref usb.conn) (pin A1))
+ (node (ref usb.conn) (pin B12))
+ (node (ref usb.conn) (pin B1))
+ (node (ref usb.conn) (pin A12))
+ (node (ref batt) (pin 1))
(node (ref tp_gnd) (pin 1))
(node (ref prot_batt) (pin 2))
(node (ref pwr_or.pdr) (pin 2))
@@ -1237,11 +1242,7 @@
(node (ref reg_1v2.ic) (pin 1))
(node (ref switch) (pin 2))
(node (ref batt_sense.bottom_res) (pin 2))
- (node (ref usb.conn) (pin A1))
- (node (ref usb.conn) (pin B12))
- (node (ref usb.conn) (pin B1))
- (node (ref usb.conn) (pin A12))
- (node (ref batt) (pin 1))
+ (node (ref usb.conn) (pin S1))
(node (ref charger.prog_res) (pin 2))
(node (ref mag.c1) (pin 2))
(node (ref oled.iref_res) (pin 2))
@@ -1278,7 +1279,8 @@
(node (ref cam.device) (pin 23))
(node (ref cam.dovdd_cap) (pin 2))
(node (ref mcu.en_pull.c) (pin 2))
- (node (ref usb.conn) (pin S1))
+ (node (ref usb.cc_pull.cc1) (pin 1))
+ (node (ref usb.cc_pull.cc2) (pin 1))
(node (ref oled.device) (pin 8))
(node (ref oled.device) (pin 29))
(node (ref oled.device) (pin 1))
@@ -1294,9 +1296,7 @@
(node (ref oled.device) (pin 10))
(node (ref oled.device) (pin 15))
(node (ref oled.device) (pin 13))
- (node (ref cam.device) (pin 17))
- (node (ref usb.cc_pull.cc1) (pin 1))
- (node (ref usb.cc_pull.cc2) (pin 1)))
+ (node (ref cam.device) (pin 17)))
(net (code 3) (name "vbatt")
(node (ref npx_key) (pin 1))
(node (ref gate.pwr_gate.pwr_fet) (pin 3))
diff --git a/examples/PcbBot/PcbBot.ref.net b/examples/PcbBot/PcbBot.ref.net
index aa77828e5..d3be4c46f 100644
--- a/examples/PcbBot/PcbBot.ref.net
+++ b/examples/PcbBot/PcbBot.ref.net
@@ -1192,6 +1192,11 @@
(net (code 2) (name "gnd")
(node (ref U4) (pin 3))
(node (ref D25) (pin 3))
+ (node (ref J1) (pin A1))
+ (node (ref J1) (pin B12))
+ (node (ref J1) (pin B1))
+ (node (ref J1) (pin A12))
+ (node (ref J2) (pin 1))
(node (ref TP1) (pin 1))
(node (ref D3) (pin 2))
(node (ref R5) (pin 2))
@@ -1237,11 +1242,7 @@
(node (ref U10) (pin 1))
(node (ref SW3) (pin 2))
(node (ref R17) (pin 2))
- (node (ref J1) (pin A1))
- (node (ref J1) (pin B12))
- (node (ref J1) (pin B1))
- (node (ref J1) (pin A12))
- (node (ref J2) (pin 1))
+ (node (ref J1) (pin S1))
(node (ref R6) (pin 2))
(node (ref C12) (pin 2))
(node (ref R15) (pin 2))
@@ -1278,7 +1279,8 @@
(node (ref J13) (pin 23))
(node (ref C24) (pin 2))
(node (ref C7) (pin 2))
- (node (ref J1) (pin S1))
+ (node (ref R1) (pin 1))
+ (node (ref R2) (pin 1))
(node (ref J8) (pin 8))
(node (ref J8) (pin 29))
(node (ref J8) (pin 1))
@@ -1294,9 +1296,7 @@
(node (ref J8) (pin 10))
(node (ref J8) (pin 15))
(node (ref J8) (pin 13))
- (node (ref J13) (pin 17))
- (node (ref R1) (pin 1))
- (node (ref R2) (pin 1)))
+ (node (ref J13) (pin 17)))
(net (code 3) (name "vbatt")
(node (ref D25) (pin 1))
(node (ref Q1) (pin 3))
diff --git a/examples/ProtectedCharger/ProtectedCharger.net b/examples/ProtectedCharger/ProtectedCharger.net
index 8680dc40d..0ad5a74e4 100644
--- a/examples/ProtectedCharger/ProtectedCharger.net
+++ b/examples/ProtectedCharger/ProtectedCharger.net
@@ -241,21 +241,21 @@
(node (ref charge_led.package) (pin 2))
(node (ref charger.vdd_cap) (pin 1)))
(net (code 2) (name "gnd")
+ (node (ref usb.conn) (pin A1))
+ (node (ref usb.conn) (pin B12))
+ (node (ref usb.conn) (pin B1))
+ (node (ref usb.conn) (pin A12))
(node (ref pwr_pins) (pin 1))
(node (ref pwr_pins) (pin 3))
+ (node (ref batt) (pin 1))
(node (ref tp_gnd) (pin 1))
(node (ref pmos.r1) (pin 2))
(node (ref charger.ic) (pin 2))
(node (ref pmos_load) (pin 1))
- (node (ref usb.conn) (pin A1))
- (node (ref usb.conn) (pin B12))
- (node (ref usb.conn) (pin B1))
- (node (ref usb.conn) (pin A12))
- (node (ref batt) (pin 1))
+ (node (ref usb.conn) (pin S1))
(node (ref charger.prog_res) (pin 2))
(node (ref charger.vdd_cap) (pin 2))
(node (ref charger.vbat_cap) (pin 2))
- (node (ref usb.conn) (pin S1))
(node (ref usb.cc_pull.cc1) (pin 1))
(node (ref usb.cc_pull.cc2) (pin 1)))
(net (code 3) (name "batt.pwr")
diff --git a/examples/ProtectedCharger/ProtectedCharger.ref.net b/examples/ProtectedCharger/ProtectedCharger.ref.net
index 3557f5210..f718397fc 100644
--- a/examples/ProtectedCharger/ProtectedCharger.ref.net
+++ b/examples/ProtectedCharger/ProtectedCharger.ref.net
@@ -241,21 +241,21 @@
(node (ref D1) (pin 2))
(node (ref C1) (pin 1)))
(net (code 2) (name "gnd")
+ (node (ref J1) (pin A1))
+ (node (ref J1) (pin B12))
+ (node (ref J1) (pin B1))
+ (node (ref J1) (pin A12))
(node (ref J3) (pin 1))
(node (ref J3) (pin 3))
+ (node (ref J2) (pin 1))
(node (ref TP1) (pin 1))
(node (ref R3) (pin 2))
(node (ref U1) (pin 2))
(node (ref Q3) (pin 1))
- (node (ref J1) (pin A1))
- (node (ref J1) (pin B12))
- (node (ref J1) (pin B1))
- (node (ref J1) (pin A12))
- (node (ref J2) (pin 1))
+ (node (ref J1) (pin S1))
(node (ref R5) (pin 2))
(node (ref C1) (pin 2))
(node (ref C2) (pin 2))
- (node (ref J1) (pin S1))
(node (ref R1) (pin 1))
(node (ref R2) (pin 1)))
(net (code 3) (name "batt.pwr")
diff --git a/examples/TestBlinkyBasic/TestBlinkyBasic.net b/examples/TestBlinkyBasic/TestBlinkyBasic.net
index 69bc35f4d..a82e4f048 100644
--- a/examples/TestBlinkyBasic/TestBlinkyBasic.net
+++ b/examples/TestBlinkyBasic/TestBlinkyBasic.net
@@ -37,7 +37,7 @@
(net (code 1) (name "led.signal")
(node (ref mcu) (pin 10))
(node (ref led.package) (pin 2)))
-(net (code 2) (name "mcu.gnd_out")
+(net (code 2) (name "mcu.gnd")
(node (ref mcu) (pin 4))
(node (ref mcu) (pin 17))
(node (ref led.res) (pin 2)))
diff --git a/examples/TestBlinkyBasic/TestBlinkyBasic.ref.net b/examples/TestBlinkyBasic/TestBlinkyBasic.ref.net
index ff9e265af..113606b3a 100644
--- a/examples/TestBlinkyBasic/TestBlinkyBasic.ref.net
+++ b/examples/TestBlinkyBasic/TestBlinkyBasic.ref.net
@@ -37,7 +37,7 @@
(net (code 1) (name "led.signal")
(node (ref U1) (pin 10))
(node (ref D1) (pin 2)))
-(net (code 2) (name "mcu.gnd_out")
+(net (code 2) (name "mcu.gnd")
(node (ref U1) (pin 4))
(node (ref U1) (pin 17))
(node (ref R1) (pin 2)))
diff --git a/examples/TofArray/TofArray.net b/examples/TofArray/TofArray.net
index 6849640e2..d6c20e93b 100644
--- a/examples/TofArray/TofArray.net
+++ b/examples/TofArray/TofArray.net
@@ -89,7 +89,7 @@
(sheetpath (names "/") (tstamps "/"))
(tstamps "0c2d0304"))
(comp (ref "tp_gnd")
- (value "_usb_gnd_link")
+ (value "gnd")
(footprint "TestPoint:TestPoint_Keystone_5015_Micro-Minature")
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value ""))
@@ -808,6 +808,12 @@
(net (code 2) (name "gnd")
(node (ref usb_esd) (pin 3))
(node (ref can_esd) (pin 3))
+ (node (ref usb.conn) (pin A1))
+ (node (ref usb.conn) (pin B12))
+ (node (ref usb.conn) (pin B1))
+ (node (ref usb.conn) (pin A12))
+ (node (ref can) (pin 3))
+ (node (ref tp_gnd) (pin 1))
(node (ref reg_3v3.ic) (pin 1))
(node (ref prot_3v3) (pin 2))
(node (ref mcu.ic) (pin 8))
@@ -821,12 +827,7 @@
(node (ref spk_drv.ic) (pin 7))
(node (ref spk_drv.ic) (pin 9))
(node (ref spk_dac.c) (pin 2))
- (node (ref usb.conn) (pin A1))
- (node (ref usb.conn) (pin B12))
- (node (ref usb.conn) (pin B1))
- (node (ref usb.conn) (pin A12))
- (node (ref tp_gnd) (pin 1))
- (node (ref can) (pin 3))
+ (node (ref usb.conn) (pin S1))
(node (ref spk_drv.inn_cap) (pin 2))
(node (ref reg_3v3.in_cap) (pin 2))
(node (ref reg_3v3.out_cap) (pin 2))
@@ -866,7 +867,8 @@
(node (ref xcvr.vdd_cap) (pin 2))
(node (ref spk_drv.pwr_cap) (pin 2))
(node (ref spk_drv.bulk_cap) (pin 2))
- (node (ref usb.conn) (pin S1))
+ (node (ref usb.cc_pull.cc1) (pin 1))
+ (node (ref usb.cc_pull.cc2) (pin 1))
(node (ref mcu.swd) (pin 2))
(node (ref mcu.swd) (pin 3))
(node (ref mcu.swd) (pin 5))
@@ -881,9 +883,7 @@
(node (ref tof.elt[3].vdd_cap[0]) (pin 2))
(node (ref tof.elt[3].vdd_cap[1]) (pin 2))
(node (ref tof.elt[4].vdd_cap[0]) (pin 2))
- (node (ref tof.elt[4].vdd_cap[1]) (pin 2))
- (node (ref usb.cc_pull.cc1) (pin 1))
- (node (ref usb.cc_pull.cc2) (pin 1)))
+ (node (ref tof.elt[4].vdd_cap[1]) (pin 2)))
(net (code 3) (name "v3v3")
(node (ref reg_3v3.ic) (pin 2))
(node (ref tp_3v3) (pin 1))
diff --git a/examples/TofArray/TofArray.ref.net b/examples/TofArray/TofArray.ref.net
index 69268cec5..884aad42c 100644
--- a/examples/TofArray/TofArray.ref.net
+++ b/examples/TofArray/TofArray.ref.net
@@ -89,7 +89,7 @@
(sheetpath (names "/") (tstamps "/"))
(tstamps "0c2d0304"))
(comp (ref "TP2")
- (value "_usb_gnd_link")
+ (value "gnd")
(footprint "TestPoint:TestPoint_Keystone_5015_Micro-Minature")
(property (name "Sheetname") (value ""))
(property (name "Sheetfile") (value ""))
@@ -808,6 +808,12 @@
(net (code 2) (name "gnd")
(node (ref U8) (pin 3))
(node (ref U10) (pin 3))
+ (node (ref J1) (pin A1))
+ (node (ref J1) (pin B12))
+ (node (ref J1) (pin B1))
+ (node (ref J1) (pin A12))
+ (node (ref J2) (pin 3))
+ (node (ref TP2) (pin 1))
(node (ref U1) (pin 1))
(node (ref D1) (pin 2))
(node (ref U2) (pin 8))
@@ -821,12 +827,7 @@
(node (ref U11) (pin 7))
(node (ref U11) (pin 9))
(node (ref C22) (pin 2))
- (node (ref J1) (pin A1))
- (node (ref J1) (pin B12))
- (node (ref J1) (pin B1))
- (node (ref J1) (pin A12))
- (node (ref TP2) (pin 1))
- (node (ref J2) (pin 3))
+ (node (ref J1) (pin S1))
(node (ref C26) (pin 2))
(node (ref C1) (pin 2))
(node (ref C2) (pin 2))
@@ -866,7 +867,8 @@
(node (ref C21) (pin 2))
(node (ref C23) (pin 2))
(node (ref C24) (pin 2))
- (node (ref J1) (pin S1))
+ (node (ref R1) (pin 1))
+ (node (ref R2) (pin 1))
(node (ref J3) (pin 2))
(node (ref J3) (pin 3))
(node (ref J3) (pin 5))
@@ -881,9 +883,7 @@
(node (ref C17) (pin 2))
(node (ref C18) (pin 2))
(node (ref C19) (pin 2))
- (node (ref C20) (pin 2))
- (node (ref R1) (pin 1))
- (node (ref R2) (pin 1)))
+ (node (ref C20) (pin 2)))
(net (code 3) (name "v3v3")
(node (ref U1) (pin 2))
(node (ref TP3) (pin 1))
diff --git a/examples/UsbSourceMeasure/UsbSourceMeasure.net b/examples/UsbSourceMeasure/UsbSourceMeasure.net
index bdd610304..ddabdc3bf 100644
--- a/examples/UsbSourceMeasure/UsbSourceMeasure.net
+++ b/examples/UsbSourceMeasure/UsbSourceMeasure.net
@@ -3041,12 +3041,12 @@
(net (code 11) (name "vcontroln")
(node (ref reg_vcontroln.ic) (pin 2))
(node (ref tp_vcontroln) (pin 1))
- (node (ref reg_vcontroln.cout.c[0]) (pin 1))
- (node (ref reg_vcontroln.cout.c[1]) (pin 1))
(node (ref ampdmeas_amps.ic) (pin 4))
(node (ref vimeas_amps.ic) (pin 4))
(node (ref ampdmeas_amps.vdd_cap) (pin 2))
- (node (ref vimeas_amps.vdd_cap) (pin 2)))
+ (node (ref vimeas_amps.vdd_cap) (pin 2))
+ (node (ref reg_vcontroln.cout.c[0]) (pin 1))
+ (node (ref reg_vcontroln.cout.c[1]) (pin 1)))
(net (code 12) (name "usb.pwr")
(node (ref usb) (pin A4))
(node (ref usb) (pin B9))
diff --git a/examples/UsbSourceMeasure/UsbSourceMeasure.ref.net b/examples/UsbSourceMeasure/UsbSourceMeasure.ref.net
index d674305ea..98205adb7 100644
--- a/examples/UsbSourceMeasure/UsbSourceMeasure.ref.net
+++ b/examples/UsbSourceMeasure/UsbSourceMeasure.ref.net
@@ -3041,12 +3041,12 @@
(net (code 11) (name "vcontroln")
(node (ref U9) (pin 2))
(node (ref TP10) (pin 1))
- (node (ref C35) (pin 1))
- (node (ref C36) (pin 1))
(node (ref U29) (pin 4))
(node (ref U28) (pin 4))
(node (ref C73) (pin 2))
- (node (ref C72) (pin 2)))
+ (node (ref C72) (pin 2))
+ (node (ref C35) (pin 1))
+ (node (ref C36) (pin 1)))
(net (code 12) (name "usb.pwr")
(node (ref J1) (pin A4))
(node (ref J1) (pin B9))
diff --git a/examples/resources/SourceMeasureControl.kicad_sch b/examples/resources/SourceMeasureControl.kicad_sch
index b10c70e1e..c1385988b 100644
--- a/examples/resources/SourceMeasureControl.kicad_sch
+++ b/examples/resources/SourceMeasureControl.kicad_sch
@@ -1850,9 +1850,9 @@
(property "Datasheet" "~" (at 127 91.44 0)
(effects (font (size 1.27 1.27)) hide)
)
- (pin "" (uuid 8463ab9a-e902-4971-8ecf-d2ec44681932))
- (pin "" (uuid 8463ab9a-e902-4971-8ecf-d2ec44681932))
- (pin "" (uuid 8463ab9a-e902-4971-8ecf-d2ec44681932))
+ (pin "" (uuid 8463ab9a-e902-4971-8ecf-d2ec44681934))
+ (pin "" (uuid 8463ab9a-e902-4971-8ecf-d2ec44681934))
+ (pin "" (uuid 8463ab9a-e902-4971-8ecf-d2ec44681934))
(pin "1" (uuid 10f87e0b-1556-4607-8d3e-cd6c8ea50e5f))
(pin "2" (uuid 536698fd-7b37-4ae9-97a8-c5a0078bb08a))
(pin "C" (uuid 2fc0e8da-9e7f-4e24-8109-0843c5f1eb00))
@@ -2236,7 +2236,7 @@
(property "Reference" "gnd_adapter" (at 210.185 127.635 0)
(effects (font (size 1.27 1.27)))
)
- (property "Value" "#VoltageSinkAdapterAnalogSource()" (at 210.82 131.445 0)
+ (property "Value" "#GroundAdapterAnalogSource()" (at 210.82 131.445 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "" (at 210.82 129.54 0)
@@ -2397,8 +2397,8 @@
(property "Datasheet" "~" (at 214.63 91.44 0)
(effects (font (size 1.27 1.27)) hide)
)
- (pin "" (uuid 145a6788-c17c-40d5-94a5-7eb9d447097c))
- (pin "" (uuid 145a6788-c17c-40d5-94a5-7eb9d447097c))
+ (pin "" (uuid 145a6788-c17c-40d5-94a5-7eb9d447097d))
+ (pin "" (uuid 145a6788-c17c-40d5-94a5-7eb9d447097d))
(pin "com" (uuid d1ead23d-c54a-41f2-aff1-2510a88bc4e0))
(pin "control" (uuid 5707a5fc-d418-4caf-b677-a5beee153ba6))
(pin "sen_com" (uuid bfd78862-a389-493b-ad6b-8f4d8a97a909))
diff --git a/examples/test_bldc_controller.py b/examples/test_bldc_controller.py
index b3bee9444..7d217f23b 100644
--- a/examples/test_bldc_controller.py
+++ b/examples/test_bldc_controller.py
@@ -88,9 +88,7 @@ def contents(self) -> None:
self.vusb = self.connect(mcu_usb.vusb_out)
self.v3v3 = self.connect(mcu_pwr.pwr_out)
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- mcu_pwr.gnd_out, self.motor_pwr.gnd)
- self.gnd = self.connect(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.mcu.gnd, self.motor_pwr.gnd)
# 3V3 DOMAIN
with self.implicit_connect(
@@ -148,7 +146,7 @@ def contents(self) -> None:
imp.Block(AnalogClampResistor()),
self.mcu.adc.request('isense'))
- self.bldc_drv = imp.Block(Drv8313())
+ self.bldc_drv = imp.Block(Drv8313(risense_res=50*mOhm(tol=0.05)))
self.connect(self.isense.pwr_out, self.bldc_drv.pwr)
self.connect(self.mcu.gpio.request('bldc_reset'), self.bldc_drv.nreset)
@@ -169,14 +167,11 @@ def contents(self) -> None:
self.curr_amp = ElementDict[Amplifier]()
self.curr_tp = ElementDict[AnalogTestPoint]()
for i in ['1', '2', '3']:
- self.curr[i] = self.Block(CurrentSenseResistor(50*mOhm(tol=0.05), sense_in_reqd=False))\
- .connected(self.gnd_merge.pwr_out, self.bldc_drv.pgnds.request(i))
-
self.curr_amp[i] = imp.Block(Amplifier(Range.from_tolerance(20, 0.05)))
self.connect(self.curr_amp[i].pwr, self.v3v3)
- (_, self.curr_tp[i], ), _ = self.chain(self.curr[i].sense_out, self.curr_amp[i],
- self.Block(AnalogTestPoint()),
- self.mcu.adc.request(f'curr_{i}'))
+ (_, self.curr_tp[i], ), _ = self.chain(self.bldc_drv.pgnd_sense.request(i), self.curr_amp[i],
+ self.Block(AnalogTestPoint()),
+ self.mcu.adc.request(f'curr_{i}'))
def refinements(self) -> Refinements:
return super().refinements() + Refinements(
@@ -210,12 +205,12 @@ def refinements(self) -> Refinements:
'hall_w=25',
]),
(['isense', 'sense', 'res', 'res', 'require_basic_part'], False),
- (['curr[1]', 'res', 'res', 'require_basic_part'], False),
- (['curr[1]', 'res', 'res', 'footprint_spec'], 'Resistor_SMD:R_2512_6332Metric'),
- (['curr[2]', 'res', 'res', 'require_basic_part'], ParamValue(['curr[1]', 'res', 'res', 'require_basic_part'])),
- (['curr[2]', 'res', 'res', 'footprint_spec'], ParamValue(['curr[1]', 'res', 'res', 'footprint_spec'])),
- (['curr[3]', 'res', 'res', 'require_basic_part'], ParamValue(['curr[1]', 'res', 'res', 'require_basic_part'])),
- (['curr[3]', 'res', 'res', 'footprint_spec'], ParamValue(['curr[1]', 'res', 'res', 'footprint_spec'])),
+ (['bldc_drv', 'pgnd_res[1]', 'res', 'res', 'require_basic_part'], False),
+ (['bldc_drv', 'pgnd_res[1]', 'res', 'res', 'footprint_spec'], 'Resistor_SMD:R_2512_6332Metric'),
+ (['bldc_drv', 'pgnd_res[2]', 'res', 'res', 'require_basic_part'], ParamValue(['bldc_drv', 'pgnd_res[1]', 'res', 'res', 'require_basic_part'])),
+ (['bldc_drv', 'pgnd_res[2]', 'res', 'res', 'footprint_spec'], ParamValue(['bldc_drv', 'pgnd_res[1]', 'res', 'res', 'footprint_spec'])),
+ (['bldc_drv', 'pgnd_res[3]', 'res', 'res', 'require_basic_part'], ParamValue(['bldc_drv', 'pgnd_res[1]', 'res', 'res', 'require_basic_part'])),
+ (['bldc_drv', 'pgnd_res[3]', 'res', 'res', 'footprint_spec'], ParamValue(['bldc_drv', 'pgnd_res[1]', 'res', 'res', 'footprint_spec'])),
(["bldc_drv", "vm_cap_bulk", "cap", "voltage_rating_derating"], 0.6), # allow using a 50V cap
(["bldc_drv", "cp_cap", "voltage_rating_derating"], 0.6), # allow using a 50V cap
diff --git a/examples/test_blinky.py b/examples/test_blinky.py
index 8b61962e5..b0ac4d748 100644
--- a/examples/test_blinky.py
+++ b/examples/test_blinky.py
@@ -10,7 +10,7 @@ def contents(self) -> None:
self.led = self.Block(IndicatorLed())
self.connect(self.led.signal, self.mcu.gpio.request())
- self.connect(self.mcu.gnd_out, self.led.gnd)
+ self.connect(self.mcu.gnd, self.led.gnd)
class TestBlinkyEmpty(SimpleBoardTop):
diff --git a/examples/test_datalogger.py b/examples/test_datalogger.py
index 1c12e03c6..926d87495 100644
--- a/examples/test_datalogger.py
+++ b/examples/test_datalogger.py
@@ -15,10 +15,7 @@ def contents(self) -> None:
self.connect(self.usb_conn.pwr, self.usb_forced_current.pwr_in)
self.bat = self.Block(Cr2032())
-
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.usb_conn.gnd, self.pwr_conn.gnd, self.bat.gnd)
- self.gnd = self.connect(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.usb_conn.gnd, self.pwr_conn.gnd, self.bat.gnd)
with self.implicit_connect(
ImplicitConnect(self.gnd, [Common]),
@@ -53,12 +50,6 @@ def contents(self) -> None:
(self.can, ), _ = self.chain(self.mcu.can.request('can'), imp.Block(CalSolCanBlock()))
- # TODO need proper support for exported unconnected ports
- self.can_gnd_load = self.Block(DummyVoltageSink())
- self.connect(self.can.can_gnd, self.can_gnd_load.pwr)
- self.can_pwr_load = self.Block(DummyVoltageSink())
- self.connect(self.can.can_pwr, self.can_pwr_load.pwr)
-
# mcu_i2c = self.mcu.i2c.request() # no devices, ignored for now
# self.i2c_pullup = imp.Block(I2cPullup())
# self.connect(self.i2c_pullup.i2c, mcu_i2c)
diff --git a/examples/test_fcml.py b/examples/test_fcml.py
index f5cb3b433..aaacdae37 100644
--- a/examples/test_fcml.py
+++ b/examples/test_fcml.py
@@ -62,7 +62,7 @@ def __init__(self, is_first: BoolLike = False, *,
gate_res: RangeLike):
super().__init__()
# in is generally towards the supply side, out is towards the inductor side
- self.low_in = self.Port(VoltageSink.empty())
+ self.low_in = self.Port(Ground.empty())
self.low_out = self.Port(VoltageSource.empty())
self.low_boot_in = self.Port(VoltageSink.empty()) # bootstrap voltage for the prior cell, except if is_first
self.low_boot_out = self.Port(VoltageSource.empty()) # bootstrap voltage for this cell
@@ -73,7 +73,7 @@ def __init__(self, is_first: BoolLike = False, *,
self.high_boot_in = self.Port(VoltageSink.empty())
# control signals
- self.gnd_ctl = self.Port(VoltageSink.empty())
+ self.gnd_ctl = self.Port(Ground.empty())
self.pwr_ctl = self.Port(VoltageSink.empty())
self.low_pwm = self.Port(DigitalSink.empty())
self.high_pwm = self.Port(DigitalSink.empty())
@@ -92,7 +92,7 @@ def generate(self):
if self.get(self.is_first):
low_pwm: Port[DigitalLink] = self.low_pwm
high_pwm: Port[DigitalLink] = self.high_pwm
- self.gnd_ctl.init_from(VoltageSink()) # ideal port, not connected
+ self.gnd_ctl.init_from(Ground()) # ideal port, not connected
self.pwr_ctl.init_from(VoltageSink()) # ideal port, not connected
else:
self.ldo = self.Block(LinearRegulator(output_voltage=3.3*Volt(tol=0.1)))
@@ -114,7 +114,7 @@ def generate(self):
driver_indep = self.driver.with_mixin(HalfBridgeDriverIndependent())
self.connect(driver_indep.high_in, high_pwm)
self.connect(driver_indep.low_in, low_pwm)
- self.connect(self.driver.high_gnd, self.high_out)
+ self.connect(self.driver.high_gnd, self.high_out.as_ground((0, 0)*Amp)) # TODO model driver current
if self.get(self.high_boot_out.is_connected()): # leave port disconnected if not used, to avoid an unsolved interface
self.connect(self.driver.high_pwr, self.high_boot_out) # schematic connected to boot diode
@@ -155,9 +155,7 @@ def generate(self):
'high_boot_out_node': self.driver.high_pwr
},
conversions={
- 'low_in': VoltageSink(
- current_draw=self.low_out.link().current_drawn
- ),
+ 'low_in': Ground(), # TODO better conventions for Ground vs VoltageSink|Source
'low_out': VoltageSource(
voltage_out=self.low_in.link().voltage
),
@@ -248,7 +246,7 @@ def generate(self):
self.connect(sw.high_in, self.pwr_in)
self.connect(sw.low_boot_in, self.pwr_gate)
else:
- self.connect(sw.low_in, last_sw.low_out)
+ self.connect(sw.low_in, last_sw.low_out.as_ground((0, 0)*Amp)) # TODO ground current modeling
self.connect(sw.high_in, last_sw.high_out)
self.connect(sw.low_boot_in, last_sw.low_boot_out)
self.connect(sw.high_boot_out, last_sw.high_boot_in)
@@ -276,13 +274,11 @@ def contents(self) -> None:
self.vusb_merge = self.Block(MergedVoltageSource()).connected_from(
self.usb_mcu.pwr, self.usb_fpga.pwr)
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.usb_mcu.gnd, self.usb_fpga.gnd, self.conv_in.gnd)
self.vusb = self.connect(self.vusb_merge.pwr_out)
- self.gnd = self.connect(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.usb_mcu.gnd, self.usb_fpga.gnd, self.conv_in.gnd)
self.tp_vusb = self.Block(VoltageTestPoint()).connected(self.vusb_merge.pwr_out)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.gnd_merge.pwr_out)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb_mcu.gnd)
# POWER
with self.implicit_connect(
@@ -314,7 +310,7 @@ def contents(self) -> None:
self.connect(self.conv.pwr_gate, self.vgate)
self.connect(self.conv.pwr_ctl, self.v3v3)
self.tp_conv_out = self.Block(VoltageTestPoint()).connected(self.conv.pwr_out)
- self.tp_conv_gnd = self.Block(VoltageTestPoint()).connected(self.conv.gnd)
+ self.tp_conv_gnd = self.Block(GroundTestPoint()).connected(self.conv.gnd)
# 3V3 DOMAIN
with self.implicit_connect(
diff --git a/examples/test_high_switch.py b/examples/test_high_switch.py
index 91f19aa0c..89df26b32 100644
--- a/examples/test_high_switch.py
+++ b/examples/test_high_switch.py
@@ -19,9 +19,6 @@ def __init__(self) -> None:
self.pwr = self.Port(VoltageSink.empty(), [Power])
self.gnd = self.Port(Ground.empty(), [Common])
- self.can_pwr = self.Port(VoltageSource.empty(), optional=True)
- self.can_gnd = self.Port(GroundSource.empty(), optional=True)
-
self.controller = self.Port(CanTransceiverPort.empty(), [Input])
self.can = self.Port(CanDiffPort.empty(), optional=True)
@@ -32,12 +29,11 @@ def contents(self):
self.connect(self.can, self.conn.differential)
self.can_fuse = self.Block(SeriesPowerPptcFuse(150 * mAmp(tol=0.1)))
- self.connect(self.conn.pwr, self.can_pwr, self.can_fuse.pwr_in)
- self.connect(self.conn.gnd, self.can_gnd)
+ self.connect(self.conn.pwr, self.can_fuse.pwr_in)
with self.implicit_connect(
ImplicitConnect(self.can_fuse.pwr_out, [Power]),
- ImplicitConnect(self.can_gnd, [Common]),
+ ImplicitConnect(self.conn.gnd, [Common]),
) as imp:
self.reg = imp.Block(Ap2204k(5*Volt(tol=0.05))) # TODO: replace with generic LinearRegulator?
@@ -52,7 +48,7 @@ def contents(self):
self.connect(self.transceiver.controller, self.controller)
self.connect(self.transceiver.can, self.can)
self.connect(self.transceiver.can_pwr, self.reg.pwr_out)
- self.connect(self.transceiver.can_gnd, self.can_gnd)
+ self.connect(self.transceiver.can_gnd, self.conn.gnd)
class CanFuse(PptcFuse, FootprintBlock):
@@ -84,7 +80,7 @@ def __init__(self) -> None:
voltage_out=12 * Volt(tol=0.1),
current_limits=(0, 3) * Amp # TODO get actual limits from LVPDB?
))
- self.gnd = self.Port(GroundSource())
+ self.gnd = self.Port(Ground())
def contents(self):
super().contents()
@@ -108,7 +104,7 @@ def __init__(self) -> None:
voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick?
current_limits=(0, 0.15) * Amp # TODO get actual limits from ???
))
- self.gnd = self.Port(GroundSource())
+ self.gnd = self.Port(Ground())
self.differential = self.Port(CanDiffPort(), [Output])
def contents(self):
@@ -135,7 +131,7 @@ def __init__(self) -> None:
voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick?
current_limits=(0, 0.15) * Amp # TODO get actual limits from ???
))
- self.gnd = self.Port(GroundSource())
+ self.gnd = self.Port(Ground())
self.differential = self.Port(CanDiffPort(), [Output])
def contents(self):
@@ -162,7 +158,7 @@ def __init__(self) -> None:
voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick?
current_limits=(0, 0.15) * Amp # TODO get actual limits from ???
))
- self.gnd = self.Port(GroundSource())
+ self.gnd = self.Port(Ground())
self.differential = self.Port(CanDiffPort(), [Output])
def contents(self):
@@ -265,12 +261,6 @@ def contents(self) -> None:
(self.can, ), self.can_chain = self.chain(self.mcu.with_mixin(IoControllerCan()).can.request('can'),
imp.Block(CalSolCanBlock()))
- # TODO need proper support for exported unconnected ports
- self.can_gnd_load = self.Block(DummyVoltageSink())
- self.connect(self.can.can_gnd, self.can_gnd_load.pwr)
- self.can_pwr_load = self.Block(DummyVoltageSink())
- self.connect(self.can.can_pwr, self.can_pwr_load.pwr)
-
(self.vsense, ), _ = self.chain( # TODO update to use VoltageSenseDivider
self.vin,
imp.Block(VoltageDivider(output_voltage=3 * Volt(tol=0.15), impedance=(100, 1000) * Ohm)),
diff --git a/examples/test_iot_display.py b/examples/test_iot_display.py
index 75c98e17a..39e4a9676 100644
--- a/examples/test_iot_display.py
+++ b/examples/test_iot_display.py
@@ -55,12 +55,10 @@ def contents(self) -> None:
self.usb = self.Block(UsbCReceptacle(current_limits=(0, 3)*Amp))
self.batt = self.Block(LipoConnector(voltage=BATTERY_VOLTAGE, actual_voltage=BATTERY_VOLTAGE)) # 2-6 AA
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.usb.gnd, self.batt.gnd)
- self.gnd = self.connect(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.usb.gnd, self.batt.gnd)
self.tp_pwr = self.Block(VoltageTestPoint("batt")).connected(self.batt.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.gnd_merge.pwr_out)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_iot_fan.py b/examples/test_iot_fan.py
index 185f834ae..c29f6a7cf 100644
--- a/examples/test_iot_fan.py
+++ b/examples/test_iot_fan.py
@@ -17,7 +17,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.pwr.gnd)
self.tp_pwr = self.Block(VoltageTestPoint()).connected(self.pwr.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.pwr.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.pwr.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_iot_iron.py b/examples/test_iot_iron.py
index a9d7d5807..85730b580 100644
--- a/examples/test_iot_iron.py
+++ b/examples/test_iot_iron.py
@@ -7,22 +7,28 @@ class IronConnector(Connector, Block):
"""See main design for details about pinning and compatibility.
This assumes a common ground with heater+ and thermocouple+.
TODO: support series heater and thermocouple, requires additional protection circuits on amps
+ TODO: optional generation for isense_res, if not connected
"""
@init_in_parent
- def __init__(self):
+ def __init__(self, *, isense_resistance: RangeLike = 22*mOhm(tol=0.05), current_draw: RangeLike=(0, 3.25)*Amp):
super().__init__()
self.conn = self.Block(PinHeader254(3))
- self.gnd = self.Export(self.conn.pins.request('1').adapt_to(Ground()),
- [Common])
+ self.gnd = self.Port(Ground.empty(), [Common])
self.pwr = self.Export(self.conn.pins.request('2').adapt_to(VoltageSink(
- current_draw=(0, 3.25)*Amp
+ current_draw=current_draw
)))
self.thermocouple = self.Export(self.conn.pins.request('3').adapt_to(AnalogSource(
voltage_out=self.gnd.link().voltage + (0, 14.3)*mVolt,
signal_out=self.gnd.link().voltage + (0, 14.3)*mVolt # up to ~350 C
)), optional=True)
+ self.isense_res = self.Block(CurrentSenseResistor(resistance=isense_resistance, sense_in_reqd=False))
+ self.isense = self.Export(self.isense_res.sense_out)
+ self.connect(self.conn.pins.request('1').adapt_to(VoltageSink(current_draw=current_draw)),
+ self.isense_res.pwr_out)
+ self.connect(self.gnd.as_voltage_source(), self.isense_res.pwr_in)
+
class IotIron(JlcBoardTop):
"""IoT soldering iron controller (ceramic heater type, not RF heating type) with USB-PD in,
@@ -41,7 +47,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.usb.gnd)
self.tp_pwr = self.Block(VoltageTestPoint()).connected(self.usb.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.usb.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# POWER
with self.implicit_connect(
@@ -147,16 +153,8 @@ def contents(self) -> None:
imp.Block(FootprintToucbPad('edg:Symbol_DucklingSolid'))
)
- self.iron = self.Block(IronConnector())
- self.connect(self.conv.pwr_out, self.iron.pwr)
-
- self.isense = self.Block(CurrentSenseResistor(resistance=22*mOhm(tol=0.05), sense_in_reqd=False))
- self.connect(self.isense.pwr_in, self.gnd)
- (self.isense_force, ), _ = self.chain(
- self.isense.pwr_out, # gnd currents not modeled, this forces one for sense resistor power
- self.Block(ForcedVoltageCurrentDraw(forced_current_draw=self.iron.pwr.link().current_drawn)),
- self.iron.gnd
- )
+ self.iron = imp.Block(IronConnector())
+ self.connect(self.conv.pwr_out, self.iron.pwr)
# IRON SENSE AMPS - 3v3 DOMAIN
with self.implicit_connect(
@@ -172,7 +170,7 @@ def contents(self) -> None:
self.mcu.adc.request('iron_vsense')
)
(self.ifilt, self.tp_i, self.iamp), _ = self.chain(
- self.isense.sense_out,
+ self.iron.isense,
imp.Block(Amplifier((18, 25))),
imp.Block(rc_filter_model),
self.Block(AnalogTestPoint()),
@@ -183,7 +181,7 @@ def contents(self) -> None:
ratio=(150, 165),
input_impedance=(0.9, 5)*kOhm
))
- self.connect(self.tamp.input_negative, self.iron.gnd.as_analog_source())
+ self.connect(self.tamp.input_negative, self.iron.isense)
self.connect(self.tamp.input_positive, self.iron.thermocouple)
self.connect(self.tamp.output, self.mcu.adc.request('thermocouple'))
self.tp_t = self.Block(AnalogTestPoint()).connected(self.iron.thermocouple)
@@ -229,8 +227,8 @@ def refinements(self) -> Refinements:
]),
(['mcu', 'programming'], 'uart-auto'),
- (['isense', 'res', 'res', 'smd_min_package'], '2512'), # more power headroom
- (['isense', 'res', 'res', 'require_basic_part'], False),
+ (['iron', 'isense_res', 'res', 'res', 'smd_min_package'], '2512'), # more power headroom
+ (['iron', 'isense_res', 'res', 'res', 'require_basic_part'], False),
# these will be enforced by the firmware control mechanism
# (['conv', 'pwr_in', 'current_draw'], Range(0, 3)), # max 3A input draw
diff --git a/examples/test_iot_knob.py b/examples/test_iot_knob.py
index 5ecd367ec..e46ccd6b0 100644
--- a/examples/test_iot_knob.py
+++ b/examples/test_iot_knob.py
@@ -19,7 +19,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.usb.gnd)
self.tp_pwr = self.Block(VoltageTestPoint()).connected(self.usb.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.usb.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_iot_led_driver.py b/examples/test_iot_led_driver.py
index e1803eab0..ced2273a8 100644
--- a/examples/test_iot_led_driver.py
+++ b/examples/test_iot_led_driver.py
@@ -17,7 +17,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.pwr.gnd)
self.tp_pwr = self.Block(VoltageTestPoint()).connected(self.pwr.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.pwr.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.pwr.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_jd_keyswitch.py b/examples/test_jd_keyswitch.py
index 632c11120..e4dd34ded 100644
--- a/examples/test_jd_keyswitch.py
+++ b/examples/test_jd_keyswitch.py
@@ -12,8 +12,8 @@ def contents(self) -> None:
self.edge2 = self.create_edge()
# TODO should connect to the nets, once .connected can take a Connection
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.edge2.gnd)
self.tp_jd_pwr = self.Block(VoltageTestPoint()).connected(self.edge2.jd_pwr_sink)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.edge2.gnd_sink)
# POWER
with self.implicit_connect(
diff --git a/examples/test_ledmatrix.py b/examples/test_ledmatrix.py
index 49fc420ae..7237c9547 100644
--- a/examples/test_ledmatrix.py
+++ b/examples/test_ledmatrix.py
@@ -15,7 +15,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.usb.gnd)
self.tp_vusb = self.Block(VoltageTestPoint()).connected(self.usb.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.usb.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_multimeter.py b/examples/test_multimeter.py
index 99c2d0580..755d064c3 100644
--- a/examples/test_multimeter.py
+++ b/examples/test_multimeter.py
@@ -177,10 +177,7 @@ def contents(self) -> None:
# so the PD port can be connected to a dedicated power brick.
self.data_usb = self.Block(UsbCReceptacle())
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.bat.gnd, self.data_usb.gnd)
-
- self.gnd = self.connect(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.bat.gnd, self.data_usb.gnd)
self.vbat = self.connect(self.bat.pwr)
# POWER
@@ -277,7 +274,7 @@ def contents(self) -> None:
# and Vdd/2 (high impedance, but can measure negative voltages)
self.inn = self.Block(BananaSafetyJack())
self.inn_mux = imp.Block(AnalogMuxer()).mux_to(
- inputs=[self.gnd_merge.pwr_out.as_analog_source(), self.ref_buf.output]
+ inputs=[self.bat.gnd.as_analog_source(), self.ref_buf.output]
)
self.inn_merge = self.Block(MergedAnalogSource()).connected_from(
self.inn_mux.out, self.inn.port.adapt_to(AnalogSource()))
diff --git a/examples/test_pcbbot.py b/examples/test_pcbbot.py
index 25666138e..961ba3f21 100644
--- a/examples/test_pcbbot.py
+++ b/examples/test_pcbbot.py
@@ -38,11 +38,8 @@ def contents(self) -> None:
self.batt = self.Block(LipoConnector(actual_voltage=(3.7, 4.2)*Volt))
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.usb.gnd, self.batt.gnd
- )
- self.gnd = self.connect(self.gnd_merge.pwr_out)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.usb.gnd, self.batt.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# POWER
with self.implicit_connect(
@@ -58,7 +55,7 @@ def contents(self) -> None:
self.pwr_or = self.Block(PriorityPowerOr( # also does reverse protection
(0, 1)*Volt, (0, 0.1)*Ohm
- )).connected_from(self.gnd_merge.pwr_out, self.usb.pwr, self.gate.pwr_out)
+ )).connected_from(self.usb.gnd, self.usb.pwr, self.gate.pwr_out)
self.pwr = self.connect(self.pwr_or.pwr_out)
(self.reg_3v3, self.prot_3v3, self.tp_3v3), _ = self.chain(
diff --git a/examples/test_protected_charger.py b/examples/test_protected_charger.py
index 3d4de116a..8c6a9c592 100644
--- a/examples/test_protected_charger.py
+++ b/examples/test_protected_charger.py
@@ -19,11 +19,8 @@ def contents(self) -> None:
self.batt = self.Block(LipoConnector(actual_voltage=(3.7, 4.2) * Volt))
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.usb.gnd, self.batt.gnd
- )
- self.gnd = self.connect(self.gnd_merge.pwr_out)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.usb.gnd, self.batt.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
with self.implicit_connect(
ImplicitConnect(self.gnd, [Common]),
diff --git a/examples/test_robotcrawler.py b/examples/test_robotcrawler.py
index e416d8115..8cd89dd49 100644
--- a/examples/test_robotcrawler.py
+++ b/examples/test_robotcrawler.py
@@ -45,6 +45,7 @@ def __init__(self) -> None:
for i in range(self.SERVO_CAM_COUNT):
self.servos_cam[str(i)] = self.Block(ServoFeedbackConnector())
+
class RobotCrawler(RobotCrawlerSpec, JlcBoardTop):
"""Implementation of the crawler robot, that implements what is needed to connect the interface blocks
as well as optional additional blocks.
@@ -56,7 +57,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.batt.gnd)
self.tp_vbatt = self.Block(VoltageTestPoint()).connected(self.batt.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.batt.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.batt.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_robotdriver.py b/examples/test_robotdriver.py
index ab6c2b74f..279e5c056 100644
--- a/examples/test_robotdriver.py
+++ b/examples/test_robotdriver.py
@@ -67,7 +67,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.batt.gnd)
self.tp_vbatt = self.Block(VoltageTestPoint()).connected(self.isense.pwr_out)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.batt.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.batt.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_robotowl.py b/examples/test_robotowl.py
index f340a253f..4061887b6 100644
--- a/examples/test_robotowl.py
+++ b/examples/test_robotowl.py
@@ -48,11 +48,11 @@ def contents(self) -> None:
mcu_usb = self.mcu.with_mixin(IoControllerUsbOut())
mcu_i2s = self.mcu.with_mixin(IoControllerI2s())
- self.gnd = self.connect(mcu_pwr.gnd_out)
+ self.gnd = self.connect(self.mcu.gnd)
self.vusb = self.connect(mcu_usb.vusb_out)
self.v3v3 = self.connect(mcu_pwr.pwr_out)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(mcu_pwr.gnd_out)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.mcu.gnd)
self.tp_usb = self.Block(VoltageTestPoint()).connected(mcu_usb.vusb_out)
self.tp_3v3 = self.Block(VoltageTestPoint()).connected(mcu_pwr.pwr_out)
diff --git a/examples/test_seven_segment.py b/examples/test_seven_segment.py
index 32ee24aea..91d8d6549 100644
--- a/examples/test_seven_segment.py
+++ b/examples/test_seven_segment.py
@@ -14,7 +14,7 @@ def contents(self) -> None:
self.gnd = self.connect(self.pwr_conn.gnd)
self.tp_pwr = self.Block(VoltageTestPoint()).connected(self.pwr_conn.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.pwr_conn.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.pwr_conn.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_simon.py b/examples/test_simon.py
index 68fc7c6c4..27fbd1bca 100644
--- a/examples/test_simon.py
+++ b/examples/test_simon.py
@@ -41,7 +41,7 @@ def contents(self) -> None:
self.v5v = self.connect(mcu_usb.vusb_out)
self.v3v3 = self.connect(mcu_pwr.pwr_out)
- self.gnd = self.connect(mcu_pwr.gnd_out)
+ self.gnd = self.connect(self.mcu.gnd)
with self.implicit_connect(
ImplicitConnect(self.v5v, [Power]),
diff --git a/examples/test_tofarray.py b/examples/test_tofarray.py
index 0ab04c2da..806c145fd 100644
--- a/examples/test_tofarray.py
+++ b/examples/test_tofarray.py
@@ -8,7 +8,7 @@ def __init__(self) -> None:
super().__init__()
self.pwr = self.Port(VoltageSource.empty(), optional=True)
- self.gnd = self.Port(GroundSource.empty())
+ self.gnd = self.Port(Ground.empty())
self.differential = self.Port(CanDiffPort.empty(), [Output])
self.conn = self.Block(PassiveConnector())
@@ -16,7 +16,7 @@ def __init__(self) -> None:
voltage_out=(7, 14) * Volt, # TODO get limits from CAN power brick?
current_limits=(0, 0.15) * Amp # TODO get actual limits from ???
)))
- self.connect(self.gnd, self.conn.pins.request('3').adapt_to(GroundSource()))
+ self.connect(self.gnd, self.conn.pins.request('3').adapt_to(Ground()))
self.connect(self.differential.canh, self.conn.pins.request('4').adapt_to(DigitalSource()))
self.connect(self.differential.canl, self.conn.pins.request('5').adapt_to(DigitalSource()))
@@ -37,12 +37,10 @@ def contents(self) -> None:
self.can = self.Block(CanConnector())
self.vusb = self.connect(self.usb.pwr)
- self.gnd_merge = self.Block(MergedVoltageSource()).connected_from(
- self.usb.gnd, self.can.gnd)
- self.gnd = self.connect(self.gnd_merge.pwr_out)
+ self.gnd = self.connect(self.usb.gnd, self.can.gnd)
self.tp_vusb = self.Block(VoltageTestPoint()).connected(self.usb.pwr)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.usb.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# POWER
with self.implicit_connect(
diff --git a/examples/test_usb_source_measure.py b/examples/test_usb_source_measure.py
index 9c32009b3..44b160d8e 100644
--- a/examples/test_usb_source_measure.py
+++ b/examples/test_usb_source_measure.py
@@ -4,6 +4,7 @@
from edg.abstract_parts.ESeriesUtil import ESeriesRatioUtil
from edg.abstract_parts.ResistiveDivider import DividerValues
from edg.electronics_model.VoltagePorts import VoltageSinkAdapterAnalogSource # needed by imported schematic
+from edg.electronics_model.GroundPort import GroundAdapterAnalogSource # needed by imported schematic
from edg import *
@@ -294,7 +295,7 @@ def __init__(self, current: RangeLike, rds_on: RangeLike):
self.ref_center = self.Port(AnalogSink.empty())
self.pwr_gate_pos = self.Port(VoltageSink.empty())
- self.pwr_gate_neg = self.Port(VoltageSink.empty())
+ self.pwr_gate_neg = self.Port(Ground.empty())
self.control_voltage = self.Port(AnalogSink.empty())
self.control_current_source = self.Port(AnalogSink.empty())
@@ -373,7 +374,7 @@ def contents(self) -> None:
self.usb = self.Block(UsbCReceptacle(voltage_out=(9, 20)*Volt, current_limits=(0, 8)*Amp))
self.gnd = self.connect(self.usb.gnd)
- self.tp_gnd = self.Block(VoltageTestPoint()).connected(self.usb.gnd)
+ self.tp_gnd = self.Block(GroundTestPoint()).connected(self.usb.gnd)
# power supplies
with self.implicit_connect(
@@ -464,7 +465,8 @@ def contents(self) -> None:
imp.Block(Lm2664(output_ripple_limit=5*mVolt)),
self.Block(VoltageTestPoint("vc-"))
)
- self.vcontroln = self.connect(self.reg_vcontroln.pwr_out)
+ self.vcontroln = self.connect(self.reg_vcontroln.pwr_out.as_ground(
+ current_draw=self.reg_vcontrol.pwr_out.link().current_drawn))
# power path domain
with self.implicit_connect(
@@ -478,10 +480,7 @@ def contents(self) -> None:
self.connect(self.vanalog, self.control.pwr_logic)
self.connect(self.vcenter, self.control.ref_center)
- # TODO: support non-zero grounds
- self.vcontroln_forced = self.Block(ForcedVoltageCurrent(0*Volt(tol=0), self.control.pwr_gate_pos.current_draw))
- self.connect(self.vcontroln_forced.pwr_in, self.vcontroln)
- self.connect(self.vcontroln_forced.pwr_out, self.control.pwr_gate_neg)
+ self.connect(self.vcontroln, self.control.pwr_gate_neg)
self.connect(self.vcontrol, self.control.pwr_gate_pos)
# logic domain