Ports on the same line are not getting parsed while running NgVeri

[Eyantra698Sumanto]

Description

Ports on the same line are not getting parsed while running NgVeri

Steps to Reproduce

• Save the following file as add.v using a text editor.

module add(input [3:0] A, input [3:0] B, output [3:0] S, output C);
wire [3:0] carry;
assign carry[0] = 1'b0; // No carry in for least significant bit
assign carry[1] = A[0] & B[0]; // Carry generated by bit 0
assign carry[2] = (A[1] & B[1]) | (carry[1] & (A[1] ^ B[1])); // Carry generated by bit 1
assign carry[3] = (A[2] & B[2]) | (carry[2] & (A[2] ^ B[2])); // Carry generated by bit 2
// Generate the sum bits for each bit position
assign S[0] = A[0] ^ B[0]; // Sum for bit 0
assign S[1] = A[1] ^ B[1] ^ carry[1]; // Sum for bit 1
assign S[2] = A[2] ^ B[2] ^ carry[2]; // Sum for bit 2
assign S[3] = A[3] ^ B[3] ^ carry[3]; // Sum for bit 3
// Generate the overall carry output
assign C = carry[3];
endmodule

• Open eSim
• Click on the Makerchip-NgVeri icon on the Left-Hand Side toolbar
• Add the file using the Add Top Level Verilog File button
• Run Convert Verilog to Ngspice from the NgVeri tab.
• The error occurs.

Expected Behavior

• The following code works fine:

module add(
input [3:0] A, 
input [3:0] B, 
input Cin,
output [3:0] S, 
output C);
// S is the sum output and C is the carry output
// A and B are the inputs
// Generate the carry bits for each bit position
wire [3:0] carry;
assign carry[0] = Cin; // No carry in for least significant bit
assign carry[1] = A[0] & B[0]; // Carry generated by bit 0
assign carry[2] = (A[1] & B[1]) | (carry[1] & (A[1] ^ B[1])); // Carry generated by bit 1
assign carry[3] = (A[2] & B[2]) | (carry[2] & (A[2] ^ B[2])); // Carry generated by bit 2
// Generate the sum bits for each bit position
assign S[0] = A[0] ^ B[0]; // Sum for bit 0
assign S[1] = A[1] ^ B[1] ^ carry[1]; // Sum for bit 1
assign S[2] = A[2] ^ B[2] ^ carry[2]; // Sum for bit 2
assign S[3] = A[3] ^ B[3] ^ carry[3]; // Sum for bit 3
// Generate the overall carry output
assign C = carry[3];
endmodule

• The code should work fine even with one line declaration of the ports

Screenshots

Version and OS

• eSim version: 2.4
• OS: Windows 11, 64 bit

Additional Context