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Layout efficiency: Substrate tap, nwell tap, vias, improved MOSFET cells #265

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hpretl opened this issue Nov 16, 2024 · 0 comments

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hpretl commented Nov 16, 2024

Maybe I just don't know how to do it properly, but it looks like a few fundamental thing are still missing from the KLayout setup:

Via generator (with selectable start and end layers, and number of X/Y multiples)
Substrate contact (maybe merge into via generator); ideal would be the possibility to make a substrate contact as a path
Option to NMOS pcell to add a guardings
Nwell contact (maybe merge into via generator); ideal would be the possibility to make an nwell contact as a path
Option to PMOS pcell to add a guardings

In addition, it would be good have the option in the MOSFET pcells to have the gates connected.

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