You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Thanks for the pointer, you are absolutely right! I totally missed it because there is no pcell in KLayout (at least none that I can find) and no mention in the process description, but there is a model and symbol for simulation and a fixed layout in sg13g2_pr.gds.
@KrzysztofHerman@sergeiandreyev Are there plans to provide a pcell, or is there one fixed size of PNP with a fixed layout (which is quite the norm for parasitic PNPs)? In any case, a description in the SG13G2_process_spec.pdf would be great!
For CMOS-only designs, an NPN or PNP (either lateral or vertical) would be needed for bandgaps and similar uses.
The text was updated successfully, but these errors were encountered: