diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index b56bb73c..d9f19d8d 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -30,7 +30,7 @@ jobs:
     if: ${{ !cancelled() }}
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: run spi test
@@ -43,7 +43,7 @@ jobs:
     if: ${{ !cancelled() }}
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: run uart16550 test
@@ -56,7 +56,7 @@ jobs:
     if: ${{ !cancelled() }}
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: clean
@@ -73,7 +73,7 @@ jobs:
     if: ${{ !cancelled() }}
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: clean
@@ -93,7 +93,7 @@ jobs:
     needs: [ verilator-baremetal ]
   
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: test baremetal
@@ -110,7 +110,7 @@ jobs:
     needs: [ verilator-baremetal ]
   
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: test baremetal
@@ -125,7 +125,7 @@ jobs:
 ##    needs: [ cyclonev, aes-ku040 ]
 ##  
 ##    steps:
-##      - uses: actions/checkout@v3
+##      - uses: actions/checkout@v4
 ##        with:
 ##          submodules: 'recursive'
 ##      - name: clean
diff --git a/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_opencryptolinux_fpga_wrapper.v b/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_opencryptolinux_fpga_wrapper.v
new file mode 100644
index 00000000..c9142e74
--- /dev/null
+++ b/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_opencryptolinux_fpga_wrapper.v
@@ -0,0 +1,347 @@
+`timescale 1ns / 1ps
+`include "bsp.vh"
+`include "iob_soc_opencryptolinux_conf.vh"
+
+module iob_soc_opencryptolinux_fpga_wrapper (
+
+   //differential clock input and reset
+   input c0_sys_clk_clk_p,
+   input c0_sys_clk_clk_n,
+   input reset,
+
+   //uart
+   output txd_o,
+   input  rxd_i,
+
+   //spi
+   output spi_SS_o,
+   output spi_SCLK_o,
+   inout spi_MISO_io,
+   inout spi_MOSI_io,
+   inout spi_WP_N_io,
+   inout spi_HOLD_N_io,
+
+`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_EXTMEM
+   output        c0_ddr4_act_n,
+   output [16:0] c0_ddr4_adr,
+   output [ 1:0] c0_ddr4_ba,
+   output [ 0:0] c0_ddr4_bg,
+   output [ 0:0] c0_ddr4_cke,
+   output [ 0:0] c0_ddr4_odt,
+   output [ 0:0] c0_ddr4_cs_n,
+   output [ 0:0] c0_ddr4_ck_t,
+   output [ 0:0] c0_ddr4_ck_c,
+   output        c0_ddr4_reset_n,
+   inout  [ 3:0] c0_ddr4_dm_dbi_n,
+   inout  [31:0] c0_ddr4_dq,
+   inout  [ 3:0] c0_ddr4_dqs_c,
+   inout  [ 3:0] c0_ddr4_dqs_t,
+`endif
+
+`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET
+   output ENET_RESETN,
+   input  ENET_RX_CLK,
+   output ENET_GTX_CLK,
+   input  ENET_RX_D0,
+   input  ENET_RX_D1,
+   input  ENET_RX_D2,
+   input  ENET_RX_D3,
+   input  ENET_RX_DV,
+   //input  ENET_RX_ERR,
+   output ENET_TX_D0,
+   output ENET_TX_D1,
+   output ENET_TX_D2,
+   output ENET_TX_D3,
+   output ENET_TX_EN,
+   //output ENET_TX_ERR,
+`endif
+
+   output trap
+);
+
+   localparam AXI_ID_W = 4;
+   localparam AXI_LEN_W = 8;
+   localparam AXI_ADDR_W = `DDR_ADDR_W;
+   localparam AXI_DATA_W = `DDR_DATA_W;
+
+   `include "iob_soc_opencryptolinux_wrapper_pwires.vs"
+
+   wire clk;
+   wire arst;
+
+
+   // 
+   // Logic to contatenate data pins and ethernet clock
+   //
+`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_ETHERNET
+   //buffered eth clock
+   wire       ETH_Clk;
+
+   //eth clock
+   BUFGCE_1 rxclk_buf (
+      .I(ENET_RX_CLK),
+      .CE(1'b1),
+      .O(ETH_Clk)
+   );
+   ODDRE1 ODDRE1_inst (
+      .Q (ENET_GTX_CLK),
+      .C (ETH_Clk),
+      .D1(1'b1),
+      .D2(1'b0),
+      .SR(~ENET_RESETN)
+   );
+
+   //MII
+   assign ETH0_MRxClk = ETH_Clk;
+   assign ETH0_MRxD = {ENET_RX_D3, ENET_RX_D2, ENET_RX_D1, ENET_RX_D0};
+   assign ETH0_MRxDv = ENET_RX_DV;
+   //assign ETH0_MRxErr = ENET_RX_ERR;
+   assign ETH0_MRxErr = 1'b0;
+
+   assign ETH0_MTxClk = ETH_Clk;
+   assign {ENET_TX_D3, ENET_TX_D2, ENET_TX_D1, ENET_TX_D0} = ETH0_MTxD;
+   assign ENET_TX_EN = ETH0_MTxEn;
+   //assign ENET_TX_ERR = ETH0_MTxErr;
+
+   assign ENET_RESETN = ETH0_phy_rstn_o;
+
+   assign ETH0_MColl = 1'b0;
+   assign ETH0_MCrS = 1'b0;
+`endif
+
+
+   //
+   // IOb-SoC
+   //
+
+   iob_soc_opencryptolinux #(
+      .AXI_ID_W  (AXI_ID_W),
+      .AXI_LEN_W (AXI_LEN_W),
+      .AXI_ADDR_W(AXI_ADDR_W),
+      .AXI_DATA_W(AXI_DATA_W)
+   ) iob_soc_opencryptolinux0 (
+      `include "iob_soc_opencryptolinux_pportmaps.vs"
+      .clk_i (clk),
+      .cke_i (1'b1),
+      .arst_i(arst),
+      .trap_o(trap)
+   );
+   
+   // UART
+   assign txd_o = uart_txd_o;
+   assign uart_rxd_i = rxd_i;
+   assign uart_cts_i = 1'b1;
+   // uart_rts_o unconnected
+   
+   // SPI
+   assign spi_SS_o = spi_SS;
+   assign spi_SCLK_o = spi_SCLK;
+   assign spi_MISO_io = spi_MISO;
+   assign spi_MOSI_io = spi_MOSI;
+   assign spi_WP_N_io = spi_WP_N;
+   assign spi_HOLD_N_io = spi_HOLD_N;
+
+   //
+   // DDR4 CONTROLLER
+   //
+
+`ifdef IOB_SOC_OPENCRYPTOLINUX_USE_EXTMEM
+   localparam DDR4_AXI_ID_W = AXI_ID_W;
+   localparam DDR4_AXI_LEN_W = AXI_LEN_W;
+   localparam DDR4_AXI_ADDR_W = AXI_ADDR_W;
+   localparam DDR4_AXI_DATA_W = AXI_DATA_W;
+
+
+   `include "iob_soc_opencryptolinux_ku040_rstn.vs"
+
+   //axi wires between ddr4 contrl and axi interconnect
+   `include "ddr4_axi_wire.vs"
+
+   //DDR4 controller axi side clocks and resets
+   wire c0_ddr4_ui_clk;  //controller output clock 200MHz
+   wire ddr4_axi_arstn;  //controller input
+
+   wire c0_ddr4_ui_clk_sync_rst;
+
+   wire calib_done;
+
+
+   //
+   // ASYNC AXI BRIDGE (between user logic (clk) and DDR controller (c0_ddr4_ui_clk)
+   //
+   axi_interconnect_0 axi_async_bridge (
+      .INTERCONNECT_ACLK   (c0_ddr4_ui_clk),           //from ddr4 controller 
+      .INTERCONNECT_ARESETN(~c0_ddr4_ui_clk_sync_rst), //from ddr4 controller
+
+      `include "iob_soc_opencryptolinux_ku040_interconnect_s_portmap.vs"
+
+      //
+      // DDR CONTROLLER SIDE (master)
+      //
+
+      .M00_AXI_ARESET_OUT_N(ddr4_axi_arstn),  //to ddr controller axi slave port
+      .M00_AXI_ACLK        (c0_ddr4_ui_clk),  //from ddr4 controller 200MHz clock
+
+      //Write address
+      .M00_AXI_AWID   (ddr4_axi_awid),
+      .M00_AXI_AWADDR (ddr4_axi_awaddr),
+      .M00_AXI_AWLEN  (ddr4_axi_awlen),
+      .M00_AXI_AWSIZE (ddr4_axi_awsize),
+      .M00_AXI_AWBURST(ddr4_axi_awburst),
+      .M00_AXI_AWLOCK (ddr4_axi_awlock[0]),
+      .M00_AXI_AWCACHE(ddr4_axi_awcache),
+      .M00_AXI_AWPROT (ddr4_axi_awprot),
+      .M00_AXI_AWQOS  (ddr4_axi_awqos),
+      .M00_AXI_AWVALID(ddr4_axi_awvalid),
+      .M00_AXI_AWREADY(ddr4_axi_awready),
+
+      //Write data
+      .M00_AXI_WDATA (ddr4_axi_wdata),
+      .M00_AXI_WSTRB (ddr4_axi_wstrb),
+      .M00_AXI_WLAST (ddr4_axi_wlast),
+      .M00_AXI_WVALID(ddr4_axi_wvalid),
+      .M00_AXI_WREADY(ddr4_axi_wready),
+
+      //Write response
+      .M00_AXI_BID   (ddr4_axi_bid),
+      .M00_AXI_BRESP (ddr4_axi_bresp),
+      .M00_AXI_BVALID(ddr4_axi_bvalid),
+      .M00_AXI_BREADY(ddr4_axi_bready),
+
+      //Read address
+      .M00_AXI_ARID   (ddr4_axi_arid),
+      .M00_AXI_ARADDR (ddr4_axi_araddr),
+      .M00_AXI_ARLEN  (ddr4_axi_arlen),
+      .M00_AXI_ARSIZE (ddr4_axi_arsize),
+      .M00_AXI_ARBURST(ddr4_axi_arburst),
+      .M00_AXI_ARLOCK (ddr4_axi_arlock[0]),
+      .M00_AXI_ARCACHE(ddr4_axi_arcache),
+      .M00_AXI_ARPROT (ddr4_axi_arprot),
+      .M00_AXI_ARQOS  (ddr4_axi_arqos),
+      .M00_AXI_ARVALID(ddr4_axi_arvalid),
+      .M00_AXI_ARREADY(ddr4_axi_arready),
+
+      //Read data
+      .M00_AXI_RID   (ddr4_axi_rid),
+      .M00_AXI_RDATA (ddr4_axi_rdata),
+      .M00_AXI_RRESP (ddr4_axi_rresp),
+      .M00_AXI_RLAST (ddr4_axi_rlast),
+      .M00_AXI_RVALID(ddr4_axi_rvalid),
+      .M00_AXI_RREADY(ddr4_axi_rready)
+   );
+
+   ddr4_0 ddr4_ctrl (
+      .sys_rst     (reset),
+      .c0_sys_clk_p(c0_sys_clk_clk_p),
+      .c0_sys_clk_n(c0_sys_clk_clk_n),
+
+      .dbg_clk(),
+      .dbg_bus(),
+
+      //USER LOGIC CLOCK AND RESET      
+      .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),  //to axi intercon
+      .addn_ui_clkout1        (clk),                      //to user logic 
+
+      //AXI INTERFACE (slave)
+      .c0_ddr4_ui_clk (c0_ddr4_ui_clk),  //to axi intercon general and master clocks
+      .c0_ddr4_aresetn(ddr4_axi_arstn),  //from interconnect axi master
+
+      //address write 
+      .c0_ddr4_s_axi_awid   (ddr4_axi_awid),
+      .c0_ddr4_s_axi_awaddr (ddr4_axi_awaddr),
+      .c0_ddr4_s_axi_awlen  (ddr4_axi_awlen),
+      .c0_ddr4_s_axi_awsize (ddr4_axi_awsize),
+      .c0_ddr4_s_axi_awburst(ddr4_axi_awburst),
+      .c0_ddr4_s_axi_awlock (ddr4_axi_awlock[0]),
+      .c0_ddr4_s_axi_awprot (ddr4_axi_awprot),
+      .c0_ddr4_s_axi_awcache(ddr4_axi_awcache),
+      .c0_ddr4_s_axi_awqos  (ddr4_axi_awqos),
+      .c0_ddr4_s_axi_awvalid(ddr4_axi_awvalid),
+      .c0_ddr4_s_axi_awready(ddr4_axi_awready),
+
+      //write  
+      .c0_ddr4_s_axi_wvalid(ddr4_axi_wvalid),
+      .c0_ddr4_s_axi_wready(ddr4_axi_wready),
+      .c0_ddr4_s_axi_wdata (ddr4_axi_wdata),
+      .c0_ddr4_s_axi_wstrb (ddr4_axi_wstrb),
+      .c0_ddr4_s_axi_wlast (ddr4_axi_wlast),
+
+      //write response
+      .c0_ddr4_s_axi_bready(ddr4_axi_bready),
+      .c0_ddr4_s_axi_bid   (ddr4_axi_bid),
+      .c0_ddr4_s_axi_bresp (ddr4_axi_bresp),
+      .c0_ddr4_s_axi_bvalid(ddr4_axi_bvalid),
+
+      //address read
+      .c0_ddr4_s_axi_arid   (ddr4_axi_arid),
+      .c0_ddr4_s_axi_araddr (ddr4_axi_araddr),
+      .c0_ddr4_s_axi_arlen  (ddr4_axi_arlen),
+      .c0_ddr4_s_axi_arsize (ddr4_axi_arsize),
+      .c0_ddr4_s_axi_arburst(ddr4_axi_arburst),
+      .c0_ddr4_s_axi_arlock (ddr4_axi_arlock[0]),
+      .c0_ddr4_s_axi_arcache(ddr4_axi_arcache),
+      .c0_ddr4_s_axi_arprot (ddr4_axi_arprot),
+      .c0_ddr4_s_axi_arqos  (ddr4_axi_arqos),
+      .c0_ddr4_s_axi_arvalid(ddr4_axi_arvalid),
+      .c0_ddr4_s_axi_arready(ddr4_axi_arready),
+
+      //read   
+      .c0_ddr4_s_axi_rready(ddr4_axi_rready),
+      .c0_ddr4_s_axi_rid   (ddr4_axi_rid),
+      .c0_ddr4_s_axi_rdata (ddr4_axi_rdata),
+      .c0_ddr4_s_axi_rresp (ddr4_axi_rresp),
+      .c0_ddr4_s_axi_rlast (ddr4_axi_rlast),
+      .c0_ddr4_s_axi_rvalid(ddr4_axi_rvalid),
+
+      //DDR4 INTERFACE (master of external DDR4 module)
+      .c0_ddr4_act_n         (c0_ddr4_act_n),
+      .c0_ddr4_adr           (c0_ddr4_adr),
+      .c0_ddr4_ba            (c0_ddr4_ba),
+      .c0_ddr4_bg            (c0_ddr4_bg),
+      .c0_ddr4_cke           (c0_ddr4_cke),
+      .c0_ddr4_odt           (c0_ddr4_odt),
+      .c0_ddr4_cs_n          (c0_ddr4_cs_n),
+      .c0_ddr4_ck_t          (c0_ddr4_ck_t),
+      .c0_ddr4_ck_c          (c0_ddr4_ck_c),
+      .c0_ddr4_reset_n       (c0_ddr4_reset_n),
+      .c0_ddr4_dm_dbi_n      (c0_ddr4_dm_dbi_n),
+      .c0_ddr4_dq            (c0_ddr4_dq),
+      .c0_ddr4_dqs_c         (c0_ddr4_dqs_c),
+      .c0_ddr4_dqs_t         (c0_ddr4_dqs_t),
+      .c0_init_calib_complete(calib_done)
+   );
+
+
+`else
+   //if DDR not used use PLL to generate system clock
+   clock_wizard #(
+      .OUTPUT_PER(10),
+      .INPUT_PER (4)
+   ) clk_250_to_100_MHz (
+      .clk_in1_p(c0_sys_clk_clk_p),
+      .clk_in1_n(c0_sys_clk_clk_n),
+      .clk_out1 (clk)
+   );
+
+   wire start;
+   iob_reset_sync start_sync (
+      .clk_i (clk),
+      .arst_i(reset),
+      .arst_o(start)
+   );
+
+   //create reset pulse as reset is never activated manually
+   //also, during bitstream loading, the reset pin is not pulled high
+   iob_pulse_gen #(
+      .START   (5),
+      .DURATION(10)
+   ) reset_pulse (
+      .clk_i  (clk),
+      .arst_i (reset),
+      .cke_i  (1'b1),
+      .start_i(start),
+      .pulse_o(arst)
+   );
+`endif
+
+endmodule
diff --git a/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc b/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc
new file mode 100644
index 00000000..a08e26d7
--- /dev/null
+++ b/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_opencryptolinux_fpga_wrapper_dev.sdc
@@ -0,0 +1,156 @@
+## System Clock 
+set clk_period 4.0
+set clk_port c0_sys_clk_clk_p
+
+# LVDS Programmable Clock Generator (CDCM61002)
+#set_property  PACKAGE_PIN M5   [get_ports LVDS_CLK0_N]
+#set_property  PACKAGE_PIN M6   [get_ports LVDS_CLK0_P]
+#set_property  PACKAGE_PIN P5   [get_ports LVDS_CLK1_N]
+#set_property  PACKAGE_PIN P6   [get_ports LVDS_CLK1_P]
+
+#set_property  IOSTANDARD LVDS [get_ports LVDS_CLK0_N]
+#set_property  IOSTANDARD LVDS [get_ports LVDS_CLK0_P]
+#set_property  IOSTANDARD LVDS [get_ports LVDS_CLK1_N]
+#set_property  IOSTANDARD LVDS [get_ports LVDS_CLK1_P]
+
+##DDR clocks
+set_property PACKAGE_PIN H22 [get_ports {c0_sys_clk_clk_p}]
+set_property PACKAGE_PIN H23 [get_ports {c0_sys_clk_clk_n}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {c0_sys_clk_clk_p}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {c0_sys_clk_clk_n}]
+
+set_property CONFIG_VOLTAGE 2.5 [current_design]
+
+#derive_pll_clocks
+#derive_clock_uncertainty
+
+set_property CFGBVS VCCO [current_design]
+
+## USB-UART Interface
+set_property PACKAGE_PIN D20 [get_ports {txd_o}]
+set_property IOSTANDARD LVCMOS18 [get_ports {txd_o}]
+set_property PACKAGE_PIN C19 [get_ports {rxd_i}]
+set_property IOSTANDARD LVCMOS18 [get_ports {rxd_i}]
+
+###### User LEDs
+#set_property PACKAGE_PIN D16 [get_ports {led[6]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[6]}]
+
+#set_property PACKAGE_PIN G16 [get_ports {led[5]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[5]}]
+
+#set_property PACKAGE_PIN H16 [get_ports {led[4]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[4]}]
+
+#set_property PACKAGE_PIN E18 [get_ports {led[3]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[3]}]
+
+#set_property PACKAGE_PIN E17 [get_ports {led[2]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[2]}]
+
+#set_property PACKAGE_PIN E16 [get_ports {led[1]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[1]}]
+
+#set_property PACKAGE_PIN H18 [get_ports {led[0]}]
+#set_property IOSTANDARD LVCMOS18 [get_ports {led[0]}]
+
+set_property PACKAGE_PIN H17 [get_ports {trap}]
+set_property IOSTANDARD LVCMOS18 [get_ports {trap}]
+
+####### User PUSH Switches
+#set_property PACKAGE_PIN N24 [get_ports {reset}]
+#set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
+set_property PACKAGE_PIN K20 [get_ports {reset}]
+set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
+
+#set_property PACKAGE_PIN K18 [get_ports {gpio_push_sw_tri_i[0]}]
+#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_push_sw_tri_i[0]}]
+
+#set_property PACKAGE_PIN L18 [get_ports {gpio_push_sw_tri_i[1]}]
+#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_push_sw_tri_i[1]}]
+
+#set_property PACKAGE_PIN K21 [get_ports {gpio_push_sw_tri_i[2]}]
+#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_push_sw_tri_i[2]}]
+
+#set_property PACKAGE_PIN K20 [get_ports {gpio_push_sw_tri_i[3]}]
+#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_push_sw_tri_i[3]}]
+
+####### Ethernet 100 MHz
+create_clock -name enet_clk -period 40 [get_ports {ENET_RX_CLK}]
+
+## Ethernet #1 Interface (J1)
+set_property PACKAGE_PIN D9 [get_ports ENET_RESETN]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RESETN]
+
+set_property PACKAGE_PIN A10 [get_ports ENET_RX_D0]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RX_D0]
+
+set_property PACKAGE_PIN B10 [get_ports ENET_RX_D1]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RX_D1]
+
+set_property PACKAGE_PIN B11 [get_ports ENET_RX_D2]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RX_D2]
+
+set_property PACKAGE_PIN C11 [get_ports ENET_RX_D3]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RX_D3]
+
+set_property PACKAGE_PIN D11 [get_ports ENET_RX_DV]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RX_DV]
+
+set_property PACKAGE_PIN E11 [get_ports ENET_RX_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_RX_CLK]
+
+set_property PACKAGE_PIN H8 [get_ports ENET_TX_D0]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_TX_D0]
+
+set_property PACKAGE_PIN H9 [get_ports ENET_TX_D1]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_TX_D1]
+
+set_property PACKAGE_PIN J9 [get_ports ENET_TX_D2]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_TX_D2]
+
+set_property PACKAGE_PIN J10 [get_ports ENET_TX_D3]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_TX_D3]
+
+set_property PACKAGE_PIN G9 [get_ports ENET_TX_EN]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_TX_EN]
+
+set_property PACKAGE_PIN G10 [get_ports ENET_GTX_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports ENET_GTX_CLK]
+
+set_property IOB TRUE [get_ports ENET_TX_D0]
+set_property IOB TRUE [get_ports ENET_TX_D1]
+set_property IOB TRUE [get_ports ENET_TX_D2]
+set_property IOB TRUE [get_ports ENET_TX_D3]
+set_property IOB TRUE [get_ports ENET_TX_EN]
+
+
+#
+# User Code/Data QSPI Interface
+#
+
+# CS
+set_property PACKAGE_PIN D19 [get_ports spi_SS_o]
+set_property IOSTANDARD LVCMOS18 [get_ports spi_SS_o]
+# CLK
+set_property PACKAGE_PIN F10 [get_ports spi_SCLK_o]
+set_property IOSTANDARD LVCMOS18 [get_ports spi_SCLK_o]
+# DQ0
+set_property PACKAGE_PIN G11 [get_ports spi_MOSI_io]
+set_property IOSTANDARD LVCMOS18 [get_ports spi_MOSI_io]
+# DQ1
+set_property PACKAGE_PIN H11 [get_ports spi_MISO_io]
+set_property IOSTANDARD LVCMOS18 [get_ports spi_MISO_io]
+# DQ2
+set_property PACKAGE_PIN J11 [get_ports spi_WP_N_io]
+set_property IOSTANDARD LVCMOS18 [get_ports spi_WP_N_io]
+# DQ3
+set_property PACKAGE_PIN H12 [get_ports spi_HOLD_N_io]
+set_property IOSTANDARD LVCMOS18 [get_ports spi_HOLD_N_io]
+
+set_property IOB TRUE [get_ports spi_SS_o]
+set_property IOB TRUE [get_ports spi_SCLK_o]
+set_property IOB TRUE [get_cells iob_soc_opencryptolinux0/SPI0/fl_spi0/dq_out_r_reg[0]]
+set_property IOB TRUE [get_cells iob_soc_opencryptolinux0/SPI0/fl_spi0/dq_out_r_reg[1]]
+set_property IOB TRUE [get_cells iob_soc_opencryptolinux0/SPI0/fl_spi0/dq_out_r_reg[2]]
+set_property IOB TRUE [get_cells iob_soc_opencryptolinux0/SPI0/fl_spi0/dq_out_r_reg[3]]
diff --git a/hardware/fpga/vivado/iob_soc_opencryptolinux_fpga_wrapper_tool.sdc b/hardware/fpga/vivado/iob_soc_opencryptolinux_fpga_wrapper_tool.sdc
new file mode 100644
index 00000000..9362913a
--- /dev/null
+++ b/hardware/fpga/vivado/iob_soc_opencryptolinux_fpga_wrapper_tool.sdc
@@ -0,0 +1,9 @@
+################################################################################
+## Synchronizers
+################################################################################
+set_property ASYNC_REG TRUE [get_cells -hier {*iob_r_data_o*[*]}]
+
+################################################################################
+## Clock groups
+#################################################################################
+set_clock_groups -asynchronous -group {c0_sys_clk_clk_p} -group {enet_clk}
diff --git a/iob_soc_opencryptolinux.py b/iob_soc_opencryptolinux.py
index 37cd6658..05fba2c2 100755
--- a/iob_soc_opencryptolinux.py
+++ b/iob_soc_opencryptolinux.py
@@ -1,6 +1,5 @@
 #!/usr/bin/env python3
 import os
-import sys
 import shutil
 import math
 
@@ -129,7 +128,6 @@ def _create_submodules_list(cls, extra_submodules=[]):
                 iob_reset_sync,
                 iob_ram_sp,
                 cls.versatType,
-                # iob_spi_master,
                 iob_eth,
                 iob_spi_master,
                 (N25Qxxx, {"purpose": "simulation"}),
diff --git a/software/src/iob_soc_opencryptolinux_boot.c b/software/src/iob_soc_opencryptolinux_boot.c
index 0a8193f2..60b84030 100644
--- a/software/src/iob_soc_opencryptolinux_boot.c
+++ b/software/src/iob_soc_opencryptolinux_boot.c
@@ -1,11 +1,14 @@
 #include "bsp.h"
 #include "clint.h"
+#include "iob-eth.h"
+#include "iob-spi.h"
+#include "iob-spidefs.h"
+#include "iob-spiplatform.h"
 #include "iob-uart16550.h"
 #include "iob_soc_opencryptolinux_conf.h"
-#include "iob_soc_opencryptolinux_system.h"
 #include "iob_soc_opencryptolinux_periphs.h"
+#include "iob_soc_opencryptolinux_system.h"
 #include "printf.h"
-#include "iob-eth.h"
 #include <string.h>
 
 #define PROGNAME "IOb-Bootloader"
@@ -13,34 +16,52 @@
 #define DC1 17 // Device Control 1 (used to indicate end of bootloader)
 #define EXT_MEM 0x80000000
 
+#define NSAMPLES 16
+
+// Set SPI Support:
+// Simulation: Enabled, except for Verilator
+// FPGA: Disabled, except for AMD
+#ifdef SIMULATION
+#   ifdef VERILATOR
+        // no SPI support
+#   else
+#       define SPI_SUPPORT
+#   endif // ifndef VERILATOR
+#else // ifdef SIMULATION: FPGA case
+#   ifdef AMD
+#       define SPI_SUPPORT
+#   endif // ifdef AMD
+        // no SPI support
+#endif // ifdef SIMULATION
 
 // Ethernet utility functions
-//NOTE: These functions are not compatible with malloc() and free().
+// NOTE: These functions are not compatible with malloc() and free().
 //      These are specifically made for use with the current iob-eth.c drivers.
 //      (These assume that there is only one block allocated at a time)
-static void* mem_alloc(size_t size){
-  return (void *)(EXT_MEM | (1<<IOB_SOC_OPENCRYPTOLINUX_MEM_ADDR_W)) - size;
+static void *mem_alloc(size_t size) {
+  return (void *)(EXT_MEM | (1 << IOB_SOC_OPENCRYPTOLINUX_MEM_ADDR_W)) - size;
 }
-static void mem_free(void* ptr){}
+static void mem_free(void *ptr) {}
 
-void clear_cache(){
+void clear_cache() {
   // Delay to ensure all data is written to memory
-  for ( unsigned int i = 0; i < 10; i++)asm volatile("nop");
+  for (unsigned int i = 0; i < 10; i++)
+    asm volatile("nop");
   // Flush VexRiscv CPU internal cache
   asm volatile(".word 0x500F" ::: "memory");
 }
 
-
 // Send signal by uart to receive file by ethernet
 uint32_t uart_recvfile_ethernet(char *file_name) {
   uart16550_puts(UART_PROGNAME);
-  uart16550_puts (": requesting to receive file by ethernet\n");
+  uart16550_puts(": requesting to receive file by ethernet\n");
 
-  //send file receive by ethernet request
-  uart16550_putc (0x13);
+  // send file receive by ethernet request
+  uart16550_putc(0x13);
 
-  //send file name (including end of string)
-  uart16550_puts(file_name); uart16550_putc(0);
+  // send file name (including end of string)
+  uart16550_puts(file_name);
+  uart16550_putc(0);
 
   // receive file size
   uint32_t file_size = uart16550_getc();
@@ -83,16 +104,90 @@ int main() {
     uart16550_puts(": Waiting for Console ACK.\n");
   }
 
+
 #ifndef IOB_SOC_OPENCRYPTOLINUX_INIT_MEM
   // Init ethernet and printf (for ethernet)
   printf_init(&uart16550_putc);
+
+#ifdef SPI_SUPPORT
+  // init spit flash controller
+  spiflash_init(SPI0_BASE);
+  printf("\nResetting flash registers...\n");
+  spiflash_resetmem();
+
+  printf("Testing program flash\n");
+  char prog_data[NSAMPLES] = {0};
+  char *char_data = NULL;
+  unsigned int read_data[NSAMPLES] = {0};
+  unsigned int flash_addr = 0x0;
+  int sample = 0;
+  int flash_failed = 0;
+
+  // set samples to write
+  for (sample = 0; sample < NSAMPLES; sample++) {
+    prog_data[sample] = sample;
+  }
+
+  // Flash data before erase
+  printf("\nFlash data before erase:\n");
+  for (sample = 0; sample < NSAMPLES; sample = sample + 4) {
+    read_data[sample >> 2] = spiflash_readmem(flash_addr + sample);
+  }
+  char_data = (char *)read_data;
+  for (sample = 0; sample < NSAMPLES; sample++) {
+    printf("\tflash[%x] = %02x\n", flash_addr + sample, char_data[sample]);
+  }
+
+  spiflash_erase_address_range(flash_addr, NSAMPLES);
+
+  // Flash data after erase
+  printf("\nFlash data after erase:\n");
+  for (sample = 0; sample < NSAMPLES; sample = sample + 4) {
+    read_data[sample >> 2] = spiflash_readmem(flash_addr + sample);
+  }
+  char_data = (char *)read_data;
+  for (sample = 0; sample < NSAMPLES; sample++) {
+    printf("\tflash[%x] = %02x\n", flash_addr + sample, char_data[sample]);
+    if (char_data[sample] != 0xFF){
+        printf("Error: flash[%x] = %02x != 0xFF\n", flash_addr + sample, char_data[sample]);
+        flash_failed = 1;
+    }   
+  }
+
+  spiflash_memProgram(prog_data, NSAMPLES, 0x0);
+
+  printf("\nFlash data after program:\n");
+  for (sample = 0; sample < NSAMPLES; sample = sample + 4) {
+    read_data[sample >> 2] = spiflash_readmem(0x0 + sample);
+  }
+  char_data = (char *)read_data;
+  for (sample = 0; sample < NSAMPLES; sample++) {
+    if (prog_data[sample] != char_data[sample]) {
+      printf("Error: expected[%x] = %02x != flash[%x] = %02x\n", flash_addr + sample,
+             prog_data[sample], flash_addr + sample, char_data[sample]);
+      flash_failed = 1;
+    } else {
+      printf("Valid: expected[%x] = %02x == flash[%x] = %02x\n", flash_addr + sample,
+             prog_data[sample], flash_addr + sample, char_data[sample]);
+    }
+  }
+
+  if (flash_failed) {
+    printf("ERROR: Flash test failed!\n");
+  } else {
+    printf("SUCCESS: Flash test passed!\n");
+  }
+#endif // ifdef SPI_SUPPORT
+
   eth_init(ETH0_BASE, &clear_cache);
-  // Use custom memory alloc/free functions to ensure it allocates in external memory
+  // Use custom memory alloc/free functions to ensure it allocates in external
+  // memory
   eth_init_mem_alloc(&mem_alloc, &mem_free);
   // Wait for PHY reset to finish
   eth_wait_phy_rst();
 
-  file_size = uart16550_recvfile("../iob_soc_opencryptolinux_mem.config", prog_start_addr);
+  file_size = uart16550_recvfile("../iob_soc_opencryptolinux_mem.config",
+                                 prog_start_addr);
   // compute_mem_load_txt
   int state = 0;
   int file_name_count = 0;
@@ -104,7 +199,7 @@ int main() {
   int i = 0;
   for (i = 0; i < file_size; i++) {
     hexChar = *(prog_start_addr + i);
-    //uart16550_puts(&hexChar); /* Used for debugging. */
+    // uart16550_puts(&hexChar); /* Used for debugging. */
     if (state == 0) {
       if (hexChar == ' ') {
         file_name_array[file_count][file_name_count] = '\0';
@@ -130,8 +225,8 @@ int main() {
           uart16550_puts(PROGNAME);
           uart16550_puts(": invalid hexadecimal character.\n");
         }
-        file_address_array[file_count-1] =
-            file_address_array[file_count-1] * 16 + hexDecimal;
+        file_address_array[file_count - 1] =
+            file_address_array[file_count - 1] * 16 + hexDecimal;
       }
     }
   }
@@ -141,7 +236,7 @@ int main() {
     // Receive data from console via Ethernet
 #ifndef SIMULATION
     file_size = uart_recvfile_ethernet(file_name_array[i]);
-    eth_rcv_file(prog_start_addr,file_size);
+    eth_rcv_file(prog_start_addr, file_size);
 #else
     file_size = uart16550_recvfile(file_name_array[i], prog_start_addr);
 #endif
@@ -149,21 +244,21 @@ int main() {
 
   // Check if running Linux
   for (i = 0; i < file_count; i++) {
-    if (!strcmp(file_name_array[i], "rootfs.cpio.gz")){
+    if (!strcmp(file_name_array[i], "rootfs.cpio.gz")) {
 #ifdef SIMULATION
       // Running Linux: setup required dependencies
       uart16550_sendfile("test.log", 12, "Test passed!");
       uart16550_putc((char)DC1);
 #endif
-      run_linux=1;
+      run_linux = 1;
       break;
     }
   }
 #else // INIT_MEM = 1
 #ifdef IOB_SOC_OPENCRYPTOLINUX_RUN_LINUX
-    // Running Linux: setup required dependencies
-    uart16550_sendfile("test.log", 12, "Test passed!");
-    uart16550_putc((char)DC1);
+  // Running Linux: setup required dependencies
+  uart16550_sendfile("test.log", 12, "Test passed!");
+  uart16550_putc((char)DC1);
 #endif
 #endif
 
diff --git a/software/src/iob_soc_opencryptolinux_firmware.c b/software/src/iob_soc_opencryptolinux_firmware.c
index 1a92b272..aeb545b5 100644
--- a/software/src/iob_soc_opencryptolinux_firmware.c
+++ b/software/src/iob_soc_opencryptolinux_firmware.c
@@ -125,9 +125,7 @@ int main() {
     uart16550_putc(buffer[i]);
 #endif
 
-//#ifndef SIMULATION
   InitializeCryptoSide(VERSAT0_BASE);
-//#endif
 
   printf("\n\n\nHello world!\n\n\n");
 
diff --git a/software/sw_build.mk b/software/sw_build.mk
index 71ded418..ed188480 100644
--- a/software/sw_build.mk
+++ b/software/sw_build.mk
@@ -107,6 +107,7 @@ IOB_SOC_OPENCRYPTOLINUX_BOOT_SRC+=src/iob_soc_opencryptolinux_boot.c
 IOB_SOC_OPENCRYPTOLINUX_BOOT_SRC+=$(filter-out %_emul.c, $(wildcard src/iob*uart*.c))
 IOB_SOC_OPENCRYPTOLINUX_BOOT_SRC+=$(filter-out %_emul.c, $(wildcard src/iob*cache*.c))
 IOB_SOC_OPENCRYPTOLINUX_BOOT_SRC+=$(filter-out %_emul.c, $(wildcard src/iob*eth*.c))
+IOB_SOC_OPENCRYPTOLINUX_BOOT_SRC+=$(filter-out %_emul.c, $(wildcard src/iob*spi*.c))
 IOB_SOC_OPENCRYPTOLINUX_BOOT_SRC+=src/printf.c
 
 build_iob_soc_opencryptolinux_software: iob_soc_opencryptolinux_firmware iob_soc_opencryptolinux_boot
diff --git a/submodules/SPI b/submodules/SPI
index f9fcc139..4a7d3677 160000
--- a/submodules/SPI
+++ b/submodules/SPI
@@ -1 +1 @@
-Subproject commit f9fcc1390cc4e1bb774869c1a3ae54148154335f
+Subproject commit 4a7d3677541ab0c400200e40cc6611f33ddc39f0