From 234dce72204c95de7a22005a6d05a854a01d8286 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 17 Sep 2024 17:21:44 +0100 Subject: [PATCH 01/12] feat(bus_width_converter): add bus width converter module - This module will be used to connect two buses with different widths with py2. Otherwise we would need to connect those buses signals individually using snippets (to trim their width). - Fix axil2iob interface widths. - Format verilog code of iob_fifo_sync.v --- lib/hardware/buses/axil2iob/axil2iob.py | 4 + .../bus_width_converter.py | 163 ++++++++++++++++++ .../hardware/src/iob_fifo_sync.v | 136 +++++++-------- 3 files changed, 235 insertions(+), 68 deletions(-) create mode 100644 lib/hardware/buses/bus_width_converter/bus_width_converter.py diff --git a/lib/hardware/buses/axil2iob/axil2iob.py b/lib/hardware/buses/axil2iob/axil2iob.py index 1a05a9178..34cd60de2 100644 --- a/lib/hardware/buses/axil2iob/axil2iob.py +++ b/lib/hardware/buses/axil2iob/axil2iob.py @@ -18,6 +18,8 @@ def setup(py_params_dict): "interface": { "type": "axil", "subtype": "slave", + "ADDR_W": "AXIL_ADDR_W", + "DATA_W": "AXIL_DATA_W", }, "descr": "AXIL interface", }, @@ -26,6 +28,8 @@ def setup(py_params_dict): "interface": { "type": "iob", "subtype": "master", + "ADDR_W": "ADDR_W", + "DATA_W": "DATA_W", }, "descr": "CPU native interface", }, diff --git a/lib/hardware/buses/bus_width_converter/bus_width_converter.py b/lib/hardware/buses/bus_width_converter/bus_width_converter.py new file mode 100644 index 000000000..3bd6b0aca --- /dev/null +++ b/lib/hardware/buses/bus_width_converter/bus_width_converter.py @@ -0,0 +1,163 @@ +interfaces = { + "iob": [ + ("valid", "output", 1), + ("addr", "output", "ADDR_W"), + ("wdata", "output", "DATA_W"), + ("wstrb", "output", "DATA_W / 8"), + ("rvalid", "input", 1), + ("rdata", "input", "DATA_W"), + ("ready", "input", 1), + ], + "axil": [ + ("awaddr", "output", "ADDR_W"), + ("awprot", "output", "PROT_W"), + ("awvalid", "output", 1), + ("awready", "input", 1), + ("wdata", "output", "DATA_W"), + ("wstrb", "output", "DATA_W / 8"), + ("wvalid", "output", 1), + ("wready", "input", 1), + ("bresp", "input", "RESP_W"), + ("bvalid", "input", 1), + ("bready", "output", 1), + ("araddr", "output", "ADDR_W"), + ("arprot", "output", "PROT_W"), + ("arvalid", "output", 1), + ("arready", "input", 1), + ("rdata", "input", "DATA_W"), + ("rresp", "input", "RESP_W"), + ("rvalid", "input", 1), + ("rready", "output", 1), + ], + "axi": [ + ("awaddr", "output", "ADDR_W"), + ("awprot", "output", "PROT_W"), + ("awvalid", "output", 1), + ("awready", "input", 1), + ("wdata", "output", "DATA_W"), + ("wstrb", "output", "DATA_W / 8"), + ("wvalid", "output", 1), + ("wready", "input", 1), + ("bresp", "input", "RESP_W"), + ("bvalid", "input", 1), + ("bready", "output", 1), + ("araddr", "output", "ADDR_W"), + ("arprot", "output", "PROT_W"), + ("arvalid", "output", 1), + ("arready", "input", 1), + ("rdata", "input", "DATA_W"), + ("rresp", "input", "RESP_W"), + ("rvalid", "input", 1), + ("rready", "output", 1), + ("awid", "output", "ID_W"), + ("awlen", "output", "LEN_W"), + ("awsize", "output", "SIZE_W"), + ("awburst", "output", "BURST_W"), + ("awlock", "output", "LOCK_W"), + ("awcache", "output", "CACHE_W"), + ("awqos", "output", "QOS_W"), + ("wlast", "output", 1), + ("bid", "input", "ID_W"), + ("arid", "output", "ID_W"), + ("arlen", "output", "LEN_W"), + ("arsize", "output", "SIZE_W"), + ("arburst", "output", "BURST_W"), + ("arlock", "output", "LOCK_W"), + ("arcache", "output", "CACHE_W"), + ("arqos", "output", "QOS_W"), + ("rid", "input", "ID_W"), + ("rlast", "input", 1), + ], +} + + +def setup(py_params_dict): + """Core purely made of wires to convert between two buses with different widths (to suppress verilog warnings). + Use verilog parameters to define widths of each bus. + :param str interface: Type of interface of buses. + """ + INTERFACE = py_params_dict["interface"] if "interface" in py_params_dict else "axil" + + wire_assigns = "" + parameter_names = [] + verilog_parameters = [] + master_interface_parameters = {} + slave_interface_parameters = {} + for signal in interfaces[INTERFACE]: + name = signal[0] + direction = signal[1] + width = signal[2] + + if type(width) is int: + bit_select = "" + elif direction == "output": + bit_select = f"[MASTER_{width}-1:0]" + else: + bit_select = f"[SLAVE_{width}-1:0]" + + # Connect both interfaces + wire_assigns += f""" + assign {INTERFACE}_{name}_o = {INTERFACE}_{name}_i{bit_select}; +""" + + # Only create verilog parameters for strings that represent widths + if type(width) is int or not width.endswith("_W"): + continue + + # Don't create a duplicate parameters + if width in parameter_names: + continue + parameter_names.append(width) + + # Set verilog parameters for each interface + verilog_parameters += [ + { + "name": f"SLAVE_{width}", + "type": "P", + "val": "0", + "min": "1", + "max": "32", + "descr": f"Slave {width[:-2]} bus width", + }, + { + "name": f"MASTER_{width}", + "type": "P", + "val": "0", + "min": "1", + "max": "32", + "descr": f"Master {width[:-2]} bus width", + }, + ] + # Set parameters for if_gen generation of each interface + slave_interface_parameters[width] = f"SLAVE_{width}" + master_interface_parameters[width] = f"MASTER_{width}" + + attributes_dict = { + "original_name": "bus_width_converter", + "name": f"{INTERFACE}_bus_width_converter", + "version": "0.1", + "confs": verilog_parameters, + "ports": [ + { + "name": "slave", + "descr": "Slave interface (connects to master)", + "interface": { + "type": INTERFACE, + "subtype": "slave", + **slave_interface_parameters, + }, + }, + { + "name": "master", + "descr": "Master interface (connects to slave)", + "interface": { + "type": INTERFACE, + "subtype": "master", + **master_interface_parameters, + }, + }, + ], + "snippets": [{"verilog_code": wire_assigns}], + } + + return attributes_dict diff --git a/lib/hardware/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v b/lib/hardware/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v index d8183808d..35e813cce 100644 --- a/lib/hardware/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v +++ b/lib/hardware/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v @@ -1,125 +1,125 @@ `timescale 1ns / 1ps module iob_fifo_sync #( - parameter W_DATA_W = 21, - R_DATA_W = 21, - ADDR_W = 21, //higher ADDR_W lower DATA_W - //determine W_ADDR_W and R_ADDR_W - MAXDATA_W = iob_max(W_DATA_W, R_DATA_W), - MINDATA_W = iob_min(W_DATA_W, R_DATA_W), - R = MAXDATA_W / MINDATA_W, - MINADDR_W = ADDR_W - $clog2(R), //lower ADDR_W (higher DATA_W) - W_ADDR_W = (W_DATA_W == MAXDATA_W) ? MINADDR_W : ADDR_W, - R_ADDR_W = (R_DATA_W == MAXDATA_W) ? MINADDR_W : ADDR_W + parameter W_DATA_W = 21, + R_DATA_W = 21, + ADDR_W = 21, //higher ADDR_W lower DATA_W + //determine W_ADDR_W and R_ADDR_W + MAXDATA_W = iob_max(W_DATA_W, R_DATA_W), + MINDATA_W = iob_min(W_DATA_W, R_DATA_W), + R = MAXDATA_W / MINDATA_W, + MINADDR_W = ADDR_W - $clog2(R), //lower ADDR_W (higher DATA_W) + W_ADDR_W = (W_DATA_W == MAXDATA_W) ? MINADDR_W : ADDR_W, + R_ADDR_W = (R_DATA_W == MAXDATA_W) ? MINADDR_W : ADDR_W ) ( - `include "iob_fifo_sync_io.vs" + `include "iob_fifo_sync_io.vs" ); - `include "iob_functions.vs" + `include "iob_functions.vs" - localparam ADDR_W_DIFF = $clog2(R); - localparam [ADDR_W:0] FIFO_SIZE = {1'b1, {ADDR_W{1'b0}}}; //in bytes + localparam ADDR_W_DIFF = $clog2(R); + localparam [ADDR_W:0] FIFO_SIZE = {1'b1, {ADDR_W{1'b0}}}; //in bytes - //effective write enable - wire w_en_int = (w_en_i & (~w_full_o)); + //effective write enable + wire w_en_int = (w_en_i & (~w_full_o)); - //write address - wire [W_ADDR_W-1:0] w_addr; - iob_counter #( + //write address + wire [W_ADDR_W-1:0] w_addr; + iob_counter #( .DATA_W (W_ADDR_W), .RST_VAL({W_ADDR_W{1'd0}}) - ) w_addr_cnt0 ( + ) w_addr_cnt0 ( `include "iob_fifo_sync_clk_en_rst_s_s_portmap.vs" .rst_i (rst_i), .en_i (w_en_int), .data_o(w_addr) - ); + ); - //effective read enable - wire r_en_int = (r_en_i & (~r_empty_o)); + //effective read enable + wire r_en_int = (r_en_i & (~r_empty_o)); - //read address - wire [R_ADDR_W-1:0] r_addr; - iob_counter #( + //read address + wire [R_ADDR_W-1:0] r_addr; + iob_counter #( .DATA_W (R_ADDR_W), .RST_VAL({R_ADDR_W{1'd0}}) - ) r_addr_cnt0 ( + ) r_addr_cnt0 ( `include "iob_fifo_sync_clk_en_rst_s_s_portmap.vs" .rst_i (rst_i), .en_i (r_en_int), .data_o(r_addr) - ); + ); - //assign according to assymetry type - localparam [ADDR_W-1:0] W_INCR = (W_DATA_W > R_DATA_W) ? + //assign according to assymetry type + localparam [ADDR_W-1:0] W_INCR = (W_DATA_W > R_DATA_W) ? {{ADDR_W-1{1'd0}},{1'd1}} << ADDR_W_DIFF : {{ADDR_W-1{1'd0}},{1'd1}}; - localparam [ADDR_W-1:0] R_INCR = (R_DATA_W > W_DATA_W) ? + localparam [ADDR_W-1:0] R_INCR = (R_DATA_W > W_DATA_W) ? {{ADDR_W-1{1'd0}},{1'd1}} << ADDR_W_DIFF : {{ADDR_W-1{1'd0}},{1'd1}}; - //FIFO level - reg [ADDR_W:0] level_nxt; - wire [ADDR_W:0] level_int; - iob_reg_r #( + //FIFO level + reg [ADDR_W:0] level_nxt; + wire [ADDR_W:0] level_int; + iob_reg_r #( .DATA_W (ADDR_W + 1), .RST_VAL({(ADDR_W + 1) {1'd0}}) - ) level_reg0 ( + ) level_reg0 ( `include "iob_fifo_sync_clk_en_rst_s_s_portmap.vs" .rst_i(rst_i), .data_i(level_nxt), .data_o(level_int) - ); - - reg [(ADDR_W+1)-1:0] level_incr; - always @* begin - level_incr = level_int + W_INCR; - level_nxt = level_int; - if (w_en_int && (!r_en_int)) //write only - level_nxt = level_incr; - else if (w_en_int && r_en_int) //write and read - level_nxt = level_incr - R_INCR; - else if (r_en_int) //read only - level_nxt = level_int - R_INCR; - end - - assign level_o = level_int; - - //FIFO empty - wire r_empty_nxt; - assign r_empty_nxt = level_nxt < {1'b0, R_INCR}; - iob_reg_r #( + ); + + reg [(ADDR_W+1)-1:0] level_incr; + always @* begin + level_incr = level_int + W_INCR; + level_nxt = level_int; + if (w_en_int && (!r_en_int)) //write only + level_nxt = level_incr; + else if (w_en_int && r_en_int) //write and read + level_nxt = level_incr - R_INCR; + else if (r_en_int) //read only + level_nxt = level_int - R_INCR; + end + + assign level_o = level_int; + + //FIFO empty + wire r_empty_nxt; + assign r_empty_nxt = level_nxt < {1'b0, R_INCR}; + iob_reg_r #( .DATA_W (1), .RST_VAL(1'd1) - ) r_empty_reg0 ( + ) r_empty_reg0 ( `include "iob_fifo_sync_clk_en_rst_s_s_portmap.vs" .rst_i (rst_i), .data_i(r_empty_nxt), .data_o(r_empty_o) - ); + ); - //FIFO full - wire w_full_nxt; - assign w_full_nxt = level_nxt > (FIFO_SIZE - W_INCR); - iob_reg_r #( + //FIFO full + wire w_full_nxt; + assign w_full_nxt = level_nxt > (FIFO_SIZE - W_INCR); + iob_reg_r #( .DATA_W (1), .RST_VAL(1'd0) - ) w_full_reg0 ( + ) w_full_reg0 ( `include "iob_fifo_sync_clk_en_rst_s_s_portmap.vs" .rst_i (rst_i), .data_i(w_full_nxt), .data_o(w_full_o) - ); + ); - assign ext_mem_clk_o = clk_i; + assign ext_mem_clk_o = clk_i; - iob_asym_converter #( + iob_asym_converter #( .W_DATA_W(W_DATA_W), .R_DATA_W(R_DATA_W), .ADDR_W (ADDR_W) - ) asym_converter ( + ) asym_converter ( .ext_mem_w_en_o (ext_mem_w_en_o), .ext_mem_w_addr_o(ext_mem_w_addr_o), .ext_mem_w_data_o(ext_mem_w_data_o), @@ -134,6 +134,6 @@ module iob_fifo_sync #( .r_addr_i (r_addr), .r_en_i (r_en_int), .r_data_o (r_data_o) - ); + ); endmodule From 51e009cbf29484e69171d89380a24dadd785ec57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 17 Sep 2024 20:36:02 +0100 Subject: [PATCH 02/12] feat(is_peripheral): Add support for 'is_peripheral' block attribute New 'is_peripheral' block attribute in iob_soc blocks list is used to identify peripheral blocks. These blocks will have their cbus connection added automatically to the system's pbus_split. Other ports should be connected manually. --- iob_soc.py | 123 ++++++++++----------------------------- scripts/iob_soc_utils.py | 91 ++++++++++++++++++++++++++++- 2 files changed, 120 insertions(+), 94 deletions(-) diff --git a/iob_soc.py b/iob_soc.py index 665af6e81..6a73372fc 100755 --- a/iob_soc.py +++ b/iob_soc.py @@ -22,35 +22,6 @@ def setup(py_params_dict): update_params(params, py_params_dict) - # Number of peripherals - peripherals = [ - { - "core_name": "iob_uart", - "instance_name": "UART0", - "instance_description": "UART peripheral", - "parameters": {}, - "connect": { - "clk_en_rst": "clk_en_rst", - "cbus": "uart0_cbus", - "rs232": "rs232", - }, - }, - { - "core_name": "iob_timer", - "instance_name": "TIMER0", - "instance_description": "Timer peripheral", - "parameters": {}, - "connect": { - "clk_en_rst": "clk_en_rst", - "cbus": "timer0_cbus", - }, - }, - # NOTE: Instantiate other peripherals here - ] - # Number of peripherals = peripherals + CLINT + PLIC - num_peripherals = len(peripherals) + 2 - peripheral_addr_w = params["addr_w"] - 1 - (num_peripherals - 1).bit_length() - attributes_dict = { "original_name": "iob_soc", "name": "iob_soc", @@ -311,60 +282,8 @@ def setup(py_params_dict): "LEN_W": "AXI_LEN_W", }, }, - # Peripheral wires - { - "name": "clint_cbus", - "descr": "CLINT Control/Status Registers bus", - "interface": { - "type": "axil", - "wire_prefix": "clint_cbus_", - # "DATA_W": params["data_w"], - # "ADDR_W": params["addr_w"] - 3, - "ID_W": "AXI_ID_W", - "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", - }, - }, - { - "name": "plic_cbus", - "descr": "PLIC Control/Status Registers bus", - "interface": { - "type": "axil", - "wire_prefix": "plic_cbus_", - # "DATA_W": params["data_w"], - # "ADDR_W": params["addr_w"] - 3, - "ID_W": "AXI_ID_W", - "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", - }, - }, - { - "name": "uart0_cbus", - "descr": "AXI bus for uart0 CSRs", - "interface": { - "type": "axil", - "wire_prefix": "uart0_", - "ID_W": "AXI_ID_W", - "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", - }, - }, - { - "name": "timer0_cbus", - "descr": "AXI bus for timer0 CSRs", - "interface": { - "type": "axil", - "wire_prefix": "timer0_", - "ID_W": "AXI_ID_W", - "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", - }, - }, - # NOTE: Add peripheral wires here + # Peripheral cbus wires added automatically + # NOTE: Add other peripheral wires here ] attributes_dict["blocks"] = [ { @@ -454,17 +373,37 @@ def setup(py_params_dict): "clk_en_rst": "clk_en_rst", "reset": "split_reset", "input": "axil_periphs_cbus", - "output_0": "uart0_cbus", - "output_1": "timer0_cbus", - # NOTE: Connect other peripherals here - "output_2": "clint_cbus", - "output_3": "plic_cbus", + # Peripherals cbus connections added automatically }, - "num_outputs": num_peripherals, + "num_outputs": 0, # Num outputs configured automatically "addr_w": params["addr_w"] - 1, }, - ] - attributes_dict["blocks"] += peripherals + [ + # Peripherals + { + "core_name": "iob_uart", + "instance_name": "UART0", + "instance_description": "UART peripheral", + "is_peripheral": True, + "parameters": {}, + "connect": { + "clk_en_rst": "clk_en_rst", + # Cbus connected automatically + "rs232": "rs232", + }, + }, + { + "core_name": "iob_timer", + "instance_name": "TIMER0", + "instance_description": "Timer peripheral", + "is_peripheral": True, + "parameters": {}, + "connect": { + "clk_en_rst": "clk_en_rst", + # Cbus connected automatically + }, + }, + # NOTE: Instantiate other peripherals here, using the 'is_peripheral' flag + # # Modules that need to be setup, but are not instantiated directly inside # 'iob_soc' Verilog module # Testbench @@ -514,6 +453,6 @@ def setup(py_params_dict): } ] - iob_soc_scripts(attributes_dict, peripherals, params, py_params_dict) + iob_soc_scripts(attributes_dict, params, py_params_dict) return attributes_dict diff --git a/scripts/iob_soc_utils.py b/scripts/iob_soc_utils.py index 91a2ab681..0ca0bfd42 100644 --- a/scripts/iob_soc_utils.py +++ b/scripts/iob_soc_utils.py @@ -21,14 +21,15 @@ def update_params(params, py_params): params[name] = type(default_val)(py_params[name]) -def iob_soc_scripts(attributes_dict, peripherals, params, py_params): +def iob_soc_scripts(attributes_dict, params, py_params): """IOb-SoC automatic setup scripts. :param dict attributes_dict: iob_soc attributes - :param list peripherals: list of peripheral blocks :param dict params: iob_soc python parameters :param dict py_params: iob_soc argument python parameters """ set_build_dir(attributes_dict, py_params) + peripherals = get_iob_soc_peripherals_list(attributes_dict) + connect_peripherals_cbus(attributes_dict, peripherals, params) generate_makefile_segments(attributes_dict, peripherals, params, py_params) generate_peripheral_base_addresses(attributes_dict, peripherals, params, py_params) @@ -50,6 +51,92 @@ def set_build_dir(attributes_dict, py_params): attributes_dict["build_dir"] = build_dir +def get_iob_soc_peripherals_list(attributes_dict): + """Parses blocks list in iob_soc attributes, for blocks with the `is_peripheral` attribute set to True. + Also removes `is_peripheral` attribute from each block after adding it to the peripherals list. + """ + peripherals = [] + for block in attributes_dict["blocks"]: + if "is_peripheral" in block and block["is_peripheral"]: + peripherals.append(block) + block.pop("is_peripheral") + return peripherals + + +def connect_peripherals_cbus(attributes_dict, peripherals, params): + """Update given attributes_dict to connect peripherals cbus to system's pbus_split. + :param dict attributes_dict: iob_soc attributes + :param list peripherals: list of peripheral blocks + :param dict params: iob_soc python parameters + """ + # Find pbus_split + pbus_split = None + for block in attributes_dict["blocks"]: + if block["instance_name"] == "iob_axil_pbus_split": + pbus_split = block + + # Number of peripherals = peripherals + CLINT + PLIC + num_peripherals = len(peripherals) + 2 + peripheral_addr_w = params["addr_w"] - 1 - (num_peripherals - 1).bit_length() + + # Configure number of connections to pbus_split + pbus_split["num_outputs"] = num_peripherals + + for idx, peripheral in enumerate(peripherals): + peripheral_name = peripheral["instance_name"].lower() + # Add peripheral cbus wire + attributes_dict["wires"].append( + { + "name": f"{peripheral_name}_cbus", + "descr": f"{peripheral_name} Control/Status Registers bus", + "interface": { + "type": "axil", + "wire_prefix": f"{peripheral_name}_cbus_", + "ID_W": "AXI_ID_W", + "ADDR_W": peripheral_addr_w, + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + ) + # Connect cbus to pbus_split + pbus_split["connect"][f"output_{idx}"] = f"{peripheral_name}_cbus" + # Connect cbus to peripheral + peripheral["connect"]["cbus"] = f"{peripheral_name}_cbus" + + # Add CLINT and PLIC wires (they are not in peripherals list) + attributes_dict["wires"] += [ + { + "name": "clint_cbus", + "descr": "CLINT Control/Status Registers bus", + "interface": { + "type": "axil", + "wire_prefix": "clint_cbus_", + "ID_W": "AXI_ID_W", + "ADDR_W": peripheral_addr_w, + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + { + "name": "plic_cbus", + "descr": "PLIC Control/Status Registers bus", + "interface": { + "type": "axil", + "wire_prefix": "plic_cbus_", + "ID_W": "AXI_ID_W", + "ADDR_W": peripheral_addr_w, + "DATA_W": "AXI_DATA_W", + "LEN_W": "AXI_LEN_W", + }, + }, + ] + + # Connect CLINT and PLIC cbus to last outputs of pbus_split + pbus_split["connect"][f"output_{num_peripherals-2}"] = "clint_cbus" + pbus_split["connect"][f"output_{num_peripherals-1}"] = "plic_cbus" + + def generate_peripheral_base_addresses( attributes_dict, peripherals_list, params, py_params ): From 175906d01223ad93183c87efe167a66f2f73daa8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 17 Sep 2024 22:24:55 +0100 Subject: [PATCH 03/12] feat(iob_system): Rename iob_soc to iob_system; Move system to lib. The 'iob_soc' core is now named 'iob_system' and was moved to lib. The future 'iob_soc' core will be an extension to the current 'iob_system'. --- .gitmodules | 2 +- .../hardware/iob_system/README.md | 16 ++-- .../iob_system/document}/doc_build.mk | 0 .../iob_system/document}/figures/bd.odg | Bin .../iob_system/document}/figures/csr_gen.odg | Bin .../iob_system/document}/figures/inst.odg | Bin .../iob_system/document}/figures/symb.odg | Bin .../iob_system/document}/figures/tbbd.odg | Bin .../iob_system/document}/tsrc/bd_desc.tex | 0 .../iob_system/document}/tsrc/benefits.tex | 0 .../document}/tsrc/deliverables.tex | 0 .../iob_system/document}/tsrc/features.tex | 0 .../iob_system/document}/tsrc/intro.tex | 0 .../document}/tsrc/presentation.tex | 0 .../iob_system/document}/tsrc/results.tex | 0 .../iob_system/document}/tsrc/title.tex | 0 .../iob_system/document}/tsrc/ug_title.tex | 0 .../iob_system/hardware}/fpga/fpga_build.mk | 6 +- .../fpga/quartus/cyclonev_gt_dk/board.tcl | 0 .../quartus/cyclonev_gt_dk/cyclonev_gt_dk.py | 12 +-- .../quartus/cyclonev_gt_dk/cyclonev_gt_dk.sdc | 0 .../hardware}/fpga/quartus/quartus.sdc | 0 .../fpga/quartus/quartus_postmap.tcl | 0 .../iob_system/hardware}/fpga/src/fpga.sdc | 0 .../vivado/aes_ku040_db_g/aes_ku040_db_g.py | 14 +-- .../vivado/aes_ku040_db_g/aes_ku040_db_g.sdc | 0 .../fpga/vivado/aes_ku040_db_g/device.tcl | 0 .../hardware}/fpga/vivado/basys3/basys3.sdc | 0 .../hardware}/fpga/vivado/basys3/basys3.v | 4 +- .../fpga/vivado/basys3/clock_wizard.v | 0 .../hardware}/fpga/vivado/vivado.sdc | 0 .../hardware}/fpga/vivado/vivado_premap.tcl | 0 .../iob_system_cache_system.py | 12 +-- .../iob_system_mwrap/iob_system_mwrap.py | 26 +++--- .../iob_system_sim_wrapper.py | 14 +-- .../hardware}/simulation/sim_build.mk | 10 +-- .../hardware}/simulation/src/.empty | 0 .../hardware/simulation/src/iob_system_tb.cpp | 14 +-- .../hardware/simulation/src/iob_system_tb.v | 28 +++--- .../hardware}/syn/genus/syn_build.tcl | 0 .../iob_system/hardware}/syn/src/bsp.vh | 0 .../hardware/iob_system/iob_system.py | 26 +++--- .../iob_system/scripts/iob_system_utils.py | 54 ++++++------ .../software/src/iob_system_firmware.S | 17 ++++ .../software/src/iob_system_firmware.c | 6 +- .../software/src/iob_system_firmware.lds | 2 +- .../software/src/iob_system_system.h | 0 lib/hardware/iob_system/software/sw_build.mk | 81 ++++++++++++++++++ .../submodules}/BOOTROM/iob_bootrom.py | 0 .../BOOTROM/software/src/iob_system_boot.S | 17 ++++ .../BOOTROM/software/src/iob_system_boot.c | 14 +-- .../BOOTROM/software/src/iob_system_boot.lds | 2 +- .../BOOTROM/software/src/iob_system_preboot.S | 8 +- .../software/src/iob_system_preboot.lds | 0 .../hardware/iob_system/submodules}/VEXRISCV | 0 software/src/iob_soc_firmware.S | 17 ---- software/sw_build.mk | 81 ------------------ .../BOOTROM/software/src/iob_soc_boot.S | 17 ---- 58 files changed, 250 insertions(+), 250 deletions(-) rename README.md => lib/hardware/iob_system/README.md (89%) rename {document => lib/hardware/iob_system/document}/doc_build.mk (100%) rename {document => lib/hardware/iob_system/document}/figures/bd.odg (100%) rename {document => lib/hardware/iob_system/document}/figures/csr_gen.odg (100%) rename {document => lib/hardware/iob_system/document}/figures/inst.odg (100%) rename {document => lib/hardware/iob_system/document}/figures/symb.odg (100%) rename {document => lib/hardware/iob_system/document}/figures/tbbd.odg (100%) rename {document => lib/hardware/iob_system/document}/tsrc/bd_desc.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/benefits.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/deliverables.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/features.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/intro.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/presentation.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/results.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/title.tex (100%) rename {document => lib/hardware/iob_system/document}/tsrc/ug_title.tex (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/fpga_build.mk (55%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/quartus/cyclonev_gt_dk/board.tcl (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py (98%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.sdc (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/quartus/quartus.sdc (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/quartus/quartus_postmap.tcl (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/src/fpga.sdc (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py (97%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.sdc (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/aes_ku040_db_g/device.tcl (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/basys3/basys3.sdc (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/basys3/basys3.v (91%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/basys3/clock_wizard.v (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/vivado.sdc (100%) rename {hardware => lib/hardware/iob_system/hardware}/fpga/vivado/vivado_premap.tcl (100%) rename hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py => lib/hardware/iob_system/hardware/modules/iob_system_cache_system/iob_system_cache_system.py (96%) rename hardware/modules/iob_soc_mwrap/iob_soc_mwrap.py => lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py (77%) rename hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py => lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py (96%) rename {hardware => lib/hardware/iob_system/hardware}/simulation/sim_build.mk (69%) rename {hardware => lib/hardware/iob_system/hardware}/simulation/src/.empty (100%) rename hardware/simulation/src/iob_soc_tb.cpp => lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.cpp (94%) rename hardware/simulation/src/iob_soc_tb.v => lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.v (88%) rename {hardware => lib/hardware/iob_system/hardware}/syn/genus/syn_build.tcl (100%) rename {hardware => lib/hardware/iob_system/hardware}/syn/src/bsp.vh (100%) rename iob_soc.py => lib/hardware/iob_system/iob_system.py (95%) rename scripts/iob_soc_utils.py => lib/hardware/iob_system/scripts/iob_system_utils.py (83%) create mode 100644 lib/hardware/iob_system/software/src/iob_system_firmware.S rename software/src/iob_soc_firmware.c => lib/hardware/iob_system/software/src/iob_system_firmware.c (95%) rename software/src/iob_soc_firmware.lds => lib/hardware/iob_system/software/src/iob_system_firmware.lds (92%) rename software/src/iob_soc_system.h => lib/hardware/iob_system/software/src/iob_system_system.h (100%) create mode 100644 lib/hardware/iob_system/software/sw_build.mk rename {submodules => lib/hardware/iob_system/submodules}/BOOTROM/iob_bootrom.py (100%) create mode 100644 lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.S rename submodules/BOOTROM/software/src/iob_soc_boot.c => lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.c (81%) rename submodules/BOOTROM/software/src/iob_soc_boot.lds => lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.lds (92%) rename submodules/BOOTROM/software/src/iob_soc_preboot.S => lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.S (70%) rename submodules/BOOTROM/software/src/iob_soc_preboot.lds => lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.lds (100%) rename {submodules => lib/hardware/iob_system/submodules}/VEXRISCV (100%) delete mode 100644 software/src/iob_soc_firmware.S delete mode 100644 software/sw_build.mk delete mode 100644 submodules/BOOTROM/software/src/iob_soc_boot.S diff --git a/.gitmodules b/.gitmodules index 92a26f7fa..e239baf8d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "submodules/VEXRISCV"] - path = submodules/VEXRISCV + path = lib/hardware/iob_system/submodules/VEXRISCV url = git@github.com:IObundle/iob-vexriscv.git diff --git a/README.md b/lib/hardware/iob_system/README.md similarity index 89% rename from README.md rename to lib/hardware/iob_system/README.md index 78da60342..8e1a7fd5f 100644 --- a/README.md +++ b/lib/hardware/iob_system/README.md @@ -54,8 +54,8 @@ GitHub will ask for your password for each downloaded module if you clone it by setup GitHub access with *ssh* and type: ```Bash -git clone --recursive git@github.com:IObundle/iob-soc.git -cd iob-soc +git clone --recursive git@github.com:IObundle/iob-system.git +cd iob-system ``` Alternatively, you can still clone this repository using *https* if you cache @@ -65,7 +65,7 @@ credential.helper 'cache --timeout='`` ## Configure your SoC -To configure your system, edit the `iob_soc.py` file, which can be found at the +To configure your system, edit the `iob_system.py` file, which can be found at the repository root. This file has the system configuration variables; hopefully, each variable is explained by a comment. @@ -120,12 +120,12 @@ export LM_LICENSE_FILE=port@licenseserver.myorg.com;lic_or_dat_file ## Create the build directory -IOb-SoC uses intricate Python scripting to create a build directory with all the necessary files and makefiles to run the different tools. The build directory is placed in the folder above at ../iob_soc_Vx.y by running the following command from the root directory. +IOb-SoC uses intricate Python scripting to create a build directory with all the necessary files and makefiles to run the different tools. The build directory is placed in the folder above at ../iob_system_Vx.y by running the following command from the root directory. ```Bash make setup ``` -If you want to avoid getting into the complications of our Python scripts, use the ../iob_soc_Vx.y directory to build your SoC. It only has code files and a few Makefiles. Enter this directory and call the available Makefile targets. Alternatively, using another Makefile in the IOb-SoC root directory, the same targets can be called. For example, to run the simulation, the IOb-SoC's top Makefile has the following target: +If you want to avoid getting into the complications of our Python scripts, use the ../iob_system_Vx.y directory to build your SoC. It only has code files and a few Makefiles. Enter this directory and call the available Makefile targets. Alternatively, using another Makefile in the IOb-SoC root directory, the same targets can be called. For example, to run the simulation, the IOb-SoC's top Makefile has the following target: ```Bash sim-run: @@ -141,7 +141,7 @@ You can *emulate* IOb-SoC's on a PC to develop and debug your embedded system. T make pc-emul-run ``` -The Makefile compiles and runs the software in the `../iob_soc_Vx.y/software/` directory. The Makefile includes the `sw_build.mk` segment supplied initially in the `./software/` directory in the IOb-SoC root. Please feel free to change this file for your specific project. To run an emulation test comparing the result to the expected result, run +The Makefile compiles and runs the software in the `../iob_system_Vx.y/software/` directory. The Makefile includes the `sw_build.mk` segment supplied initially in the `./software/` directory in the IOb-SoC root. Please feel free to change this file for your specific project. To run an emulation test comparing the result to the expected result, run ```Bash make pc-emul-test ``` @@ -155,7 +155,7 @@ make sim-run [SIMULATOR=icarus!verilator|xcelium|vcs|questa] [INIT_MEM=0|1] [USE The INIT_MEM variable specifies whether the firmware is initially loaded in the memory, skipping the boot process, and the USE_EXTMEM variable indicates whether an external memory such as DRAM is used, in which case the cache system described above is instantiated. -The Makefile compiles and runs the software in the `../iob_soc_Vx.y/hardware/simulation` directory. The Makefile includes the `./hardware/simulation/sim_build.mk`, which you can change for your project. To run a simulation test comprising several simulations with different parameters, run +The Makefile compiles and runs the software in the `../iob_system_Vx.y/hardware/simulation` directory. The Makefile includes the `./hardware/simulation/sim_build.mk`, which you can change for your project. To run a simulation test comprising several simulations with different parameters, run ```Bash make sim-test ``` @@ -308,7 +308,7 @@ The work has been partially performed in the scope of the A-IQ Ready project, wh The A-IQ Ready project is supported by the Chips Joint Undertaking (Chips JU) - the Public-Private Partnership for research, development, and innovation under Horizon Europe – and National Authorities under Grant Agreement No. 101096658. -![image](https://github.com/IObundle/iob-soc/assets/5718971/78f2a3ee-d10b-4989-b221-71154fe6e409) ![image](https://github.com/IObundle/iob-soc/assets/5718971/d57e0430-bb60-42e3-82a3-c5b6b0417322) +![image](https://github.com/IObundle/iob-system/assets/5718971/78f2a3ee-d10b-4989-b221-71154fe6e409) ![image](https://github.com/IObundle/iob-system/assets/5718971/d57e0430-bb60-42e3-82a3-c5b6b0417322) This project provides the basic infrastructure to other projects funded through the NGI Assure Fund, a fund established by NLnet diff --git a/document/doc_build.mk b/lib/hardware/iob_system/document/doc_build.mk similarity index 100% rename from document/doc_build.mk rename to lib/hardware/iob_system/document/doc_build.mk diff --git a/document/figures/bd.odg b/lib/hardware/iob_system/document/figures/bd.odg similarity index 100% rename from document/figures/bd.odg rename to lib/hardware/iob_system/document/figures/bd.odg diff --git a/document/figures/csr_gen.odg b/lib/hardware/iob_system/document/figures/csr_gen.odg similarity index 100% rename from document/figures/csr_gen.odg rename to lib/hardware/iob_system/document/figures/csr_gen.odg diff --git a/document/figures/inst.odg b/lib/hardware/iob_system/document/figures/inst.odg similarity index 100% rename from document/figures/inst.odg rename to lib/hardware/iob_system/document/figures/inst.odg diff --git a/document/figures/symb.odg b/lib/hardware/iob_system/document/figures/symb.odg similarity index 100% rename from document/figures/symb.odg rename to lib/hardware/iob_system/document/figures/symb.odg diff --git a/document/figures/tbbd.odg b/lib/hardware/iob_system/document/figures/tbbd.odg similarity index 100% rename from document/figures/tbbd.odg rename to lib/hardware/iob_system/document/figures/tbbd.odg diff --git a/document/tsrc/bd_desc.tex b/lib/hardware/iob_system/document/tsrc/bd_desc.tex similarity index 100% rename from document/tsrc/bd_desc.tex rename to lib/hardware/iob_system/document/tsrc/bd_desc.tex diff --git a/document/tsrc/benefits.tex b/lib/hardware/iob_system/document/tsrc/benefits.tex similarity index 100% rename from document/tsrc/benefits.tex rename to lib/hardware/iob_system/document/tsrc/benefits.tex diff --git a/document/tsrc/deliverables.tex b/lib/hardware/iob_system/document/tsrc/deliverables.tex similarity index 100% rename from document/tsrc/deliverables.tex rename to lib/hardware/iob_system/document/tsrc/deliverables.tex diff --git a/document/tsrc/features.tex b/lib/hardware/iob_system/document/tsrc/features.tex similarity index 100% rename from document/tsrc/features.tex rename to lib/hardware/iob_system/document/tsrc/features.tex diff --git a/document/tsrc/intro.tex b/lib/hardware/iob_system/document/tsrc/intro.tex similarity index 100% rename from document/tsrc/intro.tex rename to lib/hardware/iob_system/document/tsrc/intro.tex diff --git a/document/tsrc/presentation.tex b/lib/hardware/iob_system/document/tsrc/presentation.tex similarity index 100% rename from document/tsrc/presentation.tex rename to lib/hardware/iob_system/document/tsrc/presentation.tex diff --git a/document/tsrc/results.tex b/lib/hardware/iob_system/document/tsrc/results.tex similarity index 100% rename from document/tsrc/results.tex rename to lib/hardware/iob_system/document/tsrc/results.tex diff --git a/document/tsrc/title.tex b/lib/hardware/iob_system/document/tsrc/title.tex similarity index 100% rename from document/tsrc/title.tex rename to lib/hardware/iob_system/document/tsrc/title.tex diff --git a/document/tsrc/ug_title.tex b/lib/hardware/iob_system/document/tsrc/ug_title.tex similarity index 100% rename from document/tsrc/ug_title.tex rename to lib/hardware/iob_system/document/tsrc/ug_title.tex diff --git a/hardware/fpga/fpga_build.mk b/lib/hardware/iob_system/hardware/fpga/fpga_build.mk similarity index 55% rename from hardware/fpga/fpga_build.mk rename to lib/hardware/iob_system/hardware/fpga/fpga_build.mk index f3c07d33a..1bd479897 100644 --- a/hardware/fpga/fpga_build.mk +++ b/lib/hardware/iob_system/hardware/fpga/fpga_build.mk @@ -1,9 +1,9 @@ include auto_fpga_build.mk -# Add iob-soc software as a build dependency -RUN_DEPS+=iob_soc_bootrom.hex iob_soc_firmware.hex +# Add iob-system software as a build dependency +RUN_DEPS+=iob_system_bootrom.hex iob_system_firmware.hex # Don't add firmware to BUILD_DEPS if we are not initializing memory since we don't want to rebuild the bitstream when we modify it. -BUILD_DEPS+=iob_soc_bootrom.hex $(if $(filter $(INIT_MEM),1),iob_soc_firmware.hex) +BUILD_DEPS+=iob_system_bootrom.hex $(if $(filter $(INIT_MEM),1),iob_system_firmware.hex) QUARTUS_SEED ?=5 diff --git a/hardware/fpga/quartus/cyclonev_gt_dk/board.tcl b/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/board.tcl similarity index 100% rename from hardware/fpga/quartus/cyclonev_gt_dk/board.tcl rename to lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/board.tcl diff --git a/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py b/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py similarity index 98% rename from hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py rename to lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py index 853abf3df..e53a9b15f 100644 --- a/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py +++ b/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py @@ -1,5 +1,5 @@ def setup(py_params_dict): - params = py_params_dict["iob_soc_params"] + params = py_params_dict["iob_system_params"] attributes_dict = { "original_name": "cyclonev_gt_dk", @@ -132,7 +132,7 @@ def setup(py_params_dict): }, { "name": "rs232_int", - "descr": "iob-soc uart interface", + "descr": "iob-system uart interface", "signals": [ {"name": "rxd"}, {"name": "txd"}, @@ -245,8 +245,8 @@ def setup(py_params_dict): # attributes_dict["blocks"] = [ { - "core_name": "iob_soc_mwrap", - "instance_name": "iob_soc_mwrap", + "core_name": "iob_system_mwrap", + "instance_name": "iob_system_mwrap", "instance_description": "IOb-SoC memory wrapper", "parameters": { "AXI_ID_W": "AXI_ID_W", @@ -260,7 +260,7 @@ def setup(py_params_dict): "axi": "axi", }, "dest_dir": "hardware/common_src", - "iob_soc_params": params, + "iob_system_params": params, }, { "core_name": "iob_reset_sync", @@ -334,7 +334,7 @@ def setup(py_params_dict): if params["init_mem"]: attributes_dict["blocks"][-1]["parameters"].update( { - "FILE": '"iob_soc_firmware"', + "FILE": '"iob_system_firmware"', } ) if params["use_ethernet"]: diff --git a/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.sdc b/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.sdc similarity index 100% rename from hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.sdc rename to lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.sdc diff --git a/hardware/fpga/quartus/quartus.sdc b/lib/hardware/iob_system/hardware/fpga/quartus/quartus.sdc similarity index 100% rename from hardware/fpga/quartus/quartus.sdc rename to lib/hardware/iob_system/hardware/fpga/quartus/quartus.sdc diff --git a/hardware/fpga/quartus/quartus_postmap.tcl b/lib/hardware/iob_system/hardware/fpga/quartus/quartus_postmap.tcl similarity index 100% rename from hardware/fpga/quartus/quartus_postmap.tcl rename to lib/hardware/iob_system/hardware/fpga/quartus/quartus_postmap.tcl diff --git a/hardware/fpga/src/fpga.sdc b/lib/hardware/iob_system/hardware/fpga/src/fpga.sdc similarity index 100% rename from hardware/fpga/src/fpga.sdc rename to lib/hardware/iob_system/hardware/fpga/src/fpga.sdc diff --git a/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py b/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py similarity index 97% rename from hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py rename to lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py index a27eaa026..e953593d2 100644 --- a/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py +++ b/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py @@ -1,6 +1,6 @@ def setup(py_params_dict): # user-passed parameters - params = py_params_dict["iob_soc_params"] + params = py_params_dict["iob_system_params"] attributes_dict = { "original_name": "aes_ku040_db_g", @@ -127,7 +127,7 @@ def setup(py_params_dict): }, { "name": "rs232_int", - "descr": "iob-soc uart interface", + "descr": "iob-system uart interface", "signals": [ {"name": "rxd"}, {"name": "txd"}, @@ -210,7 +210,7 @@ def setup(py_params_dict): attributes_dict["wires"] += [ { "name": "clk_wizard_out", - "descr": "Connect clock wizard outputs to iob-soc clock and reset", + "descr": "Connect clock wizard outputs to iob-system clock and reset", "signals": [ {"name": "clk"}, {"name": "intercon_rst"}, @@ -264,8 +264,8 @@ def setup(py_params_dict): attributes_dict["blocks"] = [ { # IOb-SoC Memory Wrapper - "core_name": "iob_soc_mwrap", - "instance_name": "iob_soc_mwrap", + "core_name": "iob_system_mwrap", + "instance_name": "iob_system_mwrap", "instance_description": "IOb-SoC instance", "parameters": { "AXI_ID_W": "AXI_ID_W", @@ -279,7 +279,7 @@ def setup(py_params_dict): "axi": "axi", }, "dest_dir": "hardware/common_src", - "iob_soc_params": params, + "iob_system_params": params, }, { "core_name": "xilinx_axi_interconnect", @@ -359,7 +359,7 @@ def setup(py_params_dict): if params["init_mem"]: attributes_dict["blocks"][-1]["parameters"].update( { - "FILE": '"iob_soc_firmware"', + "FILE": '"iob_system_firmware"', } ) if params["use_ethernet"]: diff --git a/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.sdc b/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.sdc similarity index 100% rename from hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.sdc rename to lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.sdc diff --git a/hardware/fpga/vivado/aes_ku040_db_g/device.tcl b/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/device.tcl similarity index 100% rename from hardware/fpga/vivado/aes_ku040_db_g/device.tcl rename to lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/device.tcl diff --git a/hardware/fpga/vivado/basys3/basys3.sdc b/lib/hardware/iob_system/hardware/fpga/vivado/basys3/basys3.sdc similarity index 100% rename from hardware/fpga/vivado/basys3/basys3.sdc rename to lib/hardware/iob_system/hardware/fpga/vivado/basys3/basys3.sdc diff --git a/hardware/fpga/vivado/basys3/basys3.v b/lib/hardware/iob_system/hardware/fpga/vivado/basys3/basys3.v similarity index 91% rename from hardware/fpga/vivado/basys3/basys3.v rename to lib/hardware/iob_system/hardware/fpga/vivado/basys3/basys3.v index 135f462ed..ff68d3417 100644 --- a/hardware/fpga/vivado/basys3/basys3.v +++ b/lib/hardware/iob_system/hardware/fpga/vivado/basys3/basys3.v @@ -34,8 +34,8 @@ module basys3 ( // // SYSTEM // - iob_soc_mwrap iob_soc ( - `include "iob_soc_pportmaps.vs" + iob_system_mwrap iob_system ( + `include "iob_system_pportmaps.vs" .clk_i (clk), .cke_i (1'b1), .arst_i(sys_rst), diff --git a/hardware/fpga/vivado/basys3/clock_wizard.v b/lib/hardware/iob_system/hardware/fpga/vivado/basys3/clock_wizard.v similarity index 100% rename from hardware/fpga/vivado/basys3/clock_wizard.v rename to lib/hardware/iob_system/hardware/fpga/vivado/basys3/clock_wizard.v diff --git a/hardware/fpga/vivado/vivado.sdc b/lib/hardware/iob_system/hardware/fpga/vivado/vivado.sdc similarity index 100% rename from hardware/fpga/vivado/vivado.sdc rename to lib/hardware/iob_system/hardware/fpga/vivado/vivado.sdc diff --git a/hardware/fpga/vivado/vivado_premap.tcl b/lib/hardware/iob_system/hardware/fpga/vivado/vivado_premap.tcl similarity index 100% rename from hardware/fpga/vivado/vivado_premap.tcl rename to lib/hardware/iob_system/hardware/fpga/vivado/vivado_premap.tcl diff --git a/hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py b/lib/hardware/iob_system/hardware/modules/iob_system_cache_system/iob_system_cache_system.py similarity index 96% rename from hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py rename to lib/hardware/iob_system/hardware/modules/iob_system_cache_system/iob_system_cache_system.py index 9de6ae284..e6f9286b2 100644 --- a/hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py +++ b/lib/hardware/iob_system/hardware/modules/iob_system_cache_system/iob_system_cache_system.py @@ -3,8 +3,8 @@ def setup(py_params_dict): DATA_W = py_params_dict["data_w"] if "data_w" in py_params_dict else 32 MEM_ADDR_W = py_params_dict["mem_addr_w"] if "mem_addr_w" in py_params_dict else 32 attributes_dict = { - "original_name": "iob_soc_cache_system", - "name": "iob_soc_cache_system", + "original_name": "iob_system_cache_system", + "name": "iob_system_cache_system", "version": "0.1", "confs": [ { @@ -125,7 +125,7 @@ def setup(py_params_dict): "DATA_W": DATA_W, "ADDR_W": MEM_ADDR_W, }, - "descr": "iob-soc external memory instruction cache interface", + "descr": "iob-system external memory instruction cache interface", }, { "name": "dcache", @@ -135,7 +135,7 @@ def setup(py_params_dict): "DATA_W": DATA_W, "ADDR_W": MEM_ADDR_W, }, - "descr": "iob-soc external memory data cache interface", + "descr": "iob-system external memory data cache interface", }, { "name": "l2cache", @@ -145,7 +145,7 @@ def setup(py_params_dict): "DATA_W": DATA_W, "ADDR_W": MEM_ADDR_W, }, - "descr": "iob-soc external memory l2 cache interface", + "descr": "iob-system external memory l2 cache interface", }, ] attributes_dict["blocks"] = [ @@ -295,7 +295,7 @@ def setup(py_params_dict): .wtb_empty_i (1'b1), .wtb_empty_o (l2_wtb_empty), // AXI interface - `include "iob_soc_cache_system_axi_m_m_portmap.vs" + `include "iob_system_cache_system_axi_m_m_portmap.vs" .clk_i (clk_i), .cke_i (cke_i), .arst_i (arst_i) diff --git a/hardware/modules/iob_soc_mwrap/iob_soc_mwrap.py b/lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py similarity index 77% rename from hardware/modules/iob_soc_mwrap/iob_soc_mwrap.py rename to lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py index ad54f7b09..de964f17b 100644 --- a/hardware/modules/iob_soc_mwrap/iob_soc_mwrap.py +++ b/lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py @@ -1,34 +1,34 @@ import copy -import iob_soc +import iob_system def setup(py_params_dict): - params = py_params_dict["iob_soc_params"] + params = py_params_dict["iob_system_params"] - iob_soc_attr = iob_soc.setup(params) + iob_system_attr = iob_system.setup(params) attributes_dict = { - "original_name": "iob_soc_mwrap", - "name": "iob_soc_mwrap", + "original_name": "iob_system_mwrap", + "name": "iob_system_mwrap", "version": "0.1", "confs": [ { "name": "BOOT_HEXFILE", "descr": "Bootloader file name", "type": "P", - "val": '"iob_soc_bootrom"', + "val": '"iob_system_bootrom"', "min": "NA", "max": "NA", }, ] - + iob_soc_attr["confs"], + + iob_system_attr["confs"], } - # Declare memory wrapper ports and wires automatically based on iob-soc ports. + # Declare memory wrapper ports and wires automatically based on iob-system ports. mwrap_wires = [] mwrap_ports = [] - for port in iob_soc_attr["ports"]: + for port in iob_system_attr["ports"]: if port["name"] == "rom_bus": wire = copy.deepcopy(port) if "interface" in wire and "port_prefix" in wire["interface"]: @@ -70,15 +70,15 @@ def setup(py_params_dict): }, # IOb-SoC { - "core_name": "iob_soc", - "instance_name": "iob_soc", + "core_name": "iob_system", + "instance_name": "iob_system", "instance_description": "IOb-SoC core", "parameters": { i["name"]: i["name"] - for i in iob_soc_attr["confs"] + for i in iob_system_attr["confs"] if i["type"] in ["P", "F"] }, - "connect": {i["name"]: i["name"] for i in iob_soc_attr["ports"]}, + "connect": {i["name"]: i["name"] for i in iob_system_attr["ports"]}, **params, }, ] diff --git a/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py b/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py similarity index 96% rename from hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py rename to lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py index a6622b635..eea0ce654 100644 --- a/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py +++ b/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py @@ -1,9 +1,9 @@ def setup(py_params_dict): - params = py_params_dict["iob_soc_params"] + params = py_params_dict["iob_system_params"] attributes_dict = { - "original_name": "iob_soc_sim_wrapper", - "name": "iob_soc_sim_wrapper", + "original_name": "iob_system_sim_wrapper", + "name": "iob_system_sim_wrapper", "version": "0.1", "confs": [ { @@ -176,8 +176,8 @@ def setup(py_params_dict): # attributes_dict["blocks"] = [ { - "core_name": "iob_soc_mwrap", - "instance_name": "iob_soc_mwrap", + "core_name": "iob_system_mwrap", + "instance_name": "iob_system_mwrap", "instance_description": "IOb-SoC memory wrapper", "parameters": { "AXI_ID_W": "AXI_ID_W", @@ -191,7 +191,7 @@ def setup(py_params_dict): "axi": "axi", }, "dest_dir": "hardware/common_src", - "iob_soc_params": params, + "iob_system_params": params, }, { "core_name": "iob_uart", @@ -243,7 +243,7 @@ def setup(py_params_dict): if params["init_mem"]: attributes_dict["blocks"][-1]["parameters"].update( { - "FILE": '"iob_soc_firmware"', + "FILE": '"iob_system_firmware"', } ) if params["use_ethernet"]: diff --git a/hardware/simulation/sim_build.mk b/lib/hardware/iob_system/hardware/simulation/sim_build.mk similarity index 69% rename from hardware/simulation/sim_build.mk rename to lib/hardware/iob_system/hardware/simulation/sim_build.mk index dc86748d3..36ee7630a 100644 --- a/hardware/simulation/sim_build.mk +++ b/lib/hardware/iob_system/hardware/simulation/sim_build.mk @@ -1,12 +1,12 @@ include auto_sim_build.mk -# Add iob-soc software as a build dependency -HEX+=iob_soc_bootrom.hex iob_soc_firmware.hex +# Add iob-system software as a build dependency +HEX+=iob_system_bootrom.hex iob_system_firmware.hex ROOT_DIR :=../.. include $(ROOT_DIR)/software/sw_build.mk -VTOP:=iob_soc_tb +VTOP:=iob_system_tb # SOURCES ifeq ($(SIMULATOR),verilator) @@ -17,13 +17,13 @@ ifeq ($(USE_ETHERNET),1) VSRC+=./src/iob_eth_csrs_emb_verilator.c ./src/iob_eth_driver_tb.cpp endif -# get header files (needed for iob_soc_tb.cpp) +# get header files (needed for iob_system_tb.cpp) VHDR+=iob_uart_csrs.h iob_uart_csrs.h: ../../software/src/iob_uart_csrs.h cp $< $@ # verilator top module -VTOP:=iob_soc_sim_wrapper +VTOP:=iob_system_sim_wrapper endif diff --git a/hardware/simulation/src/.empty b/lib/hardware/iob_system/hardware/simulation/src/.empty similarity index 100% rename from hardware/simulation/src/.empty rename to lib/hardware/iob_system/hardware/simulation/src/.empty diff --git a/hardware/simulation/src/iob_soc_tb.cpp b/lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.cpp similarity index 94% rename from hardware/simulation/src/iob_soc_tb.cpp rename to lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.cpp index 3d26e5889..e4c02c35c 100644 --- a/hardware/simulation/src/iob_soc_tb.cpp +++ b/lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.cpp @@ -2,13 +2,13 @@ #include #include -#include "Viob_soc_sim_wrapper.h" +#include "Viob_system_sim_wrapper.h" #include "bsp.h" -#include "iob_soc_conf.h" +#include "iob_system_conf.h" #include "iob_uart_csrs.h" #include "iob_tasks.h" -#ifdef IOB_SOC_USE_ETHERNET +#ifdef IOB_SYSTEM_USE_ETHERNET #include "iob_eth_driver_tb.h" #endif @@ -25,7 +25,7 @@ extern timer_settings_t task_timer_settings; void cpu_inituart(iob_native_t *uart_if); -Viob_soc_sim_wrapper *dut = new Viob_soc_sim_wrapper; +Viob_system_sim_wrapper *dut = new Viob_system_sim_wrapper; void call_eval() { dut->eval(); } @@ -61,7 +61,7 @@ int main(int argc, char **argv, char **env) { &dut->uart_iob_wdata_i, &dut->uart_iob_wstrb_i, &dut->uart_iob_rdata_o, &dut->uart_iob_rvalid_o, &dut->uart_iob_ready_o}; -#ifdef IOB_SOC_USE_ETHERNET +#ifdef IOB_SYSTEM_USE_ETHERNET iob_native_t eth_if = {&dut->ethernet_iob_valid_i, &dut->ethernet_iob_addr_i, USINT, @@ -105,7 +105,7 @@ int main(int argc, char **argv, char **env) { fclose(cnsl2soc_fd); soc2cnsl_fd = fopen("./soc2cnsl", "wb"); -#ifdef IOB_SOC_USE_ETHERNET +#ifdef IOB_SYSTEM_USE_ETHERNET eth_setup(ð_if); #endif @@ -136,7 +136,7 @@ int main(int argc, char **argv, char **env) { txread_reg = 0; } -#ifdef IOB_SOC_USE_ETHERNET +#ifdef IOB_SYSTEM_USE_ETHERNET eth_relay_frames(ð_if); #endif } diff --git a/hardware/simulation/src/iob_soc_tb.v b/lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.v similarity index 88% rename from hardware/simulation/src/iob_soc_tb.v rename to lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.v index 3db784fed..1c03a6061 100644 --- a/hardware/simulation/src/iob_soc_tb.v +++ b/lib/hardware/iob_system/hardware/simulation/src/iob_system_tb.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps `include "bsp.vh" -`include "iob_soc_conf.vh" +`include "iob_system_conf.vh" `include "iob_uart_conf.vh" `include "iob_uart_csrs_def.vh" //Peripherals _csrs_def.vh file includes. `include "iob_uart_csrs_def.vh" -module iob_soc_tb; +module iob_system_tb; parameter realtime CLK_PER = 1s / `FREQ; - localparam ADDR_W = `IOB_SOC_ADDR_W; - localparam DATA_W = `IOB_SOC_DATA_W; + localparam ADDR_W = `IOB_SYSTEM_ADDR_W; + localparam DATA_W = `IOB_SYSTEM_DATA_W; //clock reg clk = 1; @@ -33,9 +33,9 @@ module iob_soc_tb; //IOb-SoC uart reg iob_valid_i; reg [`IOB_UART_CSRS_ADDR_W-1:0] iob_addr_i; - reg [ `IOB_SOC_DATA_W-1:0] iob_wdata_i; + reg [ `IOB_SYSTEM_DATA_W-1:0] iob_wdata_i; reg [ 3:0] iob_wstrb_i; - wire [ `IOB_SOC_DATA_W-1:0] iob_rdata_o; + wire [ `IOB_SYSTEM_DATA_W-1:0] iob_rdata_o; wire iob_ready_o; wire iob_rvalid_o; @@ -58,9 +58,9 @@ module iob_soc_tb; iob_wstrb_i = 0; //reset system - arst = ~`IOB_SOC_RST_POL; - #100 arst = `IOB_SOC_RST_POL; - #1_000 arst = ~`IOB_SOC_RST_POL; + arst = ~`IOB_SYSTEM_RST_POL; + #100 arst = `IOB_SYSTEM_RST_POL; + #1_000 arst = ~`IOB_SYSTEM_RST_POL; #100; @(posedge clk) #1; @@ -113,13 +113,13 @@ module iob_soc_tb; end end -`ifdef IOB_SOC_USE_ETHERNET +`ifdef IOB_SYSTEM_USE_ETHERNET //IOb-SoC ethernet wire ethernet_iob_valid; wire [`IOB_ETH_CSRS_ADDR_W-1:0] ethernet_iob_addr; - wire [ `IOB_SOC_DATA_W-1:0] ethernet_iob_wdata; + wire [ `IOB_SYSTEM_DATA_W-1:0] ethernet_iob_wdata; wire [ 3:0] ethernet_iob_wstrb; - wire [ `IOB_SOC_DATA_W-1:0] ethernet_iob_rdata; + wire [ `IOB_SYSTEM_DATA_W-1:0] ethernet_iob_rdata; wire ethernet_iob_ready; wire ethernet_iob_rvalid; @@ -137,12 +137,12 @@ module iob_soc_tb; `endif - iob_soc_sim_wrapper iob_soc_sim_wrapper ( + iob_system_sim_wrapper iob_system_sim_wrapper ( .clk_i (clk), .cke_i (1'b1), .arst_i(arst), -`ifdef IOB_SOC_USE_ETHERNET +`ifdef IOB_SYSTEM_USE_ETHERNET .ethernet_iob_valid_i (ethernet_valid), .ethernet_iob_addr_i (ethernet_addr), .ethernet_iob_wdata_i (ethernet_wdata), diff --git a/hardware/syn/genus/syn_build.tcl b/lib/hardware/iob_system/hardware/syn/genus/syn_build.tcl similarity index 100% rename from hardware/syn/genus/syn_build.tcl rename to lib/hardware/iob_system/hardware/syn/genus/syn_build.tcl diff --git a/hardware/syn/src/bsp.vh b/lib/hardware/iob_system/hardware/syn/src/bsp.vh similarity index 100% rename from hardware/syn/src/bsp.vh rename to lib/hardware/iob_system/hardware/syn/src/bsp.vh diff --git a/iob_soc.py b/lib/hardware/iob_system/iob_system.py similarity index 95% rename from iob_soc.py rename to lib/hardware/iob_system/iob_system.py index 6a73372fc..4f46d63c6 100755 --- a/iob_soc.py +++ b/lib/hardware/iob_system/iob_system.py @@ -1,10 +1,10 @@ import sys import os -# Add iob-soc scripts folder to python path +# Add iob-system scripts folder to python path sys.path.append(os.path.join(os.path.dirname(os.path.abspath(__file__)), "scripts")) -from iob_soc_utils import update_params, iob_soc_scripts +from iob_system_utils import update_params, iob_system_scripts def setup(py_params_dict): @@ -23,8 +23,8 @@ def setup(py_params_dict): update_params(params, py_params_dict) attributes_dict = { - "original_name": "iob_soc", - "name": "iob_soc", + "original_name": "iob_system", + "name": "iob_system", "version": "0.7", "is_system": True, "board_list": ["cyclonev_gt_dk", "aes_ku040_db_g"], @@ -183,7 +183,7 @@ def setup(py_params_dict): # Peripheral IO ports { "name": "rs232", - "descr": "iob-soc uart interface", + "descr": "iob-system uart interface", "interface": { "type": "rs232", }, @@ -248,7 +248,7 @@ def setup(py_params_dict): }, { "name": "bootrom_cbus", - "descr": "iob-soc boot controller data interface", + "descr": "iob-system boot controller data interface", "interface": { "type": "axi", "wire_prefix": "bootrom_", @@ -405,7 +405,7 @@ def setup(py_params_dict): # NOTE: Instantiate other peripherals here, using the 'is_peripheral' flag # # Modules that need to be setup, but are not instantiated directly inside - # 'iob_soc' Verilog module + # 'iob_system' Verilog module # Testbench { "core_name": "iob_tasks", @@ -415,11 +415,11 @@ def setup(py_params_dict): }, # Simulation wrapper { - "core_name": "iob_soc_sim_wrapper", - "instance_name": "iob_soc_sim_wrapper", + "core_name": "iob_system_sim_wrapper", + "instance_name": "iob_system_sim_wrapper", "instantiate": False, "dest_dir": "hardware/simulation/src", - "iob_soc_params": params, + "iob_system_params": params, }, # FPGA wrappers { @@ -427,14 +427,14 @@ def setup(py_params_dict): "instance_name": "aes_ku040_db_g", "instantiate": False, "dest_dir": "hardware/fpga/vivado/aes_ku040_db_g", - "iob_soc_params": params, + "iob_system_params": params, }, { "core_name": "cyclonev_gt_dk", "instance_name": "cyclonev_gt_dk", "instantiate": False, "dest_dir": "hardware/fpga/quartus/cyclonev_gt_dk", - "iob_soc_params": params, + "iob_system_params": params, }, ] attributes_dict["sw_modules"] = [ @@ -453,6 +453,6 @@ def setup(py_params_dict): } ] - iob_soc_scripts(attributes_dict, params, py_params_dict) + iob_system_scripts(attributes_dict, params, py_params_dict) return attributes_dict diff --git a/scripts/iob_soc_utils.py b/lib/hardware/iob_system/scripts/iob_system_utils.py similarity index 83% rename from scripts/iob_soc_utils.py rename to lib/hardware/iob_system/scripts/iob_system_utils.py index 0ca0bfd42..a11f3433f 100644 --- a/scripts/iob_soc_utils.py +++ b/lib/hardware/iob_system/scripts/iob_system_utils.py @@ -1,7 +1,7 @@ import os # -# Functions for iob_soc.py +# Functions for iob_system.py # @@ -21,14 +21,14 @@ def update_params(params, py_params): params[name] = type(default_val)(py_params[name]) -def iob_soc_scripts(attributes_dict, params, py_params): +def iob_system_scripts(attributes_dict, params, py_params): """IOb-SoC automatic setup scripts. - :param dict attributes_dict: iob_soc attributes - :param dict params: iob_soc python parameters - :param dict py_params: iob_soc argument python parameters + :param dict attributes_dict: iob_system attributes + :param dict params: iob_system python parameters + :param dict py_params: iob_system argument python parameters """ set_build_dir(attributes_dict, py_params) - peripherals = get_iob_soc_peripherals_list(attributes_dict) + peripherals = get_iob_system_peripherals_list(attributes_dict) connect_peripherals_cbus(attributes_dict, peripherals, params) generate_makefile_segments(attributes_dict, peripherals, params, py_params) generate_peripheral_base_addresses(attributes_dict, peripherals, params, py_params) @@ -41,8 +41,8 @@ def iob_soc_scripts(attributes_dict, params, py_params): def set_build_dir(attributes_dict, py_params): """If build_dir not given in py_params, set a default one. - :param dict attributes_dict: iob_soc attributes - :param dict py_params: iob_soc argument python parameters + :param dict attributes_dict: iob_system attributes + :param dict py_params: iob_system argument python parameters """ if "build_dir" in py_params and py_params["build_dir"]: build_dir = py_params["build_dir"] @@ -51,8 +51,8 @@ def set_build_dir(attributes_dict, py_params): attributes_dict["build_dir"] = build_dir -def get_iob_soc_peripherals_list(attributes_dict): - """Parses blocks list in iob_soc attributes, for blocks with the `is_peripheral` attribute set to True. +def get_iob_system_peripherals_list(attributes_dict): + """Parses blocks list in iob_system attributes, for blocks with the `is_peripheral` attribute set to True. Also removes `is_peripheral` attribute from each block after adding it to the peripherals list. """ peripherals = [] @@ -65,9 +65,9 @@ def get_iob_soc_peripherals_list(attributes_dict): def connect_peripherals_cbus(attributes_dict, peripherals, params): """Update given attributes_dict to connect peripherals cbus to system's pbus_split. - :param dict attributes_dict: iob_soc attributes + :param dict attributes_dict: iob_system attributes :param list peripherals: list of peripheral blocks - :param dict params: iob_soc python parameters + :param dict params: iob_system python parameters """ # Find pbus_split pbus_split = None @@ -141,10 +141,10 @@ def generate_peripheral_base_addresses( attributes_dict, peripherals_list, params, py_params ): """Create C header file containing peripheral base addresses. - :param dict attributes_dict: iob_soc attributes + :param dict attributes_dict: iob_system attributes :param list peripherals_list: list of peripheral blocks - :param dict params: iob_soc python parameters - :param dict py_params: iob_soc argument python parameters + :param dict params: iob_system python parameters + :param dict py_params: iob_system argument python parameters """ out_file = os.path.join( attributes_dict["build_dir"], "software", f"{attributes_dict['name']}_periphs.h" @@ -174,11 +174,11 @@ def generate_peripheral_base_addresses( def generate_makefile_segments(attributes_dict, peripherals, params, py_params): - """Generate automatic makefile segments for iob_soc. - :param dict attributes_dict: iob_soc attributes + """Generate automatic makefile segments for iob_system. + :param dict attributes_dict: iob_system attributes :param list peripherals: list of peripheral blocks - :param dict params: iob_soc python parameters - :param dict py_params: iob_soc argument python parameters + :param dict params: iob_system python parameters + :param dict py_params: iob_system argument python parameters """ build_dir = attributes_dict["build_dir"] @@ -191,7 +191,7 @@ def generate_makefile_segments(attributes_dict, peripherals, params, py_params): # os.makedirs(f"{build_dir}/software", exist_ok=True) with open(f"{build_dir}/software/auto_sw_build.mk", "w") as file: - file.write("#This file was auto generated by iob_soc_utils.py\n") + file.write("#This file was auto generated by iob_system_utils.py\n") # Create a list with every peripheral name, except clint, and plic file.write( "PERIPHERALS ?=" @@ -217,7 +217,7 @@ def generate_makefile_segments(attributes_dict, peripherals, params, py_params): # os.makedirs(f"{build_dir}/hardware/fpga", exist_ok=True) with open(f"{build_dir}/hardware/fpga/auto_fpga_build.mk", "w") as file: - file.write("#This file was auto generated by iob_soc_utils.py\n") + file.write("#This file was auto generated by iob_system_utils.py\n") # Set N_INTERCONNECT_SLAVES variable # TODO: Count axi interfaces automatically for peripherals with DMA @@ -237,7 +237,7 @@ def generate_makefile_segments(attributes_dict, peripherals, params, py_params): # os.makedirs(f"{build_dir}/hardware/simulation", exist_ok=True) with open(f"{build_dir}/hardware/simulation/auto_sim_build.mk", "w") as file: - file.write("#This file was auto generated by iob_soc_utils.py\n") + file.write("#This file was auto generated by iob_system_utils.py\n") if params["use_ethernet"]: file.write("USE_ETHERNET=1\n") # Set custom ethernet CONSOLE_CMD @@ -247,14 +247,14 @@ def generate_makefile_segments(attributes_dict, peripherals, params, py_params): ) # - # Create auto_iob_soc_boot.lds and auto_iob_soc_firmware.lds + # Create auto_iob_system_boot.lds and auto_iob_system_firmware.lds # os.makedirs(f"{build_dir}/software", exist_ok=True) - with open(f"{build_dir}/software/auto_iob_soc_boot.lds", "w") as file: - file.write("/* This file was auto generated by iob_soc_utils.py */\n") + with open(f"{build_dir}/software/auto_iob_system_boot.lds", "w") as file: + file.write("/* This file was auto generated by iob_system_utils.py */\n") file.write( f". = {hex((1 << params['mem_addr_w']) - (1 << params['bootrom_addr_w']))};\n" ) - with open(f"{build_dir}/software/auto_iob_soc_firmware.lds", "w") as file: - file.write("/* This file was auto generated by iob_soc_utils.py */\n") + with open(f"{build_dir}/software/auto_iob_system_firmware.lds", "w") as file: + file.write("/* This file was auto generated by iob_system_utils.py */\n") file.write(f". = {params['fw_addr']};\n") diff --git a/lib/hardware/iob_system/software/src/iob_system_firmware.S b/lib/hardware/iob_system/software/src/iob_system_firmware.S new file mode 100644 index 000000000..08a08e457 --- /dev/null +++ b/lib/hardware/iob_system/software/src/iob_system_firmware.S @@ -0,0 +1,17 @@ +#include "iob_system_conf.h" +#include "iob_system_periphs.h" +#include "iob_system_system.h" + +.section .init +.globl main + + //set stack pointer + lui sp, %hi(1 << IOB_SYSTEM_FW_ADDR_W) + addi sp, sp, %lo(1 << IOB_SYSTEM_FW_ADDR_W) + + //call main + jal ra, main + + // Jump to the pre-bootloader + li x5, 0x80000000 + jalr x0, 0(x5) diff --git a/software/src/iob_soc_firmware.c b/lib/hardware/iob_system/software/src/iob_system_firmware.c similarity index 95% rename from software/src/iob_soc_firmware.c rename to lib/hardware/iob_system/software/src/iob_system_firmware.c index 6aa3dc497..3a439aaf3 100644 --- a/software/src/iob_soc_firmware.c +++ b/lib/hardware/iob_system/software/src/iob_system_firmware.c @@ -1,7 +1,7 @@ #include "bsp.h" -#include "iob_soc_conf.h" -#include "iob_soc_periphs.h" -#include "iob_soc_system.h" +#include "iob_system_conf.h" +#include "iob_system_periphs.h" +#include "iob_system_system.h" #include "iob_timer.h" #include "iob_uart.h" #include "printf.h" diff --git a/software/src/iob_soc_firmware.lds b/lib/hardware/iob_system/software/src/iob_system_firmware.lds similarity index 92% rename from software/src/iob_soc_firmware.lds rename to lib/hardware/iob_system/software/src/iob_system_firmware.lds index 46f8a3cf1..66b433d02 100644 --- a/software/src/iob_soc_firmware.lds +++ b/lib/hardware/iob_system/software/src/iob_system_firmware.lds @@ -1,6 +1,6 @@ SECTIONS { /* Program code */ - INCLUDE auto_iob_soc_firmware.lds + INCLUDE auto_iob_system_firmware.lds .init : { *(.init) } .text : { *(.text) } diff --git a/software/src/iob_soc_system.h b/lib/hardware/iob_system/software/src/iob_system_system.h similarity index 100% rename from software/src/iob_soc_system.h rename to lib/hardware/iob_system/software/src/iob_system_system.h diff --git a/lib/hardware/iob_system/software/sw_build.mk b/lib/hardware/iob_system/software/sw_build.mk new file mode 100644 index 000000000..d6e81cb39 --- /dev/null +++ b/lib/hardware/iob_system/software/sw_build.mk @@ -0,0 +1,81 @@ +######################################### +# Embedded targets # +######################################### +ROOT_DIR ?=.. + +include $(ROOT_DIR)/software/auto_sw_build.mk + +# Local embedded makefile settings for custom bootloader and firmware targets. + +#Function to obtain parameter named $(1) in verilog header file located in $(2) +#Usage: $(call GET_MACRO,,) +GET_MACRO = $(shell grep "define $(1)" $(2) | rev | cut -d" " -f1 | rev) + +#Function to obtain parameter named $(1) from iob_system_conf.vh +GET_IOB_SYSTEM_CONF_MACRO = $(call GET_MACRO,IOB_SYSTEM_$(1),../src/iob_system_conf.vh) + +iob_system_bootrom.hex: ../../software/iob_system_preboot.bin ../../software/iob_system_boot.bin + ../../scripts/makehex.py $^ 00000080 $(call GET_IOB_SYSTEM_CONF_MACRO,BOOTROM_ADDR_W) > $@ + +iob_system_firmware.hex: iob_system_firmware.bin + ../../scripts/makehex.py $< $(call GET_IOB_SYSTEM_CONF_MACRO,MEM_ADDR_W) > $@ + ../../scripts/hex_split.py iob_system_firmware . + +iob_system_firmware.bin: ../../software/iob_system_firmware.bin + cp $< $@ + +../../software/%.bin: + make -C ../../ fw-build + +UTARGETS+=build_iob_system_software + +TEMPLATE_LDS=src/$@.lds + +IOB_SYSTEM_INCLUDES=-I. -Isrc -Iinclude + +IOB_SYSTEM_LFLAGS=-Wl,-Bstatic,-T,$(TEMPLATE_LDS),--strip-debug + +# FIRMWARE SOURCES +IOB_SYSTEM_FW_SRC=src/iob_system_firmware.S +IOB_SYSTEM_FW_SRC+=src/iob_system_firmware.c +IOB_SYSTEM_FW_SRC+=src/printf.c +# PERIPHERAL SOURCES +IOB_SYSTEM_FW_SRC+=$(addprefix src/,$(addsuffix .c,$(PERIPHERALS))) +IOB_SYSTEM_FW_SRC+=$(addprefix src/,$(addsuffix _csrs_emb.c,$(PERIPHERALS))) + +# BOOTLOADER SOURCES +IOB_SYSTEM_BOOT_SRC+=src/iob_system_boot.S +IOB_SYSTEM_BOOT_SRC+=src/iob_system_boot.c +IOB_SYSTEM_BOOT_SRC+=src/iob_uart.c +IOB_SYSTEM_BOOT_SRC+=src/iob_uart_csrs_emb.c + +# PREBOOT SOURCES +IOB_SYSTEM_PREBOOT_SRC=src/iob_system_preboot.S + +build_iob_system_software: iob_system_firmware iob_system_boot iob_system_preboot + +iob_system_firmware: + make $@.elf INCLUDES="$(IOB_SYSTEM_INCLUDES)" LFLAGS="$(IOB_SYSTEM_LFLAGS) -Wl,-Map,$@.map" SRC="$(IOB_SYSTEM_FW_SRC)" TEMPLATE_LDS="$(TEMPLATE_LDS)" + +iob_system_boot: + make $@.elf INCLUDES="$(IOB_SYSTEM_INCLUDES)" LFLAGS="$(IOB_SYSTEM_LFLAGS) -Wl,-Map,$@.map" SRC="$(IOB_SYSTEM_BOOT_SRC)" TEMPLATE_LDS="$(TEMPLATE_LDS)" + +iob_system_preboot: + make $@.elf INCLUDES="$(IOB_SYSTEM_INCLUDES)" LFLAGS="$(IOB_SYSTEM_LFLAGS) -Wl,-Map,$@.map" SRC="$(IOB_SYSTEM_PREBOOT_SRC)" TEMPLATE_LDS="$(TEMPLATE_LDS)" + + +.PHONY: build_iob_system_software iob_system_firmware iob_system_boot + +######################################### +# PC emulation targets # +######################################### +# Local pc-emul makefile settings for custom pc emulation targets. + +# SOURCES +EMUL_SRC+=src/iob_system_firmware.c +EMUL_SRC+=src/printf.c + +# PERIPHERAL SOURCES +EMUL_SRC+=$(addprefix src/,$(addsuffix .c,$(PERIPHERALS))) +EMUL_SRC+=$(addprefix src/,$(addsuffix _csrs_pc_emul.c,$(PERIPHERALS))) + diff --git a/submodules/BOOTROM/iob_bootrom.py b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py similarity index 100% rename from submodules/BOOTROM/iob_bootrom.py rename to lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py diff --git a/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.S b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.S new file mode 100644 index 000000000..28fecfa35 --- /dev/null +++ b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.S @@ -0,0 +1,17 @@ +#include "iob_system_conf.h" +#include "iob_system_periphs.h" +#include "iob_system_system.h" + +.section .init +.globl main + + //set stack pointer + lui sp, %hi(1 << IOB_SYSTEM_MEM_ADDR_W) + addi sp, sp, %lo(1 << IOB_SYSTEM_MEM_ADDR_W) + + //call main + jal ra, main + + // Jump to the firmware + li x5, IOB_SYSTEM_FW_ADDR + jalr x0, 0(x5) diff --git a/submodules/BOOTROM/software/src/iob_soc_boot.c b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.c similarity index 81% rename from submodules/BOOTROM/software/src/iob_soc_boot.c rename to lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.c index a652b58ea..842290fd7 100644 --- a/submodules/BOOTROM/software/src/iob_soc_boot.c +++ b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.c @@ -1,7 +1,7 @@ #include "bsp.h" -#include "iob_soc_conf.h" -#include "iob_soc_periphs.h" -#include "iob_soc_system.h" +#include "iob_system_conf.h" +#include "iob_system_periphs.h" +#include "iob_system_system.h" #include "iob_uart.h" #define PROGNAME "IOb-Bootloader" @@ -21,23 +21,23 @@ int main() { uart_puts(PROGNAME); uart_puts(": connected!\n"); -#ifdef IOB_SOC_USE_EXTMEM +#ifdef IOB_SYSTEM_USE_EXTMEM uart_puts(PROGNAME); uart_puts(": DDR in use and program runs from DDR\n"); #endif // address to copy firmware to - char *prog_start_addr = (char *)IOB_SOC_FW_ADDR; + char *prog_start_addr = (char *)IOB_SYSTEM_FW_ADDR; while (uart_getc() != ACK) { uart_puts(PROGNAME); uart_puts(": Waiting for Console ACK.\n"); } -#ifndef IOB_SOC_INIT_MEM +#ifndef IOB_SYSTEM_INIT_MEM // receive firmware from host int file_size = 0; - char r_fw[] = "iob_soc_firmware.bin"; + char r_fw[] = "iob_system_firmware.bin"; file_size = uart_recvfile(r_fw, prog_start_addr); uart_puts(PROGNAME); uart_puts(": Loading firmware...\n"); diff --git a/submodules/BOOTROM/software/src/iob_soc_boot.lds b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.lds similarity index 92% rename from submodules/BOOTROM/software/src/iob_soc_boot.lds rename to lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.lds index 4dfdb41c0..036400e46 100644 --- a/submodules/BOOTROM/software/src/iob_soc_boot.lds +++ b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.lds @@ -1,6 +1,6 @@ SECTIONS { /* Program code */ - INCLUDE auto_iob_soc_boot.lds + INCLUDE auto_iob_system_boot.lds .init : { *(.init) } .text : { *(.text) } diff --git a/submodules/BOOTROM/software/src/iob_soc_preboot.S b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.S similarity index 70% rename from submodules/BOOTROM/software/src/iob_soc_preboot.S rename to lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.S index ae706832b..c1569364f 100644 --- a/submodules/BOOTROM/software/src/iob_soc_preboot.S +++ b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.S @@ -1,13 +1,13 @@ -#include "iob_soc_conf.h" -#include "iob_soc_system.h" +#include "iob_system_conf.h" +#include "iob_system_system.h" // Can't include iob_bootrom_swreg.h because the assembler doesn't recognize stdint.h, // so define the constants here instead (these are address offsets). #define IOB_BOOTROM_ROM_ADDR 0x80 -#define LENGTH ((1 << IOB_SOC_BOOTROM_ADDR_W) - IOB_BOOTROM_ROM_ADDR) +#define LENGTH ((1 << IOB_SYSTEM_BOOTROM_ADDR_W) - IOB_BOOTROM_ROM_ADDR) #define BOOTROM (BOOTROM_BASE + IOB_BOOTROM_ROM_ADDR) -#define BOOTLDR_ADDR ((1 << IOB_SOC_MEM_ADDR_W) - (1 << IOB_SOC_BOOTROM_ADDR_W)) +#define BOOTLDR_ADDR ((1 << IOB_SYSTEM_MEM_ADDR_W) - (1 << IOB_SYSTEM_BOOTROM_ADDR_W)) .section .init .globl _start diff --git a/submodules/BOOTROM/software/src/iob_soc_preboot.lds b/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.lds similarity index 100% rename from submodules/BOOTROM/software/src/iob_soc_preboot.lds rename to lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.lds diff --git a/submodules/VEXRISCV b/lib/hardware/iob_system/submodules/VEXRISCV similarity index 100% rename from submodules/VEXRISCV rename to lib/hardware/iob_system/submodules/VEXRISCV diff --git a/software/src/iob_soc_firmware.S b/software/src/iob_soc_firmware.S deleted file mode 100644 index 10eea6ccd..000000000 --- a/software/src/iob_soc_firmware.S +++ /dev/null @@ -1,17 +0,0 @@ -#include "iob_soc_conf.h" -#include "iob_soc_periphs.h" -#include "iob_soc_system.h" - -.section .init -.globl main - - //set stack pointer - lui sp, %hi(1 << IOB_SOC_FW_ADDR_W) - addi sp, sp, %lo(1 << IOB_SOC_FW_ADDR_W) - - //call main - jal ra, main - - // Jump to the pre-bootloader - li x5, 0x80000000 - jalr x0, 0(x5) diff --git a/software/sw_build.mk b/software/sw_build.mk deleted file mode 100644 index b4a642f6b..000000000 --- a/software/sw_build.mk +++ /dev/null @@ -1,81 +0,0 @@ -######################################### -# Embedded targets # -######################################### -ROOT_DIR ?=.. - -include $(ROOT_DIR)/software/auto_sw_build.mk - -# Local embedded makefile settings for custom bootloader and firmware targets. - -#Function to obtain parameter named $(1) in verilog header file located in $(2) -#Usage: $(call GET_MACRO,,) -GET_MACRO = $(shell grep "define $(1)" $(2) | rev | cut -d" " -f1 | rev) - -#Function to obtain parameter named $(1) from iob_soc_conf.vh -GET_IOB_SOC_CONF_MACRO = $(call GET_MACRO,IOB_SOC_$(1),../src/iob_soc_conf.vh) - -iob_soc_bootrom.hex: ../../software/iob_soc_preboot.bin ../../software/iob_soc_boot.bin - ../../scripts/makehex.py $^ 00000080 $(call GET_IOB_SOC_CONF_MACRO,BOOTROM_ADDR_W) > $@ - -iob_soc_firmware.hex: iob_soc_firmware.bin - ../../scripts/makehex.py $< $(call GET_IOB_SOC_CONF_MACRO,MEM_ADDR_W) > $@ - ../../scripts/hex_split.py iob_soc_firmware . - -iob_soc_firmware.bin: ../../software/iob_soc_firmware.bin - cp $< $@ - -../../software/%.bin: - make -C ../../ fw-build - -UTARGETS+=build_iob_soc_software - -TEMPLATE_LDS=src/$@.lds - -IOB_SOC_INCLUDES=-I. -Isrc -Iinclude - -IOB_SOC_LFLAGS=-Wl,-Bstatic,-T,$(TEMPLATE_LDS),--strip-debug - -# FIRMWARE SOURCES -IOB_SOC_FW_SRC=src/iob_soc_firmware.S -IOB_SOC_FW_SRC+=src/iob_soc_firmware.c -IOB_SOC_FW_SRC+=src/printf.c -# PERIPHERAL SOURCES -IOB_SOC_FW_SRC+=$(addprefix src/,$(addsuffix .c,$(PERIPHERALS))) -IOB_SOC_FW_SRC+=$(addprefix src/,$(addsuffix _csrs_emb.c,$(PERIPHERALS))) - -# BOOTLOADER SOURCES -IOB_SOC_BOOT_SRC+=src/iob_soc_boot.S -IOB_SOC_BOOT_SRC+=src/iob_soc_boot.c -IOB_SOC_BOOT_SRC+=src/iob_uart.c -IOB_SOC_BOOT_SRC+=src/iob_uart_csrs_emb.c - -# PREBOOT SOURCES -IOB_SOC_PREBOOT_SRC=src/iob_soc_preboot.S - -build_iob_soc_software: iob_soc_firmware iob_soc_boot iob_soc_preboot - -iob_soc_firmware: - make $@.elf INCLUDES="$(IOB_SOC_INCLUDES)" LFLAGS="$(IOB_SOC_LFLAGS) -Wl,-Map,$@.map" SRC="$(IOB_SOC_FW_SRC)" TEMPLATE_LDS="$(TEMPLATE_LDS)" - -iob_soc_boot: - make $@.elf INCLUDES="$(IOB_SOC_INCLUDES)" LFLAGS="$(IOB_SOC_LFLAGS) -Wl,-Map,$@.map" SRC="$(IOB_SOC_BOOT_SRC)" TEMPLATE_LDS="$(TEMPLATE_LDS)" - -iob_soc_preboot: - make $@.elf INCLUDES="$(IOB_SOC_INCLUDES)" LFLAGS="$(IOB_SOC_LFLAGS) -Wl,-Map,$@.map" SRC="$(IOB_SOC_PREBOOT_SRC)" TEMPLATE_LDS="$(TEMPLATE_LDS)" - - -.PHONY: build_iob_soc_software iob_soc_firmware iob_soc_boot - -######################################### -# PC emulation targets # -######################################### -# Local pc-emul makefile settings for custom pc emulation targets. - -# SOURCES -EMUL_SRC+=src/iob_soc_firmware.c -EMUL_SRC+=src/printf.c - -# PERIPHERAL SOURCES -EMUL_SRC+=$(addprefix src/,$(addsuffix .c,$(PERIPHERALS))) -EMUL_SRC+=$(addprefix src/,$(addsuffix _csrs_pc_emul.c,$(PERIPHERALS))) - diff --git a/submodules/BOOTROM/software/src/iob_soc_boot.S b/submodules/BOOTROM/software/src/iob_soc_boot.S deleted file mode 100644 index 360d8f73f..000000000 --- a/submodules/BOOTROM/software/src/iob_soc_boot.S +++ /dev/null @@ -1,17 +0,0 @@ -#include "iob_soc_conf.h" -#include "iob_soc_periphs.h" -#include "iob_soc_system.h" - -.section .init -.globl main - - //set stack pointer - lui sp, %hi(1 << IOB_SOC_MEM_ADDR_W) - addi sp, sp, %lo(1 << IOB_SOC_MEM_ADDR_W) - - //call main - jal ra, main - - // Jump to the firmware - li x5, IOB_SOC_FW_ADDR - jalr x0, 0(x5) From 4c054b24afe97cb2f54020ffb6a44fd9be56605a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Sun, 22 Sep 2024 17:52:08 +0100 Subject: [PATCH 04/12] fix(iob_system): Fix iob_system setup process Setup of iob_soc with iob_system as parent is working. --- iob_soc.py | 11 ++++++ .../quartus/cyclonev_gt_dk/cyclonev_gt_dk.py | 2 +- .../vivado/aes_ku040_db_g/aes_ku040_db_g.py | 2 +- .../iob_system_mwrap/iob_system_mwrap.py | 4 +- .../iob_system_sim_wrapper.py | 4 +- lib/hardware/iob_system/iob_system.py | 4 +- .../iob_system/scripts/iob_system_utils.py | 5 ++- .../submodules/BOOTROM/iob_bootrom.py | 37 +++++++++++++++++++ .../src/iob_system_boot.S | 0 .../src/iob_system_boot.c | 0 .../src/iob_system_boot.lds | 0 .../src/iob_system_preboot.S | 0 .../src/iob_system_preboot.lds | 0 lib/hardware/iob_system/submodules/VEXRISCV | 2 +- lib/scripts/default.nix | 4 +- 15 files changed, 63 insertions(+), 12 deletions(-) create mode 100644 iob_soc.py rename lib/hardware/iob_system/submodules/BOOTROM/{software => software_templates}/src/iob_system_boot.S (100%) rename lib/hardware/iob_system/submodules/BOOTROM/{software => software_templates}/src/iob_system_boot.c (100%) rename lib/hardware/iob_system/submodules/BOOTROM/{software => software_templates}/src/iob_system_boot.lds (100%) rename lib/hardware/iob_system/submodules/BOOTROM/{software => software_templates}/src/iob_system_preboot.S (100%) rename lib/hardware/iob_system/submodules/BOOTROM/{software => software_templates}/src/iob_system_preboot.lds (100%) diff --git a/iob_soc.py b/iob_soc.py new file mode 100644 index 000000000..c7ecd43fa --- /dev/null +++ b/iob_soc.py @@ -0,0 +1,11 @@ +def setup(py_params_dict): + attributes_dict = { + "original_name": "iob_soc", + "name": "iob_soc", + "parent": {"core_name": "iob_system", **py_params_dict}, + "version": "0.1", + "confs": [], + "ports": [], + } + + return attributes_dict diff --git a/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py b/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py index e53a9b15f..ba22fb200 100644 --- a/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py +++ b/lib/hardware/iob_system/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py @@ -334,7 +334,7 @@ def setup(py_params_dict): if params["init_mem"]: attributes_dict["blocks"][-1]["parameters"].update( { - "FILE": '"iob_system_firmware"', + "FILE": f'"{params["name"]}_firmware"', } ) if params["use_ethernet"]: diff --git a/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py b/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py index e953593d2..a52452fc7 100644 --- a/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py +++ b/lib/hardware/iob_system/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py @@ -359,7 +359,7 @@ def setup(py_params_dict): if params["init_mem"]: attributes_dict["blocks"][-1]["parameters"].update( { - "FILE": '"iob_system_firmware"', + "FILE": f'"{params["name"]}_firmware"', } ) if params["use_ethernet"]: diff --git a/lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py b/lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py index de964f17b..d36b38f6c 100644 --- a/lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py +++ b/lib/hardware/iob_system/hardware/modules/iob_system_mwrap/iob_system_mwrap.py @@ -10,14 +10,14 @@ def setup(py_params_dict): attributes_dict = { "original_name": "iob_system_mwrap", - "name": "iob_system_mwrap", + "name": params["name"] + "_mwrap", "version": "0.1", "confs": [ { "name": "BOOT_HEXFILE", "descr": "Bootloader file name", "type": "P", - "val": '"iob_system_bootrom"', + "val": f'"{params["name"]}_bootrom"', "min": "NA", "max": "NA", }, diff --git a/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py b/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py index eea0ce654..0b17184e0 100644 --- a/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py +++ b/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py @@ -3,7 +3,7 @@ def setup(py_params_dict): attributes_dict = { "original_name": "iob_system_sim_wrapper", - "name": "iob_system_sim_wrapper", + "name": params["name"] + "_sim_wrapper", "version": "0.1", "confs": [ { @@ -243,7 +243,7 @@ def setup(py_params_dict): if params["init_mem"]: attributes_dict["blocks"][-1]["parameters"].update( { - "FILE": '"iob_system_firmware"', + "FILE": f'"{params["name"]}_firmware"', } ) if params["use_ethernet"]: diff --git a/lib/hardware/iob_system/iob_system.py b/lib/hardware/iob_system/iob_system.py index 4f46d63c6..ff2a1e2e8 100755 --- a/lib/hardware/iob_system/iob_system.py +++ b/lib/hardware/iob_system/iob_system.py @@ -9,6 +9,7 @@ def setup(py_params_dict): params = { + "name": "iob_system", "init_mem": False, "use_extmem": False, "use_ethernet": False, @@ -24,7 +25,7 @@ def setup(py_params_dict): attributes_dict = { "original_name": "iob_system", - "name": "iob_system", + "name": params["name"], "version": "0.7", "is_system": True, "board_list": ["cyclonev_gt_dk", "aes_ku040_db_g"], @@ -348,6 +349,7 @@ def setup(py_params_dict): "ext_rom_bus": "rom_bus", }, "bootrom_addr_w": params["bootrom_addr_w"], + "soc_name": params["name"], }, { "core_name": "axi2axil", diff --git a/lib/hardware/iob_system/scripts/iob_system_utils.py b/lib/hardware/iob_system/scripts/iob_system_utils.py index a11f3433f..690a22bf4 100644 --- a/lib/hardware/iob_system/scripts/iob_system_utils.py +++ b/lib/hardware/iob_system/scripts/iob_system_utils.py @@ -180,6 +180,7 @@ def generate_makefile_segments(attributes_dict, peripherals, params, py_params): :param dict params: iob_system python parameters :param dict py_params: iob_system argument python parameters """ + name = attributes_dict["name"] build_dir = attributes_dict["build_dir"] # Don't create files for other targets (like clean) @@ -250,11 +251,11 @@ def generate_makefile_segments(attributes_dict, peripherals, params, py_params): # Create auto_iob_system_boot.lds and auto_iob_system_firmware.lds # os.makedirs(f"{build_dir}/software", exist_ok=True) - with open(f"{build_dir}/software/auto_iob_system_boot.lds", "w") as file: + with open(f"{build_dir}/software/auto_{name}_boot.lds", "w") as file: file.write("/* This file was auto generated by iob_system_utils.py */\n") file.write( f". = {hex((1 << params['mem_addr_w']) - (1 << params['bootrom_addr_w']))};\n" ) - with open(f"{build_dir}/software/auto_iob_system_firmware.lds", "w") as file: + with open(f"{build_dir}/software/auto_{name}_firmware.lds", "w") as file: file.write("/* This file was auto generated by iob_system_utils.py */\n") file.write(f". = {params['fw_addr']};\n") diff --git a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py index efd3cdb23..383550c75 100644 --- a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py +++ b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py @@ -1,3 +1,8 @@ +import os +import sys +import shutil + + def setup(py_params_dict): VERSION = "0.1" BOOTROM_ADDR_W = ( @@ -207,4 +212,36 @@ def setup(py_params_dict): ], } + copy_sw_srcs_with_rename(py_params_dict) + return attributes_dict + + +def copy_sw_srcs_with_rename(py_params): + """Copy software sources, and rename them based on correct SoC name.""" + SOC_NAME = py_params.get("soc_name", "iob_system") + + # Don't create files for other targets (like clean) + if py_params.get("py2hwsw_target") != "setup": + return + + SRC_DIR = os.path.join(os.path.dirname(__file__), "software_templates/src") + DEST_DIR = os.path.join(py_params.get("build_dir"), "software/src") + os.makedirs(DEST_DIR, exist_ok=True) + + for filename in os.listdir(SRC_DIR): + new_filename = filename.replace("iob_system", SOC_NAME) + src = os.path.join(SRC_DIR, filename) + dst = os.path.join(DEST_DIR, new_filename) + + # Read file, replace strings with SoC name, and write new file + with open(src, "r") as file: + lines = file.readlines() + for idx in range(len(lines)): + lines[idx] = ( + lines[idx] + .replace("iob_system", SOC_NAME) + .replace("iob_system".upper(), SOC_NAME.upper()) + ) + with open(dst, "w") as file: + file.writelines(lines) diff --git a/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.S b/lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_boot.S similarity index 100% rename from lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.S rename to lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_boot.S diff --git a/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.c b/lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_boot.c similarity index 100% rename from lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.c rename to lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_boot.c diff --git a/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.lds b/lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_boot.lds similarity index 100% rename from lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_boot.lds rename to lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_boot.lds diff --git a/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.S b/lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_preboot.S similarity index 100% rename from lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.S rename to lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_preboot.S diff --git a/lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.lds b/lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_preboot.lds similarity index 100% rename from lib/hardware/iob_system/submodules/BOOTROM/software/src/iob_system_preboot.lds rename to lib/hardware/iob_system/submodules/BOOTROM/software_templates/src/iob_system_preboot.lds diff --git a/lib/hardware/iob_system/submodules/VEXRISCV b/lib/hardware/iob_system/submodules/VEXRISCV index da8b3fda9..67b1f13a4 160000 --- a/lib/hardware/iob_system/submodules/VEXRISCV +++ b/lib/hardware/iob_system/submodules/VEXRISCV @@ -1 +1 @@ -Subproject commit da8b3fda97efd749c39e214453a59a28228dfabc +Subproject commit 67b1f13a44c26198b9fd21db4ec07b90ed947bcb diff --git a/lib/scripts/default.nix b/lib/scripts/default.nix index c622abca2..424b50712 100644 --- a/lib/scripts/default.nix +++ b/lib/scripts/default.nix @@ -1,8 +1,8 @@ { pkgs ? import {} }: let - py2hwsw_commit = "4d51b94283522d53f1c3c293efda1fc9c180ae3d"; # Replace with the desired commit. - py2hwsw_sha256 = "X5jjz014jxpOh0rK7rOrvpTIvIcdX2QgU6JEaKjWTsI="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "6a26dfded288503342845fa421d3d1ee6bce021b"; # Replace with the desired commit. + py2hwsw_sha256 = "bsRLE+dLj7Msnret3CEI7cwK8VGIftaepZ7tSpAsVg0="; # Replace with the actual SHA256 hash. py2hwsw = pkgs.python3.pkgs.buildPythonPackage rec { pname = "py2hwsw"; From 0c5a0eb4dd25a679020c1976b4ff108224420d87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Mon, 30 Sep 2024 16:56:58 +0100 Subject: [PATCH 05/12] feat(bit slice): Resolve some warnings with new bit slice feature of py2hwsw. --- lib/hardware/iob_system/iob_system.py | 34 +++++++++++++++++++++++---- lib/scripts/default.nix | 4 ++-- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/lib/hardware/iob_system/iob_system.py b/lib/hardware/iob_system/iob_system.py index 434ee4375..006818ae1 100755 --- a/lib/hardware/iob_system/iob_system.py +++ b/lib/hardware/iob_system/iob_system.py @@ -300,11 +300,31 @@ def setup(py_params_dict): "connect": { "clk_en_rst_s": "clk_en_rst_s", "rst_i": "rst", - "i_bus_m": "cpu_ibus", - "d_bus_m": "cpu_dbus", + "i_bus_m": ( + "cpu_ibus", + "cpu_i_axi_arid[0]", + "cpu_i_axi_rid[0]", + "cpu_i_axi_awid[0]", + "cpu_i_axi_bid[0]", + ), + "d_bus_m": ( + "cpu_dbus", + "cpu_d_axi_arid[0]", + "cpu_d_axi_rid[0]", + "cpu_d_axi_awid[0]", + "cpu_d_axi_bid[0]", + ), "plic_interrupts_i": "interrupts", - "plic_cbus_s": "plic_cbus", - "clint_cbus_s": "clint_cbus", + "plic_cbus_s": ( + "plic_cbus", + "plic_cbus_axil_araddr[22-1:0]", + "plic_cbus_axil_awaddr[22-1:0]", + ), + "clint_cbus_s": ( + "clint_cbus", + "clint_cbus_axil_araddr[16-1:0]", + "clint_cbus_axil_awaddr[16-1:0]", + ), }, }, { @@ -322,7 +342,11 @@ def setup(py_params_dict): "rst_i": "rst", "s0_axi_s": "cpu_ibus", "s1_axi_s": "cpu_dbus", - "mem_axi_m": "axi_m", + "mem_axi_m": ( + "axi_m", + "axi_arlock[0]", + "axi_awlock[0]", + ), "bootrom_axi_m": "bootrom_cbus", "peripherals_axi_m": "axi_periphs_cbus", }, diff --git a/lib/scripts/default.nix b/lib/scripts/default.nix index 997b9bfc6..8cf7ba50a 100644 --- a/lib/scripts/default.nix +++ b/lib/scripts/default.nix @@ -1,8 +1,8 @@ { pkgs ? import {} }: let - py2hwsw_commit = "8bb5b4f96839394bfa2ed0f900f5e2704dccda24"; # Replace with the desired commit. - py2hwsw_sha256 = "SrWJMPLSQNKkYdldldTF1Xhb83XEd6mIcMCxhqi0L/8="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "33c7c86d48b0107f98c2fef8b7f63f8a8ee9b42f"; # Replace with the desired commit. + py2hwsw_sha256 = "X9feysT2sg2fSWVFg4U8QdD92BGXNEXM+MOO9xzgp1c="; # Replace with the actual SHA256 hash. py2hwsw = pkgs.python3.pkgs.buildPythonPackage rec { pname = "py2hwsw"; From 26dc8c998665842eec2bdc5a28730498c5132a3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 1 Oct 2024 04:27:47 +0100 Subject: [PATCH 06/12] feat(cbus): Replace axil peripheral cbus interfaces by iob interfaces. Fix some verilog warnings with bit slicing. Fix lib modules. --- lib/hardware/buses/iob2axil/iob2axil.py | 56 +++++++++++++++++++ lib/hardware/buses/iob_split/iob_split.py | 2 +- lib/hardware/iob_system/iob_system.py | 39 +++++++------ .../iob_system/scripts/iob_system_utils.py | 17 ++---- .../submodules/BOOTROM/iob_bootrom.py | 1 + lib/hardware/iob_system/submodules/VEXRISCV | 2 +- lib/hardware/iob_timer/iob_timer.py | 4 +- lib/hardware/iob_uart/iob_uart.py | 2 +- 8 files changed, 87 insertions(+), 36 deletions(-) diff --git a/lib/hardware/buses/iob2axil/iob2axil.py b/lib/hardware/buses/iob2axil/iob2axil.py index 55645da65..94790da52 100644 --- a/lib/hardware/buses/iob2axil/iob2axil.py +++ b/lib/hardware/buses/iob2axil/iob2axil.py @@ -4,6 +4,62 @@ def setup(py_params_dict): "name": "iob2axil", "version": "0.1", "generate_hw": False, + "confs": [ + { + "name": "AXIL_ADDR_W", + "descr": "", + "type": "P", + "val": "21", + "min": "1", + "max": "32", + }, + { + "name": "AXIL_DATA_W", + "descr": "", + "type": "P", + "val": "21", + "min": "1", + "max": "32", + }, + { + "name": "ADDR_W", + "descr": "", + "type": "P", + "val": "21", + "min": "1", + "max": "32", + }, + { + "name": "DATA_W", + "descr": "", + "type": "P", + "val": "21", + "min": "1", + "max": "32", + }, + ], + "ports": [ + { + "name": "iob_s", + "descr": "Slave IOb interface", + "interface": { + "type": "iob", + "subtype": "slave", + "ADDR_W": "ADDR_W", + "DATA_W": "DATA_W", + }, + }, + { + "name": "axil_m", + "descr": "Master AXI Lite interface", + "interface": { + "type": "axil", + "subtype": "master", + "ADDR_W": "AXIL_ADDR_W", + "DATA_W": "AXIL_DATA_W", + }, + }, + ], } return attributes_dict diff --git a/lib/hardware/buses/iob_split/iob_split.py b/lib/hardware/buses/iob_split/iob_split.py index c6a2f60e3..112b997e4 100644 --- a/lib/hardware/buses/iob_split/iob_split.py +++ b/lib/hardware/buses/iob_split/iob_split.py @@ -215,7 +215,7 @@ def setup(py_params_dict): }, "connect": { "clk_en_rst_s": "clk_en_rst_s", - "en_rst_s": "sel_reg_en_rst", + "en_rst_i": "sel_reg_en_rst", "data_i": "sel_reg_data_i", "data_o": "sel_reg_data_o", }, diff --git a/lib/hardware/iob_system/iob_system.py b/lib/hardware/iob_system/iob_system.py index 006818ae1..db687a6c2 100755 --- a/lib/hardware/iob_system/iob_system.py +++ b/lib/hardware/iob_system/iob_system.py @@ -257,6 +257,7 @@ def setup(py_params_dict): "ADDR_W": params["addr_w"] - 2, "DATA_W": "AXI_DATA_W", "LEN_W": "AXI_LEN_W", + "LOCK_W": "1", }, }, { @@ -272,10 +273,10 @@ def setup(py_params_dict): }, }, { - "name": "axil_periphs_cbus", + "name": "iob_periphs_cbus", "descr": "AXI-Lite bus for peripheral CSRs", "interface": { - "type": "axil", + "type": "iob", "wire_prefix": "periphs_", "ID_W": "AXI_ID_W", "ADDR_W": params["addr_w"] - 1, @@ -317,13 +318,11 @@ def setup(py_params_dict): "plic_interrupts_i": "interrupts", "plic_cbus_s": ( "plic_cbus", - "plic_cbus_axil_araddr[22-1:0]", - "plic_cbus_axil_awaddr[22-1:0]", + "plic_cbus_iob_addr[22-1:0]", ), "clint_cbus_s": ( "clint_cbus", - "clint_cbus_axil_araddr[16-1:0]", - "clint_cbus_axil_awaddr[16-1:0]", + "clint_cbus_iob_addr[16-1:0]", ), }, }, @@ -348,7 +347,11 @@ def setup(py_params_dict): "axi_awlock[0]", ), "bootrom_axi_m": "bootrom_cbus", - "peripherals_axi_m": "axi_periphs_cbus", + "peripherals_axi_m": ( + "axi_periphs_cbus", + "periphs_axi_awlock[0]", + "periphs_axi_arlock[0]", + ), }, "num_slaves": 2, "masters": { @@ -376,29 +379,29 @@ def setup(py_params_dict): "soc_name": params["name"], }, { - "core_name": "axi2axil", - "instance_name": "periphs_axi2axil", + "core_name": "axi2iob", + "instance_name": "periphs_axi2iob", "instance_description": "Convert AXI to AXI lite for CLINT", "parameters": { - "AXI_ID_W": "AXI_ID_W", - "AXI_ADDR_W": params["addr_w"] - 1, - "AXI_DATA_W": "AXI_DATA_W", - "AXI_LEN_W": "AXI_LEN_W", + "AXI_ID_WIDTH": "AXI_ID_W", + "ADDR_WIDTH": params["addr_w"] - 1, + "DATA_WIDTH": "AXI_DATA_W", }, "connect": { + "clk_en_rst_s": "clk_en_rst_s", "axi_s": "axi_periphs_cbus", - "axil_m": "axil_periphs_cbus", + "iob_m": "iob_periphs_cbus", }, }, { - "core_name": "iob_axil_split", - "name": "iob_axil_pbus_split", - "instance_name": "iob_axil_pbus_split", + "core_name": "iob_split", + "name": "iob_pbus_split", + "instance_name": "iob_pbus_split", "instance_description": "Split between peripherals", "connect": { "clk_en_rst_s": "clk_en_rst_s", "reset_i": "split_reset", - "input_s": "axil_periphs_cbus", + "input_s": "iob_periphs_cbus", # Peripherals cbus connections added automatically }, "num_outputs": 0, # Num outputs configured automatically diff --git a/lib/hardware/iob_system/scripts/iob_system_utils.py b/lib/hardware/iob_system/scripts/iob_system_utils.py index e5ae09f43..c89c76be2 100644 --- a/lib/hardware/iob_system/scripts/iob_system_utils.py +++ b/lib/hardware/iob_system/scripts/iob_system_utils.py @@ -72,7 +72,7 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params): # Find pbus_split pbus_split = None for block in attributes_dict["blocks"]: - if block["instance_name"] == "iob_axil_pbus_split": + if block["instance_name"] == "iob_pbus_split": pbus_split = block # Number of peripherals = peripherals + CLINT + PLIC @@ -90,12 +90,9 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params): "name": f"{peripheral_name}_cbus", "descr": f"{peripheral_name} Control/Status Registers bus", "interface": { - "type": "axil", + "type": "iob", "wire_prefix": f"{peripheral_name}_cbus_", - "ID_W": "AXI_ID_W", "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", }, }, ) @@ -110,24 +107,18 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params): "name": "clint_cbus", "descr": "CLINT Control/Status Registers bus", "interface": { - "type": "axil", + "type": "iob", "wire_prefix": "clint_cbus_", - "ID_W": "AXI_ID_W", "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", }, }, { "name": "plic_cbus", "descr": "PLIC Control/Status Registers bus", "interface": { - "type": "axil", + "type": "iob", "wire_prefix": "plic_cbus_", - "ID_W": "AXI_ID_W", "ADDR_W": peripheral_addr_w, - "DATA_W": "AXI_DATA_W", - "LEN_W": "AXI_LEN_W", }, }, ] diff --git a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py index b343b59fa..861bcd814 100644 --- a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py +++ b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py @@ -84,6 +84,7 @@ def setup(py_params_dict): "port_prefix": "cbus_", "ADDR_W": BOOTROM_ADDR_W, "DATA_W": "DATA_W", + "LOCK_W": "1", }, }, { diff --git a/lib/hardware/iob_system/submodules/VEXRISCV b/lib/hardware/iob_system/submodules/VEXRISCV index 213a9a957..4466e1e60 160000 --- a/lib/hardware/iob_system/submodules/VEXRISCV +++ b/lib/hardware/iob_system/submodules/VEXRISCV @@ -1 +1 @@ -Subproject commit 213a9a95789a8d4e6d17c44e3044ec7d8288883f +Subproject commit 4466e1e6042b656c6eeaf6b4bbb6096b30577b04 diff --git a/lib/hardware/iob_timer/iob_timer.py b/lib/hardware/iob_timer/iob_timer.py index 011e6e0bb..b16556fd8 100755 --- a/lib/hardware/iob_timer/iob_timer.py +++ b/lib/hardware/iob_timer/iob_timer.py @@ -41,7 +41,7 @@ def setup(py_params_dict): { "name": "cbus_s", "interface": { - "type": "axil", + "type": "iob", "subtype": "slave", "ADDR_W": "4", # Same as `IOB_TIMER_CSRS_ADDR_W "DATA_W": "DATA_W", @@ -174,7 +174,7 @@ def setup(py_params_dict): ], }, ], - "csr_if": "axil", + "csr_if": "iob", "connect": { "clk_en_rst_s": "clk_en_rst_s", "control_if_s": "cbus_s", diff --git a/lib/hardware/iob_uart/iob_uart.py b/lib/hardware/iob_uart/iob_uart.py index 5075af0c3..7bafedd17 100755 --- a/lib/hardware/iob_uart/iob_uart.py +++ b/lib/hardware/iob_uart/iob_uart.py @@ -1,5 +1,5 @@ def setup(py_params_dict): - CSR_IF = py_params_dict["csr_if"] if "csr_if" in py_params_dict else "axil" + CSR_IF = py_params_dict["csr_if"] if "csr_if" in py_params_dict else "iob" NAME = py_params_dict["name"] if "name" in py_params_dict else "iob_uart" attributes_dict = { "original_name": "iob_uart", From 48d768ecf07ab8f521ca1e0dfcd5a9067fa31001 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 1 Oct 2024 14:24:09 +0100 Subject: [PATCH 07/12] feat(iob_soc): Add example custom firmware Add iob_soc_firmware.c as an example custom firmware to override default one from iob_system. This custom firmware prints "Hello world from IOb-SoC!" --- software/src/iob_soc_firmware.c | 66 +++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 software/src/iob_soc_firmware.c diff --git a/software/src/iob_soc_firmware.c b/software/src/iob_soc_firmware.c new file mode 100644 index 000000000..639c59633 --- /dev/null +++ b/software/src/iob_soc_firmware.c @@ -0,0 +1,66 @@ +#include "bsp.h" +#include "iob_soc_conf.h" +#include "iob_soc_periphs.h" +#include "iob_soc_system.h" +#include "iob_timer.h" +#include "iob_uart.h" +#include "printf.h" +#include + +char *send_string = "Sending this string as a file to console.\n" + "The file is then requested back from console.\n" + "The sent file is compared to the received file to confirm " + "correct file transfer via UART using console.\n" + "Generating the file in the firmware creates an uniform " + "file transfer between pc-emul, simulation and fpga without" + " adding extra targets for file generation.\n"; + +int main() { + char pass_string[] = "Test passed!"; + char fail_string[] = "Test failed!"; + + // init timer + timer_init(TIMER0_BASE); + + // init uart + uart_init(UART0_BASE, FREQ / BAUD); + printf_init(&uart_putc); + + // test puts + uart_puts("\n\n\nHello world from IOb-SoC!\n\n\n"); + + // test printf with floats + printf("Value of Pi = %f\n\n", 3.1415); + + // test file send + char *sendfile = malloc(1000); + int send_file_size = 0; + send_file_size = strlen(strcpy(sendfile, send_string)); + uart_sendfile("Sendfile.txt", send_file_size, sendfile); + + // test file receive + char *recvfile = malloc(10000); + int file_size = 0; + file_size = uart_recvfile("Sendfile.txt", recvfile); + + // compare files + if (strcmp(sendfile, recvfile)) { + printf("FAILURE: Send and received file differ!\n"); + } else { + printf("SUCCESS: Send and received file match!\n"); + } + + free(sendfile); + free(recvfile); + + uart_sendfile("test.log", strlen(pass_string), pass_string); + + // read current timer count, compute elapsed time + unsigned long long elapsed = timer_get_count(); + unsigned int elapsedu = elapsed / (FREQ / 1000000); + + printf("\nExecution time: %d clock cycles\n", (unsigned int)elapsed); + printf("\nExecution time: %dus @%dMHz\n\n", elapsedu, FREQ / 1000000); + + uart_finish(); +} From baaf041273b96180155d33b526e53a4b0c5c3b02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Tue, 1 Oct 2024 17:52:52 +0100 Subject: [PATCH 08/12] feat(iob-soc): Add uart and timer blocks. These override ones from iob_system. TODO: Find a way of automating cbus connections of child module (iob-soc). These connections are normally automated by iob-system utils, but those scripts don't have access to the child module attributes. --- iob_soc.py | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/iob_soc.py b/iob_soc.py index c7ecd43fa..7fa05adde 100644 --- a/iob_soc.py +++ b/iob_soc.py @@ -4,8 +4,45 @@ def setup(py_params_dict): "name": "iob_soc", "parent": {"core_name": "iob_system", **py_params_dict}, "version": "0.1", - "confs": [], - "ports": [], + "ports": [ + { + "name": "rs232_m", + "descr": "iob-system uart interface", + "interface": { + "type": "rs232", + }, + }, + ], + "blocks": [ + { + "core_name": "iob_uart", + "instance_name": "UART0", + "instance_description": "UART peripheral", + "is_peripheral": True, + "parameters": {}, + "connect": { + "clk_en_rst_s": "clk_en_rst_s", + # TODO: Cbus should be connected automatically + # The iob_system blocks are handled by iob_system_utils.py, but + # the iob_system scripts do not have access to info in iob_soc.py, + # nor do they have permission to modify it (even if iob_system receives info about child module, it can't modify its dictionary). + "cbus_s": "uart0_cbus", + "rs232_m": "rs232_m", + }, + }, + { + "core_name": "iob_timer", + "instance_name": "TIMER0", + "instance_description": "Timer peripheral", + "is_peripheral": True, + "parameters": {}, + "connect": { + "clk_en_rst_s": "clk_en_rst_s", + # TODO: Cbus should be connected automatically + "cbus_s": "timer0_cbus", + }, + }, + ], } return attributes_dict From 1bf5c46c96b1897f63f8da0d370661efc815565a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 2 Oct 2024 05:49:30 +0100 Subject: [PATCH 09/12] fix(ci): Increase lib test timout to 20 min Increase timeout to allow iob_system module test to run. Update py2hwsw. --- .github/workflows/ci.yml | 2 +- lib/scripts/default.nix | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 505d74fb9..371ef51ba 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -86,7 +86,7 @@ jobs: lib: runs-on: self-hosted - timeout-minutes: 10 + timeout-minutes: 20 if: ${{ !cancelled() }} needs: [ cyclonev ] diff --git a/lib/scripts/default.nix b/lib/scripts/default.nix index 8cf7ba50a..dfb7355cf 100644 --- a/lib/scripts/default.nix +++ b/lib/scripts/default.nix @@ -1,8 +1,8 @@ { pkgs ? import {} }: let - py2hwsw_commit = "33c7c86d48b0107f98c2fef8b7f63f8a8ee9b42f"; # Replace with the desired commit. - py2hwsw_sha256 = "X9feysT2sg2fSWVFg4U8QdD92BGXNEXM+MOO9xzgp1c="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "b4b6f5bf0fd854b74898a33a6eb44ccbf1bea848"; # Replace with the desired commit. + py2hwsw_sha256 = "6ELPTWjtctNODCcWt4zp8Um0XmRA+NT+Mh6bcHAwoI8="; # Replace with the actual SHA256 hash. py2hwsw = pkgs.python3.pkgs.buildPythonPackage rec { pname = "py2hwsw"; From cfd427d71c9eca99c62f4dd7eb8fd61a29cedd76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 2 Oct 2024 15:08:43 +0100 Subject: [PATCH 10/12] fix(warnings): Fix verilog warnings; Update py2hwsw. --- .../iob_system_sim_wrapper.py | 14 ++++++++++-- lib/hardware/iob_system/iob_system.py | 22 +++++++++++++++---- .../submodules/BOOTROM/iob_bootrom.py | 7 +++--- lib/scripts/default.nix | 4 ++-- 4 files changed, 36 insertions(+), 11 deletions(-) diff --git a/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py b/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py index e9d33791a..597bac82f 100644 --- a/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py +++ b/lib/hardware/iob_system/hardware/modules/iob_system_sim_wrapper/iob_system_sim_wrapper.py @@ -106,6 +106,7 @@ def setup(py_params_dict): "ADDR_W": "AXI_ADDR_W", "DATA_W": "AXI_DATA_W", "LEN_W": "AXI_LEN_W", + "LOCK_W": "AXI_LEN_W", }, }, { @@ -132,6 +133,7 @@ def setup(py_params_dict): "ADDR_W": "AXI_ADDR_W", "DATA_W": "AXI_DATA_W", "LEN_W": "AXI_LEN_W", + "LOCK_W": "1", }, }, ] @@ -218,7 +220,11 @@ def setup(py_params_dict): "connect": { "clk_i": "clk", "rst_i": "rst", - "s0_axi_s": "axi", + "s0_axi_s": ( + "axi", + "axi_awlock[0]", + "axi_arlock[0]", + ), "m0_axi_m": "memory_axi", }, "num_slaves": 1, @@ -236,7 +242,11 @@ def setup(py_params_dict): "connect": { "clk_i": "clk", "rst_i": "rst", - "axi_s": "memory_axi", + "axi_s": ( + "memory_axi", + "{1'b0, mem_axi_arlock}", + "{1'b0, mem_axi_awlock}", + ), }, }, ] diff --git a/lib/hardware/iob_system/iob_system.py b/lib/hardware/iob_system/iob_system.py index db687a6c2..103551ef5 100755 --- a/lib/hardware/iob_system/iob_system.py +++ b/lib/hardware/iob_system/iob_system.py @@ -343,8 +343,8 @@ def setup(py_params_dict): "s1_axi_s": "cpu_dbus", "mem_axi_m": ( "axi_m", - "axi_arlock[0]", - "axi_awlock[0]", + "axi_arlock_o[0]", + "axi_awlock_o[0]", ), "bootrom_axi_m": "bootrom_cbus", "peripherals_axi_m": ( @@ -372,7 +372,17 @@ def setup(py_params_dict): }, "connect": { "clk_en_rst_s": "clk_en_rst_s", - "cbus_s": "bootrom_cbus", + "cbus_s": ( + "bootrom_cbus", + "bootrom_axi_araddr[13-1:0]", + "bootrom_axi_arid[0]", + "bootrom_axi_rid[0]", + "{1'b0, bootrom_axi_arlock}", + "bootrom_axi_awaddr[13-1:0]", + "bootrom_axi_awid[0]", + "bootrom_axi_bid[0]", + "{1'b0, bootrom_axi_awlock}", + ), "ext_rom_bus": "rom_bus", }, "bootrom_addr_w": params["bootrom_addr_w"], @@ -389,7 +399,11 @@ def setup(py_params_dict): }, "connect": { "clk_en_rst_s": "clk_en_rst_s", - "axi_s": "axi_periphs_cbus", + "axi_s": ( + "axi_periphs_cbus", + "periphs_axi_arlock[0]", + "periphs_axi_awlock[0]", + ), "iob_m": "iob_periphs_cbus", }, }, diff --git a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py index 861bcd814..d7f0166ad 100644 --- a/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py +++ b/lib/hardware/iob_system/submodules/BOOTROM/iob_bootrom.py @@ -82,9 +82,9 @@ def setup(py_params_dict): "type": "axi", "subtype": "slave", "port_prefix": "cbus_", - "ADDR_W": BOOTROM_ADDR_W, + # BOOTROM_ADDR_W + 1 for remaining csrs ("VERSION" csr) + "ADDR_W": BOOTROM_ADDR_W + 1, "DATA_W": "DATA_W", - "LOCK_W": "1", }, }, { @@ -119,7 +119,8 @@ def setup(py_params_dict): "interface": { "type": "iob", "wire_prefix": "csrs_", - "ADDR_W": BOOTROM_ADDR_W, + # BOOTROM_ADDR_W + 1 for remaining csrs ("VERSION" csr) + "ADDR_W": BOOTROM_ADDR_W + 1, "DATA_W": "DATA_W", }, }, diff --git a/lib/scripts/default.nix b/lib/scripts/default.nix index dfb7355cf..0f6db7df4 100644 --- a/lib/scripts/default.nix +++ b/lib/scripts/default.nix @@ -1,8 +1,8 @@ { pkgs ? import {} }: let - py2hwsw_commit = "b4b6f5bf0fd854b74898a33a6eb44ccbf1bea848"; # Replace with the desired commit. - py2hwsw_sha256 = "6ELPTWjtctNODCcWt4zp8Um0XmRA+NT+Mh6bcHAwoI8="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "8abbad6b93b9cfcca4fb97bdd4d09cadf8cadbe2"; # Replace with the desired commit. + py2hwsw_sha256 = "NIxU15GH3YtFYeYW1bfZJgobEs0Bk25yU7pNiXnE/IA="; # Replace with the actual SHA256 hash. py2hwsw = pkgs.python3.pkgs.buildPythonPackage rec { pname = "py2hwsw"; From 9cc6e2752eb903c82aeca45d8c171a8f9a814e0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 2 Oct 2024 16:16:55 +0100 Subject: [PATCH 11/12] fix(cbus): Fix cbus width verilog warnings Pass ADDR_W to peripherals matching output of pbus split. This fixes cbus verilog warnings. Also update peripherals to support ADDR_W and ignore unused bits. --- iob_soc.py | 8 ++++++-- lib/hardware/clocks_resets/iob_nco/iob_nco.py | 11 +++++++---- .../iob_system/scripts/iob_system_utils.py | 2 ++ lib/hardware/iob_timer/iob_timer.py | 9 ++++++--- lib/hardware/iob_uart/iob_uart.py | 17 ++++++++++++++--- 5 files changed, 35 insertions(+), 12 deletions(-) diff --git a/iob_soc.py b/iob_soc.py index 7fa05adde..c50a4c978 100644 --- a/iob_soc.py +++ b/iob_soc.py @@ -19,7 +19,9 @@ def setup(py_params_dict): "instance_name": "UART0", "instance_description": "UART peripheral", "is_peripheral": True, - "parameters": {}, + "parameters": { + "ADDR_W": "29", # TODO: Automate this with iob_system scripts + }, "connect": { "clk_en_rst_s": "clk_en_rst_s", # TODO: Cbus should be connected automatically @@ -35,7 +37,9 @@ def setup(py_params_dict): "instance_name": "TIMER0", "instance_description": "Timer peripheral", "is_peripheral": True, - "parameters": {}, + "parameters": { + "ADDR_W": "29", # TODO: Automate this with iob_system scripts + }, "connect": { "clk_en_rst_s": "clk_en_rst_s", # TODO: Cbus should be connected automatically diff --git a/lib/hardware/clocks_resets/iob_nco/iob_nco.py b/lib/hardware/clocks_resets/iob_nco/iob_nco.py index 1a2366b4b..9bc305da3 100644 --- a/lib/hardware/clocks_resets/iob_nco/iob_nco.py +++ b/lib/hardware/clocks_resets/iob_nco/iob_nco.py @@ -39,11 +39,11 @@ def setup(py_params_dict): "descr": "clock, clock enable and reset", }, { - "name": "iob_s", + "name": "cbus_s", "interface": { "type": "iob", "subtype": "slave", - "ADDR_W": "4", # Same as `IOB_NCO_CSRS_ADDR_W + "ADDR_W": "ADDR_W", "DATA_W": "DATA_W", }, "descr": "CPU native interface", @@ -80,7 +80,7 @@ def setup(py_params_dict): "interface": { "type": "iob", "wire_prefix": "csrs_", - "ADDR_W": "ADDR_W", + "ADDR_W": "4", "DATA_W": "DATA_W", }, }, @@ -311,7 +311,10 @@ def setup(py_params_dict): ], "connect": { "clk_en_rst_s": "clk_en_rst_s", - "control_if_s": "iob_s", + "control_if_s": ( + "cbus_s", + "iob_addr_i[4-1:0]", + ), "csrs_iob_o": "csrs_iob", # Register interfaces "softreset": "softreset", diff --git a/lib/hardware/iob_system/scripts/iob_system_utils.py b/lib/hardware/iob_system/scripts/iob_system_utils.py index c89c76be2..5fbc913d4 100644 --- a/lib/hardware/iob_system/scripts/iob_system_utils.py +++ b/lib/hardware/iob_system/scripts/iob_system_utils.py @@ -100,6 +100,8 @@ def connect_peripherals_cbus(attributes_dict, peripherals, params): pbus_split["connect"][f"output_{idx}_m"] = f"{peripheral_name}_cbus" # Connect cbus to peripheral peripheral["connect"]["cbus_s"] = f"{peripheral_name}_cbus" + # Set address width parameter + peripheral["parameters"]["ADDR_W"] = peripheral_addr_w # Add CLINT and PLIC wires (they are not in peripherals list) attributes_dict["wires"] += [ diff --git a/lib/hardware/iob_timer/iob_timer.py b/lib/hardware/iob_timer/iob_timer.py index b16556fd8..c192b1be8 100755 --- a/lib/hardware/iob_timer/iob_timer.py +++ b/lib/hardware/iob_timer/iob_timer.py @@ -43,7 +43,7 @@ def setup(py_params_dict): "interface": { "type": "iob", "subtype": "slave", - "ADDR_W": "4", # Same as `IOB_TIMER_CSRS_ADDR_W + "ADDR_W": "ADDR_W", "DATA_W": "DATA_W", }, "descr": "CPU native interface", @@ -56,7 +56,7 @@ def setup(py_params_dict): "interface": { "type": "iob", "wire_prefix": "csrs_", - "ADDR_W": "ADDR_W", + "ADDR_W": "4", "DATA_W": "DATA_W", }, }, @@ -177,7 +177,10 @@ def setup(py_params_dict): "csr_if": "iob", "connect": { "clk_en_rst_s": "clk_en_rst_s", - "control_if_s": "cbus_s", + "control_if_s": ( + "cbus_s", + "iob_addr_i[4-1:0]", + ), "csrs_iob_o": "csrs_iob", # Register interfaces "reset": "reset", diff --git a/lib/hardware/iob_uart/iob_uart.py b/lib/hardware/iob_uart/iob_uart.py index 7bafedd17..8d2736775 100755 --- a/lib/hardware/iob_uart/iob_uart.py +++ b/lib/hardware/iob_uart/iob_uart.py @@ -1,6 +1,17 @@ def setup(py_params_dict): CSR_IF = py_params_dict["csr_if"] if "csr_if" in py_params_dict else "iob" NAME = py_params_dict["name"] if "name" in py_params_dict else "iob_uart" + + if CSR_IF == "iob": + cbus_widths = ["iob_addr_i[3-1:0]"] + elif CSR_IF == "axi": + cbus_widths = [ + "axi_araddr_i[3-1:0]", + "axi_awaddr_i[3-1:0]", + ] + else: + cbus_widths = [] + attributes_dict = { "original_name": "iob_uart", "name": NAME, @@ -46,7 +57,7 @@ def setup(py_params_dict): "interface": { "type": CSR_IF, "subtype": "slave", - "ADDR_W": "3", # Same as `IOB_UART_CSRS_ADDR_W + "ADDR_W": "ADDR_W", "DATA_W": "DATA_W", }, "descr": "CPU native interface", @@ -66,7 +77,7 @@ def setup(py_params_dict): "interface": { "type": "iob", "wire_prefix": "csrs_", - "ADDR_W": "ADDR_W", + "ADDR_W": "3", "DATA_W": "DATA_W", }, }, @@ -272,7 +283,7 @@ def setup(py_params_dict): "csr_if": CSR_IF, "connect": { "clk_en_rst_s": "clk_en_rst_s", - "control_if_s": "cbus_s", + "control_if_s": ("cbus_s", *cbus_widths), "csrs_iob_o": "csrs_iob", # Register interfaces "softreset": "softreset", From 5569a5949b8aac24a329d4aef5bf86fb22dec776 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 2 Oct 2024 16:40:21 +0100 Subject: [PATCH 12/12] feat(iob_system): Set init_mem to True by default. This allows lib ghactions test to run faster. --- lib/hardware/iob_system/iob_system.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/hardware/iob_system/iob_system.py b/lib/hardware/iob_system/iob_system.py index 103551ef5..ac5836b02 100755 --- a/lib/hardware/iob_system/iob_system.py +++ b/lib/hardware/iob_system/iob_system.py @@ -10,7 +10,7 @@ def setup(py_params_dict): params = { "name": "iob_system", - "init_mem": False, + "init_mem": True, "use_extmem": False, "use_ethernet": False, "addr_w": 32,