From 7b3dcb466216ff2aea4211a0addf34dbf5f85006 Mon Sep 17 00:00:00 2001 From: Martim Esteves Date: Mon, 2 Sep 2024 16:43:41 +0100 Subject: [PATCH] module iob_ram_2p generated with py2hwsw --- .../ram/iob_ram_2p/hardware/src/iob_ram_2p.v | 58 ------- .../memories/ram/iob_ram_2p/iob_ram_2p.py | 158 +++++++++++++++++- 2 files changed, 157 insertions(+), 59 deletions(-) delete mode 100644 lib/hardware/memories/ram/iob_ram_2p/hardware/src/iob_ram_2p.v diff --git a/lib/hardware/memories/ram/iob_ram_2p/hardware/src/iob_ram_2p.v b/lib/hardware/memories/ram/iob_ram_2p/hardware/src/iob_ram_2p.v deleted file mode 100644 index 693605222..000000000 --- a/lib/hardware/memories/ram/iob_ram_2p/hardware/src/iob_ram_2p.v +++ /dev/null @@ -1,58 +0,0 @@ -`timescale 1ns / 1ps - -module iob_ram_2p #( - parameter HEXFILE = "none", - parameter DATA_W = 0, - parameter ADDR_W = 0, - parameter WRITE_FIRST = 1 // 0: read first | 1: write first -) ( - input clk_i, - - //write port - input w_en_i, - input [ADDR_W-1:0] w_addr_i, - input [DATA_W-1:0] w_data_i, - output w_ready_o, - - //read port - input r_en_i, - input [ADDR_W-1:0] r_addr_i, - output [DATA_W-1:0] r_data_o, - output r_ready_o -); - - wire en_int; - wire we_int; - wire [ADDR_W-1:0] addr_int; - - // Internal Single Port RAM - iob_ram_sp #( - .HEXFILE(HEXFILE), - .DATA_W(DATA_W), - .ADDR_W(ADDR_W) - ) iob_ram_sp_inst ( - .clk_i (clk_i), - .en_i (en_int), - .we_i (we_int), - .addr_i(addr_int), - .d_i (w_data_i), - .d_o (r_data_o) - ); - - generate - if (WRITE_FIRST) begin : write_first - assign en_int = w_en_i | r_en_i; - assign we_int = w_en_i; - assign addr_int = w_en_i ? w_addr_i : r_addr_i; - assign w_ready_o = 1'b1; - assign r_ready_o = ~w_en_i; - end else begin : read_first - assign en_int = w_en_i | r_en_i; - assign we_int = w_en_i & (~r_en_i); - assign addr_int = r_en_i ? r_addr_i : w_addr_i; - assign w_ready_o = ~r_en_i; - assign r_ready_o = 1'b1; - end - endgenerate - -endmodule diff --git a/lib/hardware/memories/ram/iob_ram_2p/iob_ram_2p.py b/lib/hardware/memories/ram/iob_ram_2p/iob_ram_2p.py index dc6496c3e..57e68a97d 100644 --- a/lib/hardware/memories/ram/iob_ram_2p/iob_ram_2p.py +++ b/lib/hardware/memories/ram/iob_ram_2p/iob_ram_2p.py @@ -3,11 +3,167 @@ def setup(py_params_dict): "original_name": "iob_ram_2p", "name": "iob_ram_2p", "version": "0.1", - "generate_hw": False, + "version": "0.1", + "confs": [ + { + "name": "HEXFILE", + "type": "P", + "val": '"none"', + "min": "NA", + "max": "NA", + "descr": "Name of file to load into RAM", + }, + { + "name": "DATA_W", + "type": "P", + "val": "0", + "min": "NA", + "max": "NA", + "descr": "DATA width", + }, + { + "name": "ADDR_W", + "type": "P", + "val": "0", + "min": "NA", + "max": "NA", + "descr": "Address bus width", + }, + { + "name": "WRITE_FIRST", + "type": "P", + "val": "1", + "min": "NA", + "max": "NA", + "descr": "", + }, + ], + "ports": [ + { + "name": "clk_i", + "descr": "Input port", + "signals": [ + {"name": "clk", "width": 1, "direction": "input"}, + ], + }, + { + "name": "w_en_i", + "descr": "Input port", + "signals": [ + {"name": "w_en", "width": 1, "direction": "input"}, + ], + }, + { + "name": "w_addr_i", + "descr": "Input port", + "signals": [ + {"name": "w_addr", "width": "ADDR_W", "direction": "input"}, + ], + }, + { + "name": "w_data_i", + "descr": "Input port", + "signals": [ + {"name": "w_data", "width": "DATA_W", "direction": "input"}, + ], + }, + { + "name": "w_ready_o", + "descr": "Output port", + "signals": [ + {"name": "w_ready", "width": 1, "direction": "output"}, + ], + }, + { + "name": "r_en_i", + "descr": "Input port", + "signals": [ + {"name": "r_en", "width": 1, "direction": "input"}, + ], + }, + { + "name": "r_addr_i", + "descr": "Input port", + "signals": [ + {"name": "r_addr", "width": "ADDR_W", "direction": "input"}, + ], + }, + { + "name": "r_data_o", + "descr": "Output port", + "signals": [ + {"name": "r_data", "width": "DATA_W", "direction": "output"}, + ], + }, + { + "name": "r_ready_o", + "descr": "Output port", + "signals": [ + {"name": "r_ready", "width": 1, "direction": "output"}, + ], + }, + ], + "wires": [ + { + "name": "en_int", + "descr": "en wire", + "signals": [ + {"name": "en_in", "width": 1}, + ], + }, + { + "name": "we_int", + "descr": "we wire", + "signals": [ + {"name": "we_int", "width": 1}, + ], + }, + { + "name": "addr_int", + "descr": "addr wire", + "signals": [ + {"name": "addr_int", "width": "ADDR_W"}, + ], + }, + ], "blocks": [ { "core_name": "iob_ram_sp", "instance_name": "iob_ram_sp_inst", + "parameters": { + "HEXFILE": "HEXFILE", + "DATA_W": "DATA_W", + "ADDR_W": "ADDR_W", + }, + "connect": { + "clk_i": "clk_i", + "en_i": "en_int", + "we_i": "we_int", + "addr_i": "addr_int", + "d_i": "w_data_i", + "d_o": "r_data_o", + }, + }, + ], + "snippets": [ + { + "verilog_code": """ + generate + if (WRITE_FIRST) begin : write_first + assign en_int = w_en_i | r_en_i; + assign we_int = w_en_i; + assign addr_int = w_en_i ? w_addr_i : r_addr_i; + assign w_ready_o = 1'b1; + assign r_ready_o = ~w_en_i; + end else begin : read_first + assign en_int = w_en_i | r_en_i; + assign we_int = w_en_i & (~r_en_i); + assign addr_int = r_en_i ? r_addr_i : w_addr_i; + assign w_ready_o = ~r_en_i; + assign r_ready_o = 1'b1; + end + endgenerate + """, }, ], }