diff --git a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/FTDI_AMV_CONTROLLER/ftdi_rx_avm_writer_controller_ent.vhd b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/FTDI_AMV_CONTROLLER/ftdi_rx_avm_writer_controller_ent.vhd index 7c6a3d5be..4cfb40e52 100644 --- a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/FTDI_AMV_CONTROLLER/ftdi_rx_avm_writer_controller_ent.vhd +++ b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/FTDI_AMV_CONTROLLER/ftdi_rx_avm_writer_controller_ent.vhd @@ -5,341 +5,345 @@ use ieee.numeric_std.all; use work.ftdi_avm_usb3_pkg.all; entity ftdi_rx_avm_writer_controller_ent is - port( - clk_i : in std_logic; - rst_i : in std_logic; - ftdi_module_stop_i : in std_logic; - ftdi_module_start_i : in std_logic; - controller_wr_start_i : in std_logic; - controller_wr_reset_i : in std_logic; - controller_wr_initial_addr_i : in std_logic_vector(63 downto 0); - controller_wr_length_bytes_i : in std_logic_vector(31 downto 0); - controller_rd_busy_i : in std_logic; - avm_master_wr_status_i : in t_ftdi_avm_usb3_master_wr_status; - buffer_stat_empty_i : in std_logic; - buffer_rddata_i : in std_logic_vector(255 downto 0); - buffer_rdready_i : in std_logic; - controller_wr_busy_o : out std_logic; - avm_master_wr_control_o : out t_ftdi_avm_usb3_master_wr_control; - buffer_rdreq_o : out std_logic - ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + ftdi_module_stop_i : in std_logic; + ftdi_module_start_i : in std_logic; + controller_wr_start_i : in std_logic; + controller_wr_reset_i : in std_logic; + controller_wr_initial_addr_i : in std_logic_vector(63 downto 0); + controller_wr_length_bytes_i : in std_logic_vector(31 downto 0); + controller_rd_busy_i : in std_logic; + avm_master_wr_status_i : in t_ftdi_avm_usb3_master_wr_status; + buffer_stat_empty_i : in std_logic; + buffer_rddata_i : in std_logic_vector(255 downto 0); + buffer_rdready_i : in std_logic; + controller_wr_busy_o : out std_logic; + controller_wr_finished_o : out std_logic; + avm_master_wr_control_o : out t_ftdi_avm_usb3_master_wr_control; + buffer_rdreq_o : out std_logic + ); end entity ftdi_rx_avm_writer_controller_ent; architecture RTL of ftdi_rx_avm_writer_controller_ent is - type t_ftdi_rx_avm_writer_controller_fsm is ( - STOPPED, -- rx avm writer controller is stopped - IDLE, -- rx avm writer controller is in idle - AVM_WAITING, -- avm writer is waiting the avm bus be released - BUFFER_WAITING, -- waiting data buffer to have data - BUFFER_READ, -- read data from data buffer - BUFFER_FETCH, -- fetch data from data buffer - WRITE_START, -- start of a avm write - WRITE_WAITING, -- wait for avm write to finish - FINISHED -- rx avm writer controller is finished - ); + type t_ftdi_rx_avm_writer_controller_fsm is ( + STOPPED, -- rx avm writer controller is stopped + IDLE, -- rx avm writer controller is in idle + AVM_WAITING, -- avm writer is waiting the avm bus be released + BUFFER_WAITING, -- waiting data buffer to have data + BUFFER_READ, -- read data from data buffer + BUFFER_FETCH, -- fetch data from data buffer + WRITE_START, -- start of a avm write + WRITE_WAITING, -- wait for avm write to finish + FINISHED -- rx avm writer controller is finished + ); - signal s_ftdi_rx_avm_writer_controller_state : t_ftdi_rx_avm_writer_controller_fsm; + signal s_ftdi_rx_avm_writer_controller_state : t_ftdi_rx_avm_writer_controller_fsm; - signal s_wr_addr_cnt : unsigned(58 downto 0); -- 2^64 bytes of address / 32 bytes per word = 2^59 words of addr - signal s_wr_data_cnt : unsigned(26 downto 0); -- 2^32 bytes of maximum length / 32 bytes per write = 2^27 maximum write length + signal s_wr_addr_cnt : unsigned(58 downto 0); -- 2^64 bytes of address / 32 bytes per word = 2^59 words of addr + signal s_wr_data_cnt : unsigned(26 downto 0); -- 2^32 bytes of maximum length / 32 bytes per write = 2^27 maximum write length - constant c_WR_ADDR_OVERFLOW_VAL : unsigned((s_wr_addr_cnt'length - 1) downto 0) := (others => '1'); + constant c_WR_ADDR_OVERFLOW_VAL : unsigned((s_wr_addr_cnt'length - 1) downto 0) := (others => '1'); begin - p_ftdi_rx_avm_writer_controller : process(clk_i, rst_i) is - variable v_ftdi_rx_avm_writer_controller_state : t_ftdi_rx_avm_writer_controller_fsm := STOPPED; - begin - if (rst_i = '1') then - -- fsm state reset - s_ftdi_rx_avm_writer_controller_state <= STOPPED; - v_ftdi_rx_avm_writer_controller_state := STOPPED; - -- internal signals reset - s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); - s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); - -- outputs reset - controller_wr_busy_o <= '0'; - avm_master_wr_control_o <= c_FTDI_AVM_USB3_MASTER_WR_CONTROL_RST; - buffer_rdreq_o <= '0'; - elsif rising_edge(clk_i) then - - -- States Transition -- - -- States transitions FSM - case (s_ftdi_rx_avm_writer_controller_state) is - - -- state "STOPPED" - when STOPPED => - -- rx avm writer controller is stopped - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= STOPPED; - v_ftdi_rx_avm_writer_controller_state := STOPPED; - -- default internal signal values - s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); - s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); - -- conditional state transition - -- check if a start was issued - if (ftdi_module_start_i = '1') then - -- start issued, go to idle - s_ftdi_rx_avm_writer_controller_state <= IDLE; - v_ftdi_rx_avm_writer_controller_state := IDLE; - end if; - - -- state "IDLE" - when IDLE => - -- rx avm writer controller is in idle - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= IDLE; - v_ftdi_rx_avm_writer_controller_state := IDLE; - -- default internal signal values - s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); - s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); - -- conditional state transition - -- check if a write start was requested - if (controller_wr_start_i = '1') then - -- write start requested - -- set write parameters - -- set the write addr counter to the (write initial addr / 32) - s_wr_addr_cnt <= unsigned(controller_wr_initial_addr_i(63 downto 5)); - -- set the write data counter to the (write data length / 32) - s_wr_data_cnt <= unsigned(controller_wr_length_bytes_i(31 downto 5)); - -- check if the write data length is aligned to 32 bytes and is not already zero - if ((controller_wr_length_bytes_i(4 downto 0) = "00000") and (s_wr_data_cnt /= 0)) then - -- the write data length is aligned to 32 bytes and is not already zero - -- decrement the write data counter - s_wr_data_cnt <= s_wr_data_cnt - 1; - end if; - -- check if the avm reader controller is busy (using the avm bus) - if (controller_rd_busy_i = '1') then - -- the avm reader controller is busy (using the avm bus) - -- go to avm waiting - s_ftdi_rx_avm_writer_controller_state <= AVM_WAITING; - v_ftdi_rx_avm_writer_controller_state := AVM_WAITING; - else - -- the avm reader controller is free (not using the avm bus) - -- go to buffer waiting - s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; - v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; - end if; - end if; - - -- state "AVM_WAITING" - when AVM_WAITING => - -- avm writer is waiting the avm bus be released - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= AVM_WAITING; - v_ftdi_rx_avm_writer_controller_state := AVM_WAITING; - -- default internal signal values - -- conditional state transition - -- check if the avm reader controller is free (not using the avm bus) - if (controller_rd_busy_i = '0') then - -- the avm reader controller is free (not using the avm bus) - -- go to buffer waiting - s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; - v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; - end if; - - -- state "BUFFER_WAITING" - when BUFFER_WAITING => - -- waiting data buffer to have data - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; - v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; - -- default internal signal values - -- conditional state transition - -- check if the rx data buffer is ready to be read and not empty and the avm write can start - if ((buffer_rdready_i = '1') and (buffer_stat_empty_i = '0') and (avm_master_wr_status_i.wr_ready = '1')) then - -- the rx data buffer is ready to be read and not empty and the avm write can start - -- go to buffer read - s_ftdi_rx_avm_writer_controller_state <= BUFFER_READ; - v_ftdi_rx_avm_writer_controller_state := BUFFER_READ; - end if; - - -- state "BUFFER_READ" - when BUFFER_READ => - -- read data from data buffer - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= BUFFER_FETCH; - v_ftdi_rx_avm_writer_controller_state := BUFFER_FETCH; - -- default internal signal values - -- conditional state transition - - -- state "BUFFER_FETCH" - when BUFFER_FETCH => - -- fetch data from data buffer - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= WRITE_START; - v_ftdi_rx_avm_writer_controller_state := WRITE_START; - -- default internal signal values - -- conditional state transition - - -- state "WRITE_START" - when WRITE_START => - -- start of a avm write - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= WRITE_WAITING; - v_ftdi_rx_avm_writer_controller_state := WRITE_WAITING; - -- default internal signal values - -- conditional state transition - - -- state "WRITE_WAITING" - when WRITE_WAITING => - -- wait for avm write to finish - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= WRITE_WAITING; - v_ftdi_rx_avm_writer_controller_state := WRITE_WAITING; - -- default internal signal values - -- conditional state transition - -- check if the avm write is done - if (avm_master_wr_status_i.wr_done = '1') then - -- avm write is done - -- update write addr counter - -- check if the write addr counter will overflow - if (s_wr_addr_cnt = c_WR_ADDR_OVERFLOW_VAL) then - -- the write addr counter will overflow - -- clear the write addr counter - s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); - else - -- the write addr counter will not overflow - -- increment the write addr counter - s_wr_addr_cnt <= s_wr_addr_cnt + 1; - end if; - -- check if there is more data to be write - if (s_wr_data_cnt = 0) then - -- there is no more data to be write - -- go to finished - s_ftdi_rx_avm_writer_controller_state <= FINISHED; - v_ftdi_rx_avm_writer_controller_state := FINISHED; - else - -- there is more data to be write - -- decrement write data counter - s_wr_data_cnt <= s_wr_data_cnt - 1; - -- check if the rx data buffer is ready to be read and not empty and the avm write can start - if ((buffer_rdready_i = '1') and (buffer_stat_empty_i = '0') and (avm_master_wr_status_i.wr_ready = '1')) then - -- the rx data buffer is ready to be read and not empty and the avm write can start - -- go to buffer read - s_ftdi_rx_avm_writer_controller_state <= BUFFER_READ; - v_ftdi_rx_avm_writer_controller_state := BUFFER_READ; - else - -- the rx data buffer is not ready to be read or not empty or the avm write cannot start - -- go to buffer waiting - s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; - v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; - end if; - end if; - end if; - - -- state "FINISHED" - when FINISHED => - -- rx avm writer controller is finished - -- default state transition - s_ftdi_rx_avm_writer_controller_state <= IDLE; - v_ftdi_rx_avm_writer_controller_state := IDLE; - -- default internal signal values - s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); - s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); - -- conditional state transition - - -- all the other states (not defined) - when others => - s_ftdi_rx_avm_writer_controller_state <= STOPPED; - v_ftdi_rx_avm_writer_controller_state := STOPPED; - - end case; - - -- check if a stop was issued - if (ftdi_module_stop_i = '1') then - -- a stop was issued - -- go to stopped - s_ftdi_rx_avm_writer_controller_state <= STOPPED; - v_ftdi_rx_avm_writer_controller_state := STOPPED; - -- check if a reset was requested - elsif (controller_wr_reset_i = '1') then - -- a reset was requested - -- go to idle - s_ftdi_rx_avm_writer_controller_state <= IDLE; - v_ftdi_rx_avm_writer_controller_state := IDLE; - end if; - - -- Output Generation -- - -- Default output generation - controller_wr_busy_o <= '0'; - avm_master_wr_control_o <= c_FTDI_AVM_USB3_MASTER_WR_CONTROL_RST; - buffer_rdreq_o <= '0'; - -- Output generation FSM - case (v_ftdi_rx_avm_writer_controller_state) is - - -- state "STOPPED" - when STOPPED => - -- rx avm writer controller is stopped - -- default output signals - null; - -- conditional output signals - - -- state "IDLE" - when IDLE => - -- rx avm writer controller is in idle - -- default output signals - null; - -- conditional output signals - - -- state "AVM_WAITING" - when AVM_WAITING => - -- avm writer is waiting the avm bus be released - -- default output signals - controller_wr_busy_o <= '1'; - -- conditional output signals - - -- state "BUFFER_WAITING" - when BUFFER_WAITING => - -- waiting data buffer to have data - -- default output signals - controller_wr_busy_o <= '1'; - -- conditional output signals - - -- state "BUFFER_READ" - when BUFFER_READ => - -- read data from data buffer - -- default output signals - controller_wr_busy_o <= '1'; - buffer_rdreq_o <= '1'; - -- conditional output signals - - -- state "BUFFER_FETCH" - when BUFFER_FETCH => - -- fetch data from data buffer - -- default output signals - controller_wr_busy_o <= '1'; - -- conditional output signals - - -- state "WRITE_START" - when WRITE_START => - -- start of a avm write - -- default output signals - controller_wr_busy_o <= '1'; - avm_master_wr_control_o.wr_req <= '1'; - avm_master_wr_control_o.wr_address(63 downto 5) <= std_logic_vector(s_wr_addr_cnt); - avm_master_wr_control_o.wr_address(4 downto 0) <= (others => '0'); - avm_master_wr_control_o.wr_data <= buffer_rddata_i; - -- conditional output signals - - -- state "WRITE_WAITING" - when WRITE_WAITING => - -- wait for avm write to finish - -- default output signals - controller_wr_busy_o <= '1'; - -- conditional output signals - - -- state "FINISHED" - when FINISHED => - -- rx avm writer controller is finished - -- default output signals - controller_wr_busy_o <= '1'; - -- conditional output signals - - end case; - - end if; - end process p_ftdi_rx_avm_writer_controller; + p_ftdi_rx_avm_writer_controller : process(clk_i, rst_i) is + variable v_ftdi_rx_avm_writer_controller_state : t_ftdi_rx_avm_writer_controller_fsm := STOPPED; + begin + if (rst_i = '1') then + -- fsm state reset + s_ftdi_rx_avm_writer_controller_state <= STOPPED; + v_ftdi_rx_avm_writer_controller_state := STOPPED; + -- internal signals reset + s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); + s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); + -- outputs reset + controller_wr_busy_o <= '0'; + controller_wr_finished_o <= '0'; + avm_master_wr_control_o <= c_FTDI_AVM_USB3_MASTER_WR_CONTROL_RST; + buffer_rdreq_o <= '0'; + elsif rising_edge(clk_i) then + + -- States Transition -- + -- States transitions FSM + case (s_ftdi_rx_avm_writer_controller_state) is + + -- state "STOPPED" + when STOPPED => + -- rx avm writer controller is stopped + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= STOPPED; + v_ftdi_rx_avm_writer_controller_state := STOPPED; + -- default internal signal values + s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); + s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); + -- conditional state transition + -- check if a start was issued + if (ftdi_module_start_i = '1') then + -- start issued, go to idle + s_ftdi_rx_avm_writer_controller_state <= IDLE; + v_ftdi_rx_avm_writer_controller_state := IDLE; + end if; + + -- state "IDLE" + when IDLE => + -- rx avm writer controller is in idle + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= IDLE; + v_ftdi_rx_avm_writer_controller_state := IDLE; + -- default internal signal values + s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); + s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); + -- conditional state transition + -- check if a write start was requested + if (controller_wr_start_i = '1') then + -- write start requested + -- set write parameters + -- set the write addr counter to the (write initial addr / 32) + s_wr_addr_cnt <= unsigned(controller_wr_initial_addr_i(63 downto 5)); + -- set the write data counter to the (write data length / 32) + s_wr_data_cnt <= unsigned(controller_wr_length_bytes_i(31 downto 5)); + -- check if the write data length is aligned to 32 bytes and is not already zero + if ((controller_wr_length_bytes_i(4 downto 0) = "00000") and (s_wr_data_cnt /= 0)) then + -- the write data length is aligned to 32 bytes and is not already zero + -- decrement the write data counter + s_wr_data_cnt <= s_wr_data_cnt - 1; + end if; + -- check if the avm reader controller is busy (using the avm bus) + if (controller_rd_busy_i = '1') then + -- the avm reader controller is busy (using the avm bus) + -- go to avm waiting + s_ftdi_rx_avm_writer_controller_state <= AVM_WAITING; + v_ftdi_rx_avm_writer_controller_state := AVM_WAITING; + else + -- the avm reader controller is free (not using the avm bus) + -- go to buffer waiting + s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; + v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; + end if; + end if; + + -- state "AVM_WAITING" + when AVM_WAITING => + -- avm writer is waiting the avm bus be released + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= AVM_WAITING; + v_ftdi_rx_avm_writer_controller_state := AVM_WAITING; + -- default internal signal values + -- conditional state transition + -- check if the avm reader controller is free (not using the avm bus) + if (controller_rd_busy_i = '0') then + -- the avm reader controller is free (not using the avm bus) + -- go to buffer waiting + s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; + v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; + end if; + + -- state "BUFFER_WAITING" + when BUFFER_WAITING => + -- waiting data buffer to have data + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; + v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; + -- default internal signal values + -- conditional state transition + -- check if the rx data buffer is ready to be read and not empty and the avm write can start + if ((buffer_rdready_i = '1') and (buffer_stat_empty_i = '0') and (avm_master_wr_status_i.wr_ready = '1')) then + -- the rx data buffer is ready to be read and not empty and the avm write can start + -- go to buffer read + s_ftdi_rx_avm_writer_controller_state <= BUFFER_READ; + v_ftdi_rx_avm_writer_controller_state := BUFFER_READ; + end if; + + -- state "BUFFER_READ" + when BUFFER_READ => + -- read data from data buffer + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= BUFFER_FETCH; + v_ftdi_rx_avm_writer_controller_state := BUFFER_FETCH; + -- default internal signal values + -- conditional state transition + + -- state "BUFFER_FETCH" + when BUFFER_FETCH => + -- fetch data from data buffer + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= WRITE_START; + v_ftdi_rx_avm_writer_controller_state := WRITE_START; + -- default internal signal values + -- conditional state transition + + -- state "WRITE_START" + when WRITE_START => + -- start of a avm write + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= WRITE_WAITING; + v_ftdi_rx_avm_writer_controller_state := WRITE_WAITING; + -- default internal signal values + -- conditional state transition + + -- state "WRITE_WAITING" + when WRITE_WAITING => + -- wait for avm write to finish + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= WRITE_WAITING; + v_ftdi_rx_avm_writer_controller_state := WRITE_WAITING; + -- default internal signal values + -- conditional state transition + -- check if the avm write is done + if (avm_master_wr_status_i.wr_done = '1') then + -- avm write is done + -- update write addr counter + -- check if the write addr counter will overflow + if (s_wr_addr_cnt = c_WR_ADDR_OVERFLOW_VAL) then + -- the write addr counter will overflow + -- clear the write addr counter + s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); + else + -- the write addr counter will not overflow + -- increment the write addr counter + s_wr_addr_cnt <= s_wr_addr_cnt + 1; + end if; + -- check if there is more data to be write + if (s_wr_data_cnt = 0) then + -- there is no more data to be write + -- go to finished + s_ftdi_rx_avm_writer_controller_state <= FINISHED; + v_ftdi_rx_avm_writer_controller_state := FINISHED; + else + -- there is more data to be write + -- decrement write data counter + s_wr_data_cnt <= s_wr_data_cnt - 1; + -- check if the rx data buffer is ready to be read and not empty and the avm write can start + if ((buffer_rdready_i = '1') and (buffer_stat_empty_i = '0') and (avm_master_wr_status_i.wr_ready = '1')) then + -- the rx data buffer is ready to be read and not empty and the avm write can start + -- go to buffer read + s_ftdi_rx_avm_writer_controller_state <= BUFFER_READ; + v_ftdi_rx_avm_writer_controller_state := BUFFER_READ; + else + -- the rx data buffer is not ready to be read or not empty or the avm write cannot start + -- go to buffer waiting + s_ftdi_rx_avm_writer_controller_state <= BUFFER_WAITING; + v_ftdi_rx_avm_writer_controller_state := BUFFER_WAITING; + end if; + end if; + end if; + + -- state "FINISHED" + when FINISHED => + -- rx avm writer controller is finished + -- default state transition + s_ftdi_rx_avm_writer_controller_state <= IDLE; + v_ftdi_rx_avm_writer_controller_state := IDLE; + -- default internal signal values + s_wr_addr_cnt <= to_unsigned(0, s_wr_addr_cnt'length); + s_wr_data_cnt <= to_unsigned(0, s_wr_data_cnt'length); + -- conditional state transition + + -- all the other states (not defined) + when others => + s_ftdi_rx_avm_writer_controller_state <= STOPPED; + v_ftdi_rx_avm_writer_controller_state := STOPPED; + + end case; + + -- check if a stop was issued + if (ftdi_module_stop_i = '1') then + -- a stop was issued + -- go to stopped + s_ftdi_rx_avm_writer_controller_state <= STOPPED; + v_ftdi_rx_avm_writer_controller_state := STOPPED; + -- check if a reset was requested + elsif (controller_wr_reset_i = '1') then + -- a reset was requested + -- go to idle + s_ftdi_rx_avm_writer_controller_state <= IDLE; + v_ftdi_rx_avm_writer_controller_state := IDLE; + end if; + + -- Output Generation -- + -- Default output generation + controller_wr_busy_o <= '0'; + controller_wr_finished_o <= '0'; + avm_master_wr_control_o <= c_FTDI_AVM_USB3_MASTER_WR_CONTROL_RST; + buffer_rdreq_o <= '0'; + -- Output generation FSM + case (v_ftdi_rx_avm_writer_controller_state) is + + -- state "STOPPED" + when STOPPED => + -- rx avm writer controller is stopped + -- default output signals + null; + -- conditional output signals + + -- state "IDLE" + when IDLE => + -- rx avm writer controller is in idle + -- default output signals + null; + -- conditional output signals + + -- state "AVM_WAITING" + when AVM_WAITING => + -- avm writer is waiting the avm bus be released + -- default output signals + controller_wr_busy_o <= '1'; + -- conditional output signals + + -- state "BUFFER_WAITING" + when BUFFER_WAITING => + -- waiting data buffer to have data + -- default output signals + controller_wr_busy_o <= '1'; + -- conditional output signals + + -- state "BUFFER_READ" + when BUFFER_READ => + -- read data from data buffer + -- default output signals + controller_wr_busy_o <= '1'; + buffer_rdreq_o <= '1'; + -- conditional output signals + + -- state "BUFFER_FETCH" + when BUFFER_FETCH => + -- fetch data from data buffer + -- default output signals + controller_wr_busy_o <= '1'; + -- conditional output signals + + -- state "WRITE_START" + when WRITE_START => + -- start of a avm write + -- default output signals + controller_wr_busy_o <= '1'; + avm_master_wr_control_o.wr_req <= '1'; + avm_master_wr_control_o.wr_address(63 downto 5) <= std_logic_vector(s_wr_addr_cnt); + avm_master_wr_control_o.wr_address(4 downto 0) <= (others => '0'); + avm_master_wr_control_o.wr_data <= buffer_rddata_i; + -- conditional output signals + + -- state "WRITE_WAITING" + when WRITE_WAITING => + -- wait for avm write to finish + -- default output signals + controller_wr_busy_o <= '1'; + -- conditional output signals + + -- state "FINISHED" + when FINISHED => + -- rx avm writer controller is finished + -- default output signals + controller_wr_busy_o <= '1'; + controller_wr_finished_o <= '1'; + -- conditional output signals + + end case; + + end if; + end process p_ftdi_rx_avm_writer_controller; end architecture RTL; diff --git a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_irq_manager_pkg.vhd b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_irq_manager_pkg.vhd index 985a0a558..af20e7ef7 100644 --- a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_irq_manager_pkg.vhd +++ b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_irq_manager_pkg.vhd @@ -4,49 +4,51 @@ use ieee.numeric_std.all; package ftdi_irq_manager_pkg is - type t_ftdi_rx_irq_manager_watches is record - rx_buffer_empty : std_logic; - rly_hccd_last_rx_buffer : std_logic; - rx_hccd_comm_err_state : std_logic; - end record t_ftdi_rx_irq_manager_watches; - - type t_ftdi_rx_irq_manager_flags is record - rx_hccd_received : std_logic; - rx_hccd_comm_err : std_logic; - end record t_ftdi_rx_irq_manager_flags; - - constant c_FTDI_RX_IRQ_MANAGER_WATCHES_RST : t_ftdi_rx_irq_manager_watches := ( - rx_buffer_empty => '0', - rly_hccd_last_rx_buffer => '0', - rx_hccd_comm_err_state => '0' - ); - - constant c_FTDI_RX_IRQ_MANAGER_FLAGS_RST : t_ftdi_rx_irq_manager_flags := ( - rx_hccd_received => '0', - rx_hccd_comm_err => '0' - ); - - -- - - type t_ftdi_tx_irq_manager_watches is record - tx_lut_transmitted : std_logic; - tx_lut_comm_err_state : std_logic; - end record t_ftdi_tx_irq_manager_watches; - - type t_ftdi_tx_irq_manager_flags is record - tx_lut_finished : std_logic; - tx_lut_comm_err : std_logic; - end record t_ftdi_tx_irq_manager_flags; - - constant c_FTDI_TX_IRQ_MANAGER_WATCHES_RST : t_ftdi_tx_irq_manager_watches := ( - tx_lut_transmitted => '0', - tx_lut_comm_err_state => '0' - ); - - constant c_FTDI_TX_IRQ_MANAGER_FLAGS_RST : t_ftdi_tx_irq_manager_flags := ( - tx_lut_finished => '0', - tx_lut_comm_err => '0' - ); + type t_ftdi_rx_irq_manager_watches is record + -- rx_buffer_empty : std_logic; + rly_hccd_last_rx_buffer : std_logic; + avm_controller_wr_finished : std_logic; + rx_hccd_comm_err_state : std_logic; + end record t_ftdi_rx_irq_manager_watches; + + type t_ftdi_rx_irq_manager_flags is record + rx_hccd_received : std_logic; + rx_hccd_comm_err : std_logic; + end record t_ftdi_rx_irq_manager_flags; + + constant c_FTDI_RX_IRQ_MANAGER_WATCHES_RST : t_ftdi_rx_irq_manager_watches := ( + -- rx_buffer_empty => '0', + rly_hccd_last_rx_buffer => '0', + avm_controller_wr_finished => '0', + rx_hccd_comm_err_state => '0' + ); + + constant c_FTDI_RX_IRQ_MANAGER_FLAGS_RST : t_ftdi_rx_irq_manager_flags := ( + rx_hccd_received => '0', + rx_hccd_comm_err => '0' + ); + + -- + + type t_ftdi_tx_irq_manager_watches is record + tx_lut_transmitted : std_logic; + tx_lut_comm_err_state : std_logic; + end record t_ftdi_tx_irq_manager_watches; + + type t_ftdi_tx_irq_manager_flags is record + tx_lut_finished : std_logic; + tx_lut_comm_err : std_logic; + end record t_ftdi_tx_irq_manager_flags; + + constant c_FTDI_TX_IRQ_MANAGER_WATCHES_RST : t_ftdi_tx_irq_manager_watches := ( + tx_lut_transmitted => '0', + tx_lut_comm_err_state => '0' + ); + + constant c_FTDI_TX_IRQ_MANAGER_FLAGS_RST : t_ftdi_tx_irq_manager_flags := ( + tx_lut_finished => '0', + tx_lut_comm_err => '0' + ); end package ftdi_irq_manager_pkg; diff --git a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_rx_irq_manager_ent.vhd b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_rx_irq_manager_ent.vhd index 25534bf9a..a23898baa 100644 --- a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_rx_irq_manager_ent.vhd +++ b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/IRQ_MANAGER/ftdi_rx_irq_manager_ent.vhd @@ -5,93 +5,102 @@ use ieee.numeric_std.all; use work.ftdi_irq_manager_pkg.all; entity ftdi_rx_irq_manager_ent is - port( - clk_i : in std_logic; - rst_i : in std_logic; - irq_manager_stop_i : in std_logic; - irq_manager_start_i : in std_logic; - global_irq_en_i : in std_logic; - irq_watches_i : in t_ftdi_rx_irq_manager_watches; - irq_flags_en_i : in t_ftdi_rx_irq_manager_flags; - irq_flags_clr_i : in t_ftdi_rx_irq_manager_flags; - irq_flags_o : out t_ftdi_rx_irq_manager_flags; - irq_o : out std_logic - ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + irq_manager_stop_i : in std_logic; + irq_manager_start_i : in std_logic; + global_irq_en_i : in std_logic; + irq_watches_i : in t_ftdi_rx_irq_manager_watches; + irq_flags_en_i : in t_ftdi_rx_irq_manager_flags; + irq_flags_clr_i : in t_ftdi_rx_irq_manager_flags; + irq_flags_o : out t_ftdi_rx_irq_manager_flags; + irq_o : out std_logic + ); end entity ftdi_rx_irq_manager_ent; architecture RTL of ftdi_rx_irq_manager_ent is - signal s_irq_manager_started : std_logic; - signal s_irq_watches_delayed : t_ftdi_rx_irq_manager_watches; - signal s_irq_flags : t_ftdi_rx_irq_manager_flags; + signal s_irq_manager_started : std_logic; + signal s_irq_watches_delayed : t_ftdi_rx_irq_manager_watches; + signal s_irq_flags : t_ftdi_rx_irq_manager_flags; - signal s_rx_payload_written_flag : std_logic; + signal s_rx_payload_written_flag : std_logic; + signal s_avm_controller_wr_finished : std_logic; begin - p_ftdi_rx_irq_manager : process(clk_i, rst_i) is - begin - if (rst_i = '1') then - - s_irq_manager_started <= '0'; - s_irq_watches_delayed <= c_FTDI_RX_IRQ_MANAGER_WATCHES_RST; - s_irq_flags <= c_FTDI_RX_IRQ_MANAGER_FLAGS_RST; - - s_rx_payload_written_flag <= '0'; - - elsif (rising_edge(clk_i)) then - - -- manage start/stop - if (irq_manager_start_i = '1') then - s_irq_manager_started <= '1'; - elsif (irq_manager_stop_i = '1') then - s_irq_manager_started <= '0'; - end if; - - -- manage flags - if (s_irq_manager_started = '0') then - -- keep flags cleared - s_irq_flags <= c_FTDI_RX_IRQ_MANAGER_FLAGS_RST; - s_rx_payload_written_flag <= '0'; - else - -- clear flags -- - if (irq_flags_clr_i.rx_hccd_received = '1') then - s_rx_payload_written_flag <= '0'; - s_irq_flags.rx_hccd_received <= '0'; - end if; - if (irq_flags_clr_i.rx_hccd_comm_err = '1') then - s_irq_flags.rx_hccd_comm_err <= '0'; - end if; - -- set flags -- - -- check if the global interrupt is enabled - if (global_irq_en_i = '1') then - if (irq_flags_en_i.rx_hccd_received = '1') then - - if ((s_irq_watches_delayed.rly_hccd_last_rx_buffer = '0') and (irq_watches_i.rly_hccd_last_rx_buffer = '1')) then - s_rx_payload_written_flag <= '1'; - end if; - if ((s_irq_watches_delayed.rx_buffer_empty = '0') and (irq_watches_i.rx_buffer_empty = '1') and (s_rx_payload_written_flag = '1')) then - s_irq_flags.rx_hccd_received <= '1'; - end if; - end if; - if (irq_flags_en_i.rx_hccd_comm_err = '1') then - if ((s_irq_watches_delayed.rx_hccd_comm_err_state = '0') and (irq_watches_i.rx_hccd_comm_err_state = '1')) then - s_irq_flags.rx_hccd_comm_err <= '1'; - end if; - end if; - end if; - end if; - - -- delay signals - s_irq_watches_delayed <= irq_watches_i; - - end if; - end process p_ftdi_rx_irq_manager; - - -- irq assignment and outputs generation - irq_flags_o <= s_irq_flags; - irq_o <= ('0') when (rst_i = '1') - else ('1') when ((s_irq_flags.rx_hccd_received = '1') or (s_irq_flags.rx_hccd_comm_err = '1')) - else ('0'); + p_ftdi_rx_irq_manager : process(clk_i, rst_i) is + begin + if (rst_i = '1') then + + s_irq_manager_started <= '0'; + s_irq_watches_delayed <= c_FTDI_RX_IRQ_MANAGER_WATCHES_RST; + s_irq_flags <= c_FTDI_RX_IRQ_MANAGER_FLAGS_RST; + + s_rx_payload_written_flag <= '0'; + s_avm_controller_wr_finished <= '0'; + + elsif (rising_edge(clk_i)) then + + -- manage start/stop + if (irq_manager_start_i = '1') then + s_irq_manager_started <= '1'; + elsif (irq_manager_stop_i = '1') then + s_irq_manager_started <= '0'; + end if; + + -- manage flags + if (s_irq_manager_started = '0') then + -- keep flags cleared + s_irq_flags <= c_FTDI_RX_IRQ_MANAGER_FLAGS_RST; + s_rx_payload_written_flag <= '0'; + else + -- clear flags -- + if (irq_flags_clr_i.rx_hccd_received = '1') then + s_rx_payload_written_flag <= '0'; + s_irq_flags.rx_hccd_received <= '0'; + end if; + if (irq_flags_clr_i.rx_hccd_comm_err = '1') then + s_irq_flags.rx_hccd_comm_err <= '0'; + end if; + -- set flags -- + -- check if the global interrupt is enabled + if (global_irq_en_i = '1') then + if (irq_flags_en_i.rx_hccd_received = '1') then + if ((s_irq_watches_delayed.rly_hccd_last_rx_buffer = '0') and (irq_watches_i.rly_hccd_last_rx_buffer = '1')) then + s_rx_payload_written_flag <= '1'; + end if; + -- if ((s_irq_watches_delayed.rx_buffer_empty = '0') and (irq_watches_i.rx_buffer_empty = '1') and (s_rx_payload_written_flag = '1')) then + -- s_irq_flags.rx_hccd_received <= '1'; + -- end if; + if ((s_irq_watches_delayed.avm_controller_wr_finished = '0') and (irq_watches_i.avm_controller_wr_finished = '1')) then + s_avm_controller_wr_finished <= '1'; + end if; + if ((s_rx_payload_written_flag = '1') and (s_avm_controller_wr_finished = '1')) then + s_irq_flags.rx_hccd_received <= '1'; + s_rx_payload_written_flag <= '0'; + s_avm_controller_wr_finished <= '0'; + end if; + end if; + if (irq_flags_en_i.rx_hccd_comm_err = '1') then + if ((s_irq_watches_delayed.rx_hccd_comm_err_state = '0') and (irq_watches_i.rx_hccd_comm_err_state = '1')) then + s_irq_flags.rx_hccd_comm_err <= '1'; + end if; + end if; + end if; + end if; + + -- delay signals + s_irq_watches_delayed <= irq_watches_i; + + end if; + end process p_ftdi_rx_irq_manager; + + -- irq assignment and outputs generation + irq_flags_o <= s_irq_flags; + irq_o <= ('0') when (rst_i = '1') + else ('1') when ((s_irq_flags.rx_hccd_received = '1') or (s_irq_flags.rx_hccd_comm_err = '1')) + else ('0'); end architecture RTL; diff --git a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/PROTOCOL/ftdi_rx_protocol_payload_reader_ent.vhd b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/PROTOCOL/ftdi_rx_protocol_payload_reader_ent.vhd index 85701c766..8135d70e4 100644 --- a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/PROTOCOL/ftdi_rx_protocol_payload_reader_ent.vhd +++ b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/PROTOCOL/ftdi_rx_protocol_payload_reader_ent.vhd @@ -91,7 +91,8 @@ architecture RTL of ftdi_rx_protocol_payload_reader_ent is signal s_payload_write_flag : std_logic; signal s_force_payload_length_flag : std_logic; - signal s_registered_forced_length_bytes : unsigned(31 downto 0); + signal s_registered_forced_length_bytes : unsigned(26 downto 0); -- 2^32 bytes of maximum length / 32 bytes per write = 2^27 maximum write length + constant c_FORCED_LENGTH_BYTES_ZERO : unsigned((s_registered_forced_length_bytes'length - 1) downto 0) := (others => '0'); signal s_qqword_delay_clear : std_logic; signal s_qqword_delay_trigger : std_logic; @@ -221,12 +222,12 @@ begin v_ftdi_tx_prot_payload_reader_state := WAITING_RX_DATA_EOP; end if; -- check if the payload length need to be forced to a specific length - if (payload_force_length_bytes_i /= x"00000000") then + if ((payload_force_length_bytes_i /= x"00000000") and (payload_force_length_bytes_i /= payload_length_bytes_i)) then -- the payload length need to be forced to a specific length -- set the force payload length flag s_force_payload_length_flag <= '1'; - -- register the forced payload length - s_registered_forced_length_bytes <= unsigned(payload_force_length_bytes_i); + -- register the forced payload length to (forced payload length / 32) + s_registered_forced_length_bytes <= unsigned(payload_force_length_bytes_i(31 downto 5)); end if; end if; @@ -713,7 +714,7 @@ begin if (s_force_payload_length_flag = '1') then -- the payload need to be forced to a specific length -- check if the payload has passed the forced length - if (s_registered_forced_length_bytes <= 32) then + if (s_registered_forced_length_bytes <= 1) then -- the payload has passed the forced length -- clear the payload write flag s_payload_write_flag <= '0'; @@ -724,7 +725,7 @@ begin else -- the payload has passed not the forced length -- decrement the 32 bytes written to the buffer - s_registered_forced_length_bytes <= s_registered_forced_length_bytes - 32; + s_registered_forced_length_bytes <= s_registered_forced_length_bytes - 1; end if; end if; -- check if the rx data buffer is full @@ -887,7 +888,7 @@ begin if (s_force_payload_length_flag = '1') then -- the payload need to be forced to a specific length -- check if the payload need to be filled with zeros - if (s_registered_forced_length_bytes /= x"00000000") then + if (s_registered_forced_length_bytes /= c_FORCED_LENGTH_BYTES_ZERO) then -- the payload need to be filled with zeros -- go to payload wating fill s_ftdi_tx_prot_payload_reader_state <= PAYLOAD_WAITING_FILL; @@ -955,7 +956,7 @@ begin v_mask_cnt := 0; -- conditional state transition -- check if the zero fill ended - if (s_registered_forced_length_bytes <= 32) then + if (s_registered_forced_length_bytes <= 1) then -- the zero fill ended -- go to finish payload rx s_ftdi_tx_prot_payload_reader_state <= FINISH_PAYLOAD_RX; @@ -963,7 +964,7 @@ begin else -- the zero fill has not ended -- decrement the 32 bytes written to the buffer - s_registered_forced_length_bytes <= s_registered_forced_length_bytes - 32; + s_registered_forced_length_bytes <= s_registered_forced_length_bytes - 1; -- go to payload wating fill s_ftdi_tx_prot_payload_reader_state <= PAYLOAD_DELAY_FILL; v_ftdi_tx_prot_payload_reader_state := PAYLOAD_DELAY_FILL; diff --git a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/ftdi_usb3_top.vhd b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/ftdi_usb3_top.vhd index 409d55aec..9960b5d06 100644 --- a/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/ftdi_usb3_top.vhd +++ b/FPGA_Developments/FTDI_USB3/Development/Ftdi_Usb3/ftdi_usb3_top.vhd @@ -88,6 +88,9 @@ architecture rtl of ftdi_usb3_top is signal s_avm_usb3_master_wr_status : t_ftdi_avm_usb3_master_wr_status; signal s_avm_slave_wr_control_address : std_logic_vector((c_FTDI_AVM_USB3_ADRESS_SIZE - 1) downto 0); + -- FTDI AVM Controller Signals + signal s_avm_controller_wr_finished : std_logic; + -- Tx Data Buffer Signals signal s_tx_buffer_wrdata : std_logic_vector(255 downto 0); signal s_tx_buffer_wrreq : std_logic; @@ -271,6 +274,7 @@ begin buffer_rddata_i => s_rx_buffer_rddata, buffer_rdready_i => s_rx_buffer_rdready, controller_wr_busy_o => s_config_read_registers.rx_data_status_reg.rx_wr_busy, + controller_wr_finished_o => s_avm_controller_wr_finished, avm_master_wr_control_o => s_avm_usb3_master_wr_control, buffer_rdreq_o => s_rx_buffer_rdreq ); @@ -425,21 +429,22 @@ begin -- RX IRQ Manager ftdi_rx_irq_manager_ent_inst : entity work.ftdi_rx_irq_manager_ent port map( - clk_i => a_avs_clock, - rst_i => a_reset, - irq_manager_stop_i => s_config_write_registers.ftdi_module_control_reg.ftdi_module_stop, - irq_manager_start_i => s_config_write_registers.ftdi_module_control_reg.ftdi_module_start, - global_irq_en_i => s_config_write_registers.ftdi_irq_control_reg.ftdi_global_irq_en, - irq_watches_i.rx_buffer_empty => s_config_read_registers.rx_buffer_status_reg.rx_buffer_empty, - irq_watches_i.rly_hccd_last_rx_buffer => s_config_read_registers.hccd_reply_status_reg.rly_hccd_last_rx_buffer, - irq_watches_i.rx_hccd_comm_err_state => s_config_read_registers.rx_comm_error_reg.rx_comm_err_state, - irq_flags_en_i.rx_hccd_received => s_config_write_registers.rx_irq_control_reg.rx_hccd_received_irq_en, - irq_flags_en_i.rx_hccd_comm_err => s_config_write_registers.rx_irq_control_reg.rx_hccd_comm_err_irq_en, - irq_flags_clr_i.rx_hccd_received => s_config_write_registers.rx_irq_flag_clear_reg.rx_hccd_received_irq_flag_clr, - irq_flags_clr_i.rx_hccd_comm_err => s_config_write_registers.rx_irq_flag_clear_reg.rx_hccd_comm_err_irq_flag_clr, - irq_flags_o.rx_hccd_received => s_config_read_registers.rx_irq_flag_reg.rx_hccd_received_irq_flag, - irq_flags_o.rx_hccd_comm_err => s_config_read_registers.rx_irq_flag_reg.rx_hccd_comm_err_irq_flag, - irq_o => a_irq_rx + clk_i => a_avs_clock, + rst_i => a_reset, + irq_manager_stop_i => s_config_write_registers.ftdi_module_control_reg.ftdi_module_stop, + irq_manager_start_i => s_config_write_registers.ftdi_module_control_reg.ftdi_module_start, + global_irq_en_i => s_config_write_registers.ftdi_irq_control_reg.ftdi_global_irq_en, + -- irq_watches_i.rx_buffer_empty => s_config_read_registers.rx_buffer_status_reg.rx_buffer_empty, + irq_watches_i.rly_hccd_last_rx_buffer => s_config_read_registers.hccd_reply_status_reg.rly_hccd_last_rx_buffer, + irq_watches_i.avm_controller_wr_finished => s_avm_controller_wr_finished, + irq_watches_i.rx_hccd_comm_err_state => s_config_read_registers.rx_comm_error_reg.rx_comm_err_state, + irq_flags_en_i.rx_hccd_received => s_config_write_registers.rx_irq_control_reg.rx_hccd_received_irq_en, + irq_flags_en_i.rx_hccd_comm_err => s_config_write_registers.rx_irq_control_reg.rx_hccd_comm_err_irq_en, + irq_flags_clr_i.rx_hccd_received => s_config_write_registers.rx_irq_flag_clear_reg.rx_hccd_received_irq_flag_clr, + irq_flags_clr_i.rx_hccd_comm_err => s_config_write_registers.rx_irq_flag_clear_reg.rx_hccd_comm_err_irq_flag_clr, + irq_flags_o.rx_hccd_received => s_config_read_registers.rx_irq_flag_reg.rx_hccd_received_irq_flag, + irq_flags_o.rx_hccd_comm_err => s_config_read_registers.rx_irq_flag_reg.rx_hccd_comm_err_irq_flag, + irq_o => a_irq_rx ); -- TX IRQ Manager diff --git a/FPGA_Developments/FTDI_USB3/Development/Testbench/ftdi_config_avalon_mm_stimulli.vhd b/FPGA_Developments/FTDI_USB3/Development/Testbench/ftdi_config_avalon_mm_stimulli.vhd index 29e5de94b..dd57a717c 100644 --- a/FPGA_Developments/FTDI_USB3/Development/Testbench/ftdi_config_avalon_mm_stimulli.vhd +++ b/FPGA_Developments/FTDI_USB3/Development/Testbench/ftdi_config_avalon_mm_stimulli.vhd @@ -250,17 +250,19 @@ begin when 20 => -- Request Half-CCD - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_fee_number <= std_logic_vector(to_unsigned(3, 3)); - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_number <= std_logic_vector(to_unsigned(2, 2)); - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_side <= '1'; - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_height <= std_logic_vector(to_unsigned(16, 13)); - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_width <= std_logic_vector(to_unsigned(7, 12)); - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_exposure_number <= std_logic_vector(to_unsigned(875, 16)); - avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_req_timeout <= std_logic_vector(to_unsigned(0, 16)); - avs_config_wr_regs_o.hccd_req_control_reg.req_request_hccd <= '1'; + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_fee_number <= std_logic_vector(to_unsigned(3, 3)); + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_number <= std_logic_vector(to_unsigned(2, 2)); + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_side <= '1'; + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_height <= std_logic_vector(to_unsigned(16, 13)); + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_ccd_width <= std_logic_vector(to_unsigned(7, 12)); + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_exposure_number <= std_logic_vector(to_unsigned(875, 16)); + avs_config_wr_regs_o.hccd_req_control_reg.req_hccd_req_timeout <= std_logic_vector(to_unsigned(0, 16)); + avs_config_wr_regs_o.hccd_req_control_reg.req_request_hccd <= '1'; + -- Payload Config + avs_config_wr_regs_o.payload_config_reg.rx_payload_reader_force_length_bytes <= std_logic_vector(to_unsigned(864, 32)); -- AMV Controller - avs_config_wr_regs_o.rx_data_control_reg.rx_wr_data_length_bytes <= x"FFFFFFFF"; - avs_config_wr_regs_o.rx_data_control_reg.rx_wr_start <= '1'; + avs_config_wr_regs_o.rx_data_control_reg.rx_wr_data_length_bytes <= std_logic_vector(to_unsigned(864 - 32, 32)); + avs_config_wr_regs_o.rx_data_control_reg.rx_wr_start <= '1'; -- when 20 => -- -- Transmit LUT diff --git a/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/OTHERS_MANAGERS/scom_frame_manager_ent.vhd b/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/OTHERS_MANAGERS/scom_frame_manager_ent.vhd index d43311870..6d5270491 100644 --- a/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/OTHERS_MANAGERS/scom_frame_manager_ent.vhd +++ b/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/OTHERS_MANAGERS/scom_frame_manager_ent.vhd @@ -57,7 +57,7 @@ begin if (ch_sync_trigger_i = '1') then -- sync issued, increment frame -- check if the frame was cleared - if (frame_clear_i = '1') then + if (s_frame_cleared = '1') then -- the frame was cleared, no need to increment -- clear the frame cleared flag s_frame_cleared <= '0'; diff --git a/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/TESTBENCH/testbench_top.vhd b/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/TESTBENCH/testbench_top.vhd index d250733f1..1190d34ee 100644 --- a/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/TESTBENCH/testbench_top.vhd +++ b/FPGA_Developments/Synchronization_COMM/Development/Synchronization_COMM/TESTBENCH/testbench_top.vhd @@ -116,7 +116,8 @@ begin s_sync <= '1'; v_sync_high := '1'; v_sync_div_cnt := 0; - elsif ((v_sync_high = '1') and (v_sync_div_cnt = 45000)) then +-- elsif ((v_sync_high = '1') and (v_sync_div_cnt = 45000)) then + elsif ((v_sync_high = '1') and (v_sync_div_cnt = 10000)) then s_sync <= '0'; v_sync_high := '0'; -- v_sync_one_shot := '1'; -- comment this line to remove one-shot