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Dooz.eda.rpt
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Dooz.eda.rpt
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EDA Netlist Writer report for Dooz
Sat Dec 14 11:50:01 2019
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Timing Analysis Settings
4. Timing Analysis Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+--------------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sat Dec 14 11:50:01 2019 ;
; Revision Name ; Dooz ;
; Top-level Entity Name ; Dooz ;
; Family ; MAX II ;
; Timing Analysis Files Creation ; Successful ;
+--------------------------------+---------------------------------------+
+-----------------------------------------------------------+
; Timing Analysis Settings ;
+-------------------------------------+---------------------+
; Option ; Setting ;
+-------------------------------------+---------------------+
; Tool Name ; PrimeTime (Verilog) ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
+-------------------------------------+---------------------+
+---------------------------------------------+
; Timing Analysis Generated Files ;
+---------------------------------------------+
; Generated Files ;
+---------------------------------------------+
; J:/fpga/dooz/timing/primetime/Dooz.vo ;
; J:/fpga/dooz/timing/primetime/Dooz_v.sdo ;
; J:/fpga/dooz/timing/primetime/Dooz_pt_v.tcl ;
+---------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Dec 14 11:50:01 2019
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Dooz -c Dooz
Info: Generated files "Dooz.vo" and "Dooz_v.sdo" in directory "J:/fpga/dooz/timing/primetime/" for EDA timing analysis tool
Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
Info: Generated PrimeTime Tcl script file J:/fpga/dooz/timing/primetime/Dooz_pt_v.tcl
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 166 megabytes
Info: Processing ended: Sat Dec 14 11:50:02 2019
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00