From 4bf9ef39568057363e4570f1706c140fb1e51c26 Mon Sep 17 00:00:00 2001
From: yulightenyu <145419941+yulightenyu@users.noreply.github.com>
Date: Fri, 25 Oct 2024 17:34:15 +0800
Subject: [PATCH] fix: change CHIAsyncQueueBridge depth to 16 (#3768)

To support maximum number of L-Credits defined in CHI.IssueE.b.14.2.1
---
 src/main/scala/system/SoC.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/system/SoC.scala b/src/main/scala/system/SoC.scala
index a979ebcb27..8a239d895e 100644
--- a/src/main/scala/system/SoC.scala
+++ b/src/main/scala/system/SoC.scala
@@ -67,7 +67,7 @@ case class SoCParameters
   NumIRSrc: Int = 256,
   UseXSNoCTop: Boolean = false,
   IMSICUseTL: Boolean = false,
-  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 4, sync = 3, safe = false)),
+  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
   EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
 ){
   // L3 configurations