From c56439083caa78c08c2993614f1d0e53b2ecf043 Mon Sep 17 00:00:00 2001
From: lihuijin <501296508@qq.com>
Date: Tue, 8 Oct 2024 18:19:46 +0800
Subject: [PATCH] area(LoadQueueReplay): optimise
 exceptionVec(loadAddrMisaligned)

---
 src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
index a6e7b147e2..f8c7f8f65e 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
@@ -535,6 +535,7 @@ class LoadQueueReplay(implicit p: Parameters) extends XSModule
     replay_req(i).valid             := s2_oldestSel(i).valid
     replay_req(i).bits              := DontCare
     replay_req(i).bits.uop          := s2_replayUop
+    replay_req(i).bits.uop.exceptionVec(loadAddrMisaligned) := false.B
     replay_req(i).bits.isvec        := s2_vecReplay.isvec
     replay_req(i).bits.isLastElem   := s2_vecReplay.isLastElem
     replay_req(i).bits.is128bit     := s2_vecReplay.is128bit