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多谢解答,我在看下代码,所以目前xiangshan 验证无论是soc 级别还是模块级别都是用业界的方式,生成verilog 然后用difftest/uvm的testbench 来做对吧. 另外想问下chiseltest 是有什么弊端吗,好像用的都不多 |
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多谢解答,我在看下代码,所以目前xiangshan 验证无论是soc 级别还是模块级别都是用业界的方式,生成verilog 然后用difftest/uvm的testbench 来做对吧. 另外想问下chiseltest 是有什么弊端吗,好像用的都不多 |
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目前香山流程如果验证出design bug 需要从verilog 对应到chisel后改chisel 然后重新生成verilog 后在有后续验证,这样是否会不方便,特别是使用foreach/map 这些循环生成的verilog |
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目前只有huancun子模块有单元测试吗?其他子模块都是基于difftest的验证?
另外请教下关于dual core的验证环境,测试代码分别为每个core 准备吗? difftest 需要做哪些修改?
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