Welcome to XiangShan Discussions!

[poemonsense]

👋 Welcome!

We’re using Discussions as a place to connect with other members of our community. We hope that you:

• Ask questions you’re wondering about.
• Share ideas.
• Engage with other community members.
• Welcome others and are open-minded. Remember that this is a community we
  build together 💪.

To get started, comment below with an introduction of yourself and tell us about what you do with this community.

[michael-etzkorn]

Hi Everyone!

My name is Michael Etzkorn. I'm a recent graduate from the University of Illinois majoring in Computer Engineering. I still feel uncomfortable tracking the inheritance of objects and utilizing the libraries of Chisel, but I feel it to be a powerful improvement over SystemVerilog and it's still continuing to grow. I hope to continue analyzing RISCV cores and learn how to utilize Chisel to connect SoCs seamlessly. My principal focus at the moment is analyzing Chipyard's repo, but I hope to improve my understanding of computer architecture and someday make contributions here. I also hope to help improve and utilize Chisel's verification capabilities. Perhaps making it easier to connect it to existing frameworks like UVM.

我也会说中文！学而不厌，继续加油 😄