From be9f99e06df7b3c93e0b1e8092b0d4dad419b697 Mon Sep 17 00:00:00 2001
From: "Matthias J. Kannwischer" <matthias@kannwischer.eu>
Date: Wed, 30 Oct 2024 15:51:52 +0800
Subject: [PATCH] fetch_int -> from_integer; integer_representation ->
 to_integer

sage deprecated fetch_int and integer_representation in vesion 3.9:
https://www.sagemath.org/changelogs/sage-9.8.txt.

We should switch to from_integer to_integer.
Thanks yx7
---
 utilities.sage | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/utilities.sage b/utilities.sage
index ca5462a..02cbc16 100644
--- a/utilities.sage
+++ b/utilities.sage
@@ -10,7 +10,7 @@ implode_dict = { explode_table[i]:i for i in range(256)}
 
 def decode_vec(t, l):
     t = [(t[i//2] >> i % 2 * 4) & 0xf for i in range(2 * len(t))]
-    v = vector(map(F16.fetch_int, t))
+    v = vector(map(F16.from_integer, t))
 
     if l % 2 == 1:
         v = v[:-1]
@@ -21,8 +21,8 @@ def encode_vec(v):
         v  = vector(F16, v.list() + [ F16(0) ])
     bs = []
     for i in range(len(v)//2):
-        bs += [v[i*2].integer_representation() |
-               (v[i*2 + 1].integer_representation() << 4)]
+        bs += [v[i*2].to_integer() |
+               (v[i*2 + 1].to_integer() << 4)]
     return bytes(bs)
 
 def decode_matrix(t, rows, columns):
@@ -182,7 +182,7 @@ def bitsliced_add(veca, vecb):
 def bitsliced_mul_add(In, a, Out):
     In0, In1, In2, In3 = In
     Out0, Out1, Out2, Out3 = Out
-    a_int = a.integer_representation()
+    a_int = a.to_integer()
 
     if a_int & 1:
         Out0 ^^= In0