diff --git a/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v b/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
index 24ade5748..52b0b53fe 100644
--- a/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
+++ b/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
@@ -165,41 +165,7 @@ module iob_soc_fpga_wrapper (
.memory_mem_dqs_n (ddr3b_dqs_n),
.memory_mem_odt (ddr3b_odt),
- .axi_bridge_0_s0_awid (memory_axi_awid),
- .axi_bridge_0_s0_awaddr (memory_axi_awaddr),
- .axi_bridge_0_s0_awlen (memory_axi_awlen),
- .axi_bridge_0_s0_awsize (memory_axi_awsize),
- .axi_bridge_0_s0_awburst(memory_axi_awburst),
- .axi_bridge_0_s0_awlock (memory_axi_awlock),
- .axi_bridge_0_s0_awcache(memory_axi_awcache),
- .axi_bridge_0_s0_awprot (memory_axi_awprot),
- .axi_bridge_0_s0_awvalid(memory_axi_awvalid),
- .axi_bridge_0_s0_awready(memory_axi_awready),
- .axi_bridge_0_s0_wdata (memory_axi_wdata),
- .axi_bridge_0_s0_wstrb (memory_axi_wstrb),
- .axi_bridge_0_s0_wlast (memory_axi_wlast),
- .axi_bridge_0_s0_wvalid (memory_axi_wvalid),
- .axi_bridge_0_s0_wready (memory_axi_wready),
- .axi_bridge_0_s0_bid (memory_axi_bid),
- .axi_bridge_0_s0_bresp (memory_axi_bresp),
- .axi_bridge_0_s0_bvalid (memory_axi_bvalid),
- .axi_bridge_0_s0_bready (memory_axi_bready),
- .axi_bridge_0_s0_arid (memory_axi_arid),
- .axi_bridge_0_s0_araddr (memory_axi_araddr),
- .axi_bridge_0_s0_arlen (memory_axi_arlen),
- .axi_bridge_0_s0_arsize (memory_axi_arsize),
- .axi_bridge_0_s0_arburst(memory_axi_arburst),
- .axi_bridge_0_s0_arlock (memory_axi_arlock),
- .axi_bridge_0_s0_arcache(memory_axi_arcache),
- .axi_bridge_0_s0_arprot (memory_axi_arprot),
- .axi_bridge_0_s0_arvalid(memory_axi_arvalid),
- .axi_bridge_0_s0_arready(memory_axi_arready),
- .axi_bridge_0_s0_rid (memory_axi_rid),
- .axi_bridge_0_s0_rdata (memory_axi_rdata),
- .axi_bridge_0_s0_rresp (memory_axi_rresp),
- .axi_bridge_0_s0_rlast (memory_axi_rlast),
- .axi_bridge_0_s0_rvalid (memory_axi_rvalid),
- .axi_bridge_0_s0_rready (memory_axi_rready),
+ `include "iob_soc_cyclonev_interconnect_s_portmap.vs"
.mem_if_ddr3_emif_0_pll_sharing_pll_mem_clk (),
.mem_if_ddr3_emif_0_pll_sharing_pll_write_clk (),
@@ -224,14 +190,4 @@ module iob_soc_fpga_wrapper (
);
`endif
-`ifdef IOB_SOC_USE_EXTMEM
- // interconnect clk and arst
- wire clk_interconnect;
- wire arst_interconnect;
- assign clk_interconnect = clk;
- assign arst_interconnect = arst;
-`endif
-
- `include "iob_soc_interconnect.vs"
-
endmodule
diff --git a/iob_soc.py b/iob_soc.py
index 66d4f57ba..c25f1d605 100755
--- a/iob_soc.py
+++ b/iob_soc.py
@@ -39,6 +39,7 @@ class iob_soc(iob_module):
name = "iob_soc"
version = "V0.70"
setup_dir = os.path.dirname(__file__)
+ rw_overlap = True
# IOb-SoC has the following list of non standard attributes:
peripherals = None # List with instances peripherals to include in system
diff --git a/scripts/iob_soc_create_wrapper_files.py b/scripts/iob_soc_create_wrapper_files.py
index 96cf5ba24..3e9034d7e 100755
--- a/scripts/iob_soc_create_wrapper_files.py
+++ b/scripts/iob_soc_create_wrapper_files.py
@@ -80,6 +80,11 @@ def create_wrapper_files(build_dir, name, ios, confs, num_extmem_connections):
fd_pportmaps.close()
create_interconnect_instance(out_dir, name, num_extmem_connections)
+ create_cyclonev_interconnect_s_portmap(out_dir, name, num_extmem_connections)
+ modify_alt_ddr3_qsys(
+ os.path.join(build_dir, f"hardware/fpga/quartus/CYCLONEV-GT-DK/alt_ddr3.qsys"),
+ num_extmem_connections,
+ )
create_ku040_interconnect_s_portmap(out_dir, name, num_extmem_connections)
create_ku040_rstn(out_dir, name, num_extmem_connections)
@@ -284,3 +289,203 @@ def create_ku040_interconnect_s_portmap(out_dir, name, num_extmem_connections):
fp_interconnect = open(f"{out_dir}/{name}_ku040_interconnect_s_portmap.vs", "w")
fp_interconnect.write(interconnect_str)
fp_interconnect.close()
+
+
+def create_cyclonev_interconnect_s_portmap(out_dir, name, num_extmem_connections):
+ interconnect_str = ""
+ for i in range(num_extmem_connections):
+ interconnect_str += f"""
+ //
+ // External memory connection {i}
+ //
+
+ //Write address
+ .axi_bridge_{i}_s0_awid (axi_awid[{i}*AXI_ID_W+:1]),
+ .axi_bridge_{i}_s0_awaddr (axi_awaddr[{i}*AXI_ADDR_W+:AXI_ADDR_W]),
+ .axi_bridge_{i}_s0_awlen (axi_awlen[{i}*AXI_LEN_W+:AXI_LEN_W]),
+ .axi_bridge_{i}_s0_awsize (axi_awsize[{i}*3+:3]),
+ .axi_bridge_{i}_s0_awburst(axi_awburst[{i}*2+:2]),
+ .axi_bridge_{i}_s0_awlock (axi_awlock[{i}*2+:1]),
+ .axi_bridge_{i}_s0_awcache(axi_awcache[{i}*4+:4]),
+ .axi_bridge_{i}_s0_awprot (axi_awprot[{i}*3+:3]),
+ .axi_bridge_{i}_s0_awvalid(axi_awvalid[{i}*1+:1]),
+ .axi_bridge_{i}_s0_awready(axi_awready[{i}*1+:1]),
+
+ //Write data
+ .axi_bridge_{i}_s0_wdata (axi_wdata[{i}*AXI_DATA_W+:AXI_DATA_W]),
+ .axi_bridge_{i}_s0_wstrb (axi_wstrb[{i}*(AXI_DATA_W/8)+:(AXI_DATA_W/8)]),
+ .axi_bridge_{i}_s0_wlast (axi_wlast[{i}*1+:1]),
+ .axi_bridge_{i}_s0_wvalid (axi_wvalid[{i}*1+:1]),
+ .axi_bridge_{i}_s0_wready (axi_wready[{i}*1+:1]),
+
+ //Write response
+ .axi_bridge_{i}_s0_bid (axi_bid[{i}*AXI_ID_W+:1]),
+ .axi_bridge_{i}_s0_bresp (axi_bresp[{i}*2+:2]),
+ .axi_bridge_{i}_s0_bvalid (axi_bvalid[{i}*1+:1]),
+ .axi_bridge_{i}_s0_bready (axi_bready[{i}*1+:1]),
+
+ //Read address
+ .axi_bridge_{i}_s0_arid (axi_arid[{i}*AXI_ID_W+:1]),
+ .axi_bridge_{i}_s0_araddr (axi_araddr[{i}*AXI_ADDR_W+:AXI_ADDR_W]),
+ .axi_bridge_{i}_s0_arlen (axi_arlen[{i}*AXI_LEN_W+:AXI_LEN_W]),
+ .axi_bridge_{i}_s0_arsize (axi_arsize[{i}*3+:3]),
+ .axi_bridge_{i}_s0_arburst(axi_arburst[{i}*2+:2]),
+ .axi_bridge_{i}_s0_arlock (axi_arlock[{i}*2+:1]),
+ .axi_bridge_{i}_s0_arcache(axi_arcache[{i}*4+:4]),
+ .axi_bridge_{i}_s0_arprot (axi_arprot[{i}*3+:3]),
+ .axi_bridge_{i}_s0_arvalid(axi_arvalid[{i}*1+:1]),
+ .axi_bridge_{i}_s0_arready(axi_arready[{i}*1+:1]),
+
+ //Read data
+ .axi_bridge_{i}_s0_rid (axi_rid[{i}*AXI_ID_W+:1]),
+ .axi_bridge_{i}_s0_rdata (axi_rdata[{i}*AXI_DATA_W+:AXI_DATA_W]),
+ .axi_bridge_{i}_s0_rresp (axi_rresp[{i}*2+:2]),
+ .axi_bridge_{i}_s0_rlast (axi_rlast[{i}*1+:1]),
+ .axi_bridge_{i}_s0_rvalid (axi_rvalid[{i}*1+:1]),
+ .axi_bridge_{i}_s0_rready (axi_rready[{i}*1+:1]),
+
+"""
+
+ fp_interconnect = open(f"{out_dir}/{name}_cyclonev_interconnect_s_portmap.vs", "w")
+ fp_interconnect.write(interconnect_str)
+ fp_interconnect.close()
+
+
+# Add slave ports to alt_ddr3.qsys, based on number of extmem connections
+def modify_alt_ddr3_qsys(qsys_path, num_extmem_connections):
+ with open(qsys_path, "r") as f:
+ lines = f.readlines()
+ new_lines = []
+
+ for line in lines:
+ new_lines.append(line)
+ if "element clk_0" in line:
+ for i in range(1, num_extmem_connections):
+ new_lines.insert(-1,
+ f"""
+ element axi_bridge_{i}
+ {{
+ datum _sortIndex
+ {{
+ value = "{i+2}";
+ type = "int";
+ }}
+ }}
+ \n""",
+ )
+ elif 'interface name="clk"' in line:
+ for i in range(1, num_extmem_connections):
+ new_lines.insert(-1,
+ f"""
+
+ \n""",
+ )
+ elif 'module name="clk_0"' in line:
+ for i in range(1, num_extmem_connections):
+ new_lines.insert(-1,
+ f"""
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ \n""",
+ )
+ elif 'end="axi_bridge_0.clk"' in line:
+ for i in range(1, num_extmem_connections):
+ new_lines.insert(-1,
+ f"""
+
+
+
+
+
+
+ \n""",
+ )
+ elif 'name="qsys_mm.clockCrossingAdapter"' in line:
+ for i in range(1, num_extmem_connections):
+ new_lines.insert(-1,
+ f"""
+
+ \n""",
+ )
+
+ with open(qsys_path, "w") as f:
+ f.writelines(new_lines)
diff --git a/scripts/iob_soc_utils.py b/scripts/iob_soc_utils.py
index 9b5a800d8..a3dea8afa 100755
--- a/scripts/iob_soc_utils.py
+++ b/scripts/iob_soc_utils.py
@@ -192,7 +192,6 @@ def post_setup_iob_soc(python_module, num_extmem_connections):
name = python_module.name
# Run iob-soc specialized setup sequence
- iob_soc_wrapper_setup(python_module, num_extmem_connections)
iob_soc_sw_setup(python_module)
iob_soc_hw_setup(python_module)
iob_soc_doc_setup(python_module)
@@ -201,6 +200,8 @@ def post_setup_iob_soc(python_module, num_extmem_connections):
return
### Only run lines below if this system is the top module ###
+ iob_soc_wrapper_setup(python_module, num_extmem_connections)
+
# Check if was setup with INIT_MEM and USE_EXTMEM (check if macro exists)
extmem_macro = bool(
next((i["val"] for i in confs if i["name"] == "USE_EXTMEM"), False)
diff --git a/submodules/LIB/hardware/modules/fifo/iob_fifo_async/hardware/src/iob_fifo_async.v b/submodules/LIB/hardware/modules/fifo/iob_fifo_async/hardware/src/iob_fifo_async.v
index 0b61ea9b5..066c5ed03 100644
--- a/submodules/LIB/hardware/modules/fifo/iob_fifo_async/hardware/src/iob_fifo_async.v
+++ b/submodules/LIB/hardware/modules/fifo/iob_fifo_async/hardware/src/iob_fifo_async.v
@@ -215,6 +215,7 @@ module iob_fifo_async #(
.clk_i (r_clk_i),
.cke_i (r_cke_i),
.arst_i (r_arst_i),
+ .rst_i (r_rst_i),
.w_addr_i (w_addr),
.w_en_i (w_en_int),
.w_data_i (w_data_i),
diff --git a/submodules/LIB/hardware/modules/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v b/submodules/LIB/hardware/modules/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v
index fc8cb9b88..047709e5a 100644
--- a/submodules/LIB/hardware/modules/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v
+++ b/submodules/LIB/hardware/modules/fifo/iob_fifo_sync/hardware/src/iob_fifo_sync.v
@@ -117,12 +117,12 @@ module iob_fifo_sync #(
//FIFO empty
wire r_empty_nxt;
assign r_empty_nxt = level_nxt < {1'b0,R_INCR};
- iob_reg #(
+ iob_reg_r #(
.DATA_W (1),
.RST_VAL(1'd1)
) r_empty_reg0 (
`include "clk_en_rst_s_s_portmap.vs"
-
+ .rst_i(rst_i),
.data_i(r_empty_nxt),
.data_o(r_empty_o)
);
@@ -130,12 +130,12 @@ module iob_fifo_sync #(
//FIFO full
wire w_full_nxt;
assign w_full_nxt = level_nxt > (FIFO_SIZE - W_INCR);
- iob_reg #(
+ iob_reg_r #(
.DATA_W (1),
.RST_VAL(1'd0)
) w_full_reg0 (
`include "clk_en_rst_s_s_portmap.vs"
-
+ .rst_i(rst_i),
.data_i(w_full_nxt),
.data_o(w_full_o)
);
@@ -154,6 +154,7 @@ module iob_fifo_sync #(
.ext_mem_r_addr_o(ext_mem_r_addr_o),
.ext_mem_r_data_i(ext_mem_r_data_i),
`include "clk_en_rst_s_s_portmap.vs"
+ .rst_i(rst_i),
.w_addr_i (w_addr),
.w_en_i (w_en_int),
.w_data_i (w_data_i),
diff --git a/submodules/LIB/hardware/modules/asym_converter/hardware/src/iob_asym_converter.v b/submodules/LIB/hardware/modules/iob_asym_converter/hardware/src/iob_asym_converter.v
similarity index 88%
rename from submodules/LIB/hardware/modules/asym_converter/hardware/src/iob_asym_converter.v
rename to submodules/LIB/hardware/modules/iob_asym_converter/hardware/src/iob_asym_converter.v
index 4fb991ed0..203346287 100644
--- a/submodules/LIB/hardware/modules/asym_converter/hardware/src/iob_asym_converter.v
+++ b/submodules/LIB/hardware/modules/iob_asym_converter/hardware/src/iob_asym_converter.v
@@ -14,42 +14,45 @@ module iob_asym_converter #(
parameter R_ADDR_W = (R_DATA_W == MAXDATA_W) ? MINADDR_W : ADDR_W
) (
//memory write port
- output [ R-1:0] ext_mem_w_en_o,
+ output [ R-1:0] ext_mem_w_en_o,
output [MINADDR_W-1:0] ext_mem_w_addr_o,
output [MAXDATA_W-1:0] ext_mem_w_data_o,
//memory read port
- output [ R-1:0] ext_mem_r_en_o,
+ output [ R-1:0] ext_mem_r_en_o,
output [MINADDR_W-1:0] ext_mem_r_addr_o,
- input [MAXDATA_W-1:0] ext_mem_r_data_i,
- `include "clk_en_rst_s_port.vs"
+ input [MAXDATA_W-1:0] ext_mem_r_data_i,
+`include "clk_en_rst_s_port.vs"
+ input rst_i,
//write port
- input [ W_ADDR_W-1:0] w_addr_i,
+ input [ W_ADDR_W-1:0] w_addr_i,
input w_en_i,
- input [ W_DATA_W-1:0] w_data_i,
+ input [ W_DATA_W-1:0] w_data_i,
//read port
- input [ R_ADDR_W-1:0] r_addr_i,
+ input [ R_ADDR_W-1:0] r_addr_i,
input r_en_i,
output [ R_DATA_W-1:0] r_data_o
);
//Data is valid after read enable
wire r_data_valid_reg;
- iob_reg #(
+ iob_reg_r #(
.DATA_W (1),
.RST_VAL(1'b0)
) r_data_valid_reg_inst (
- `include "clk_en_rst_s_s_portmap.vs"
+`include "clk_en_rst_s_s_portmap.vs"
+ .rst_i (rst_i),
.data_i(r_en_i),
.data_o(r_data_valid_reg)
);
//Register read data from the memory
wire [MAXDATA_W-1:0] r_data_reg;
- iob_reg_e #(
+ iob_reg_re #(
.DATA_W (MAXDATA_W),
.RST_VAL({MAXDATA_W{1'd0}})
) r_data_reg_inst (
- `include "clk_en_rst_s_s_portmap.vs"
+`include "clk_en_rst_s_s_portmap.vs"
+ .rst_i (rst_i),
.en_i (r_data_valid_reg),
.data_i(ext_mem_r_data_i),
.data_o(r_data_reg)
diff --git a/submodules/LIB/hardware/modules/asym_converter/iob_asym_converter.py b/submodules/LIB/hardware/modules/iob_asym_converter/iob_asym_converter.py
similarity index 82%
rename from submodules/LIB/hardware/modules/asym_converter/iob_asym_converter.py
rename to submodules/LIB/hardware/modules/iob_asym_converter/iob_asym_converter.py
index 4fc68cc24..19a4c4e78 100644
--- a/submodules/LIB/hardware/modules/asym_converter/iob_asym_converter.py
+++ b/submodules/LIB/hardware/modules/iob_asym_converter/iob_asym_converter.py
@@ -1,7 +1,8 @@
import os
from iob_module import iob_module
-from iob_reg_e import iob_reg_e
+from iob_reg_r import iob_reg_r
+from iob_reg_re import iob_reg_re
from iob_utils import iob_utils
@@ -17,7 +18,8 @@ def _create_submodules_list(cls):
[
{"interface": "clk_en_rst_s_s_portmap"},
{"interface": "clk_en_rst_s_port"},
- iob_reg_e,
+ iob_reg_r,
+ iob_reg_re,
iob_utils,
]
)
diff --git a/submodules/LIB/scripts/iob_module.py b/submodules/LIB/scripts/iob_module.py
index 62c30f852..11d94c99e 100644
--- a/submodules/LIB/scripts/iob_module.py
+++ b/submodules/LIB/scripts/iob_module.py
@@ -30,7 +30,7 @@ class iob_module:
build_dir = "" # Build directory for this module
confs = None # List of configuration macros/parameters for this module
autoaddr = True # register address mode: True: automatic; False: manual
- rw_overlap = True # overlap Read and Write register addresses
+ rw_overlap = False # overlap Read and Write register addresses
regs = None # List of registers for this module
ios = None # List of I/O for this module
block_groups = None # List of block groups for this module. Used for documentation.
diff --git a/submodules/UART/iob_uart.py b/submodules/UART/iob_uart.py
index 455ca3fc9..825fc5781 100755
--- a/submodules/UART/iob_uart.py
+++ b/submodules/UART/iob_uart.py
@@ -14,6 +14,7 @@ class iob_uart(iob_module):
name = "iob_uart"
version = "V0.10"
setup_dir = os.path.dirname(__file__)
+ rw_overlap = True
@classmethod
def _create_submodules_list(cls):