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O7ARMv6MG.Mod
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O7ARMv6MG.Mod
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MODULE O7ARMv6MG; (* NW 18.4.2016 / 31.5.2019 code generator in Oberon-07 for RISC*)
(* Modified for ARMv6-M by A. V. Shiryaev, 2016.05.07, 2019.10.21, 2023.06.21 *)
(*
http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC-Arch.pdf
ARMv6-M Architecture Reference Manual
http://ecee.colorado.edu/ecen3000/labs/lab3/files/DDI0419C_arm_architecture_v6m_reference_manual.pdf
*)
(*
TODO:
LEN(record.arrayOfChar):
Reg Stack
invalid code generated when no Reg Stack compile-time error
implement "special feautures" (see RISC-Arch.pdf, section 4):
implement MOV+U F0, c = 1 feature? save flags to register
when it's required?
MRS instruction
check loadCond (IsFlagsUp0 related)
implement LDPSR
see PO.Applications.pdf, p. 47
shifts...
implementation limits:
long B branches: use BX
optimizations:
optimize MovIm (3-4 instr-s)
arrays assignment (see PO.Applications.pdf, 45):
use special command instead of loop
bits:
SYSTEM.BIT(adr, bit)
...
register procedures https://github.com/aixp/ProjectOberon2013/commit/873fe7ef74a2c41592f9904ad7c3893e4a368d58
*)
IMPORT SYSTEM, Files, ORS := O7S, ORB := O7B, ARMv6M := O7ARMv6M;
(*Code generator for Oberon compiler for RISC processor.
Procedural interface to Parser OSAP; result in array "code".
Procedure Close writes code-files*)
TYPE
LONGINT = INTEGER;
BYTE = CHAR;
CONST WordSize* = 4;
parblksize0Proc* = 0; parblksize0Int* = 0;
(* MT = 12; SB = 13; SP = 14; LNK = 15; (*dedicated registers*) *)
MT = 6; SB = 7; SP = ARMv6M.SP; LNK = ARMv6M.LR;
maxCode = 8000; maxStrx = 2400; maxTD = 160; C24 = 1000000H;
Reg = 10; RegI = 11; Cond = 12; (*internal item modes*)
(*frequently used opcodes*) U = 2000H; V = 1000H;
Mov = 0; Lsl = 1; Asr = 2; Ror= 3; And = 4; Ann = 5; Ior = 6; Xor = 7;
Add = 8; Sub = 9; Cmp = 9; Mul = 10; Div = 11;
Fad = 12; Fsb = 13; Fml = 14; Fdv = 15;
Ldr = 8; Str = 10;
BR = 0; BLR = 1; BC = 2; BL = 3;
MI = 0; PL = 8; EQ = 1; NE = 9; LT = 5; GE = 13; LE = 6; GT = 14;
TYPE Item* = RECORD
mode*: INTEGER;
type*: ORB.Type;
a-, b-, r: LONGINT;
rdo-: BOOLEAN (*read only*)
END ;
(* Item forms and meaning of fields:
mode r a b
--------------------------------
Const - value (proc adr) (immediate value)
Var base off - (direct adr)
Par - off0 off1 (indirect adr)
Reg regno
RegI regno off -
Cond cond Fchain Tchain *)
VAR pc-, varsize: LONGINT; (*program counter, data index*)
tdx, strx: LONGINT;
entry: LONGINT; (*main entry point*)
RH: LONGINT; (*available registers R[0] ... R[H-1]*)
curSB: LONGINT; (*current static base in SB*)
frame: LONGINT; (*frame offset changed in SaveRegs and RestoreRegs*)
fixorgP, fixorgD, fixorgT: LONGINT; (*origins of lists of locations to be fixed up by loader*)
check: BOOLEAN; (*emit run-time checks*)
version: INTEGER; (* 0 = RISC-0, 1 = RISC-5 *)
relmap: ARRAY 6 OF INTEGER; (*condition codes for relations*)
armcode: ARRAY maxCode OF LONGINT;
data: ARRAY maxTD OF LONGINT; (*type descriptors*)
str: ARRAY maxStrx OF CHAR;
RM: SET; (* registers modified *)
enterPushFixup: INTEGER;
PROCEDURE BITS (x: INTEGER): SET;
BEGIN
RETURN SYSTEM.VAL(SET, x)
END BITS;
PROCEDURE ORDSET (x: SET): INTEGER;
BEGIN
RETURN SYSTEM.VAL(INTEGER, x)
END ORDSET;
PROCEDURE LSL (x, n: INTEGER): INTEGER;
BEGIN RETURN SYSTEM.LSH(x, n)
END LSL;
(*instruction assemblers according to formats*)
(* encode register *)
PROCEDURE ER (a: INTEGER): INTEGER;
BEGIN
IF a = SB THEN RETURN 3
ELSIF a = 3 THEN RETURN SB
ELSE RETURN a
END
END ER;
PROCEDURE ERs (s: SET): SET;
VAR r: SET; i: INTEGER;
BEGIN
r := {}; i := 0;
WHILE i < 10H DO
IF i IN s THEN INCL(r, ER(i)) END;
INC(i)
END;
RETURN r
END ERs;
(* decode register *)
PROCEDURE DR (a: INTEGER): INTEGER;
BEGIN
IF a = SB THEN RETURN 3
ELSIF a = 3 THEN RETURN SB
ELSE RETURN a
END
END DR;
PROCEDURE UpdateFlags (a: INTEGER);
BEGIN
ARMv6M.EmitCMPIm(armcode, pc, ER(a), 0)
END UpdateFlags;
(* emit RSBS a, a, #0 *)
PROCEDURE RSBS0 (a: INTEGER);
BEGIN
INCL(RM, a);
a := ER(a);
ARMv6M.EmitRSBS0(armcode, pc, a, a)
END RSBS0;
(* A6.7.17 *)
PROCEDURE IsCMPIm (c: INTEGER): BOOLEAN;
BEGIN
RETURN c DIV 800H = 5
END IsCMPIm;
PROCEDURE RemoveRedundantCmp;
BEGIN
IF (pc >= 2) & ~ARMv6M.IsLThumb32(armcode[pc - 2]) & IsCMPIm(armcode[pc - 1]) THEN DEC(pc) END
END RemoveRedundantCmp;
(* op # Mov: R.a := R.b op R.c; op = Mov: R.a := R.c *)
(* S=1: change NZCV according R.a after *)
PROCEDURE Put00 (S: INTEGER; op, a, b, c: LONGINT);
VAR u, v: BOOLEAN;
r: INTEGER;
BEGIN (*emit format-0 instruction
code[pc] := ((a*10H + b) * 10H + op) * 10000H + c; *)
ASSERT(S IN {0,1}, 20);
IF ORS.errcnt = 0 THEN
u := 13 IN BITS(op);
IF u THEN DEC(op, U) END;
v := 12 IN BITS(op);
IF v THEN DEC(op, V) END;
ASSERT(op DIV 10H = 0, 21);
ASSERT(a DIV 10H = 0, 22);
ASSERT(b DIV 10H = 0, 23);
ASSERT(c DIV 10H = 0, 24);
INCL(RM, a);
IF ~((op IN {Add,Sub}) & u) THEN RemoveRedundantCmp END;
CASE op MOD 10H OF Mov: (* R.a := R.c *)
ASSERT(~v, 100);
IF ~u THEN
IF c = SP THEN
ARMv6M.EmitADDSPIm(armcode, pc, ER(a), 0);
IF S = 1 THEN UpdateFlags(a) END
ELSIF c = LNK THEN
ARMv6M.EmitPUSH(armcode, pc, {LNK});
ARMv6M.EmitPOP(armcode, pc, {ER(a)});
IF S = 1 THEN UpdateFlags(a) END
ELSE
ARMv6M.EmitMOVSR(armcode, pc, ER(a), ER(c))
END
ELSE
ASSERT(b = 0, 101);
ASSERT(c IN {0,1}, 102);
IF c = 0 THEN
HALT(103)
ELSE (* c = 1 *)
HALT(126) (* TODO *)
END
END
| Lsl: (* R.a := R.b <- R.c *)
ASSERT(~u, 104);
ASSERT(~v, 105);
IF a = b THEN
ARMv6M.EmitLSLSR(armcode, pc, ER(a), ER(c))
ELSIF a # c THEN
Put00(0, Mov, a, 0, b);
ARMv6M.EmitLSLSR(armcode, pc, ER(a), ER(c))
ELSE (* R.a := R.b <- R.a *)
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
IF (b < MT) & (r <= b) THEN r := b + 1 END;
ASSERT(r < MT, 100);
Put00(0, Mov, r, 0, a);
Put00(0, Mov, a, 0, b);
ARMv6M.EmitLSLSR(armcode, pc, ER(a), ER(r))
END
| Asr: (* R.a := R.b -> R.c *)
ASSERT(~u, 109);
ASSERT(~v, 110);
IF a = b THEN
ARMv6M.EmitASRSR(armcode, pc, ER(a), ER(c))
ELSIF a # c THEN
Put00(0, Mov, a, 0, b);
ARMv6M.EmitASRSR(armcode, pc, ER(a), ER(c))
ELSE (* R.a := R.b -> R.a *)
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
IF (b < MT) & (r <= b) THEN r := b + 1 END;
ASSERT(r < MT, 100);
Put00(0, Mov, r, 0, a);
Put00(0, Mov, a, 0, b);
ARMv6M.EmitASRSR(armcode, pc, ER(a), ER(r))
END
| Ror: (* R.a := R.b rot R.c *)
ASSERT(~u, 114);
ASSERT(~v, 115);
IF a = b THEN
ARMv6M.EmitRORSR(armcode, pc, ER(a), ER(c))
ELSIF a # c THEN
Put00(0, Mov, a, 0, b);
ARMv6M.EmitRORSR(armcode, pc, ER(a), ER(c))
ELSE (* R.a := R.b rot R.a *)
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
IF (b < MT) & (r <= b) THEN r := b + 1 END;
ASSERT(r < MT, 100);
Put00(0, Mov, r, 0, a);
Put00(0, Mov, a, 0, b);
ARMv6M.EmitRORSR(armcode, pc, ER(a), ER(r))
END
| And: (* R.a := R.b & R.c *)
ASSERT(~u, 119);
ASSERT(~v, 120);
IF a = b THEN
ARMv6M.EmitANDSR(armcode, pc, ER(a), ER(c))
ELSIF a = c THEN
ARMv6M.EmitANDSR(armcode, pc, ER(a), ER(b))
ELSIF b = c THEN HALT(1) (* R.a := R.b *)
ELSE
Put00(0, Mov, a, 0, b);
ARMv6M.EmitANDSR(armcode, pc, ER(a), ER(c))
END
| Ann: (* R.a := R.b & ~R.c *)
ASSERT(~u, 124);
ASSERT(~v, 125);
ASSERT(b # c, 100); (* in this case, emit R.a := 0 *)
IF a = b THEN (* R.a := R.a & ~R.c *)
ARMv6M.EmitBICSR(armcode, pc, ER(a), ER(c))
ELSIF a # c THEN
Put00(0, Mov, a, 0, b);
ARMv6M.EmitBICSR(armcode, pc, ER(a), ER(c))
ELSE (* R.a := R.b & ~R.a *)
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
IF (b < MT) & (r <= b) THEN r := b + 1 END;
ASSERT(r < MT, 100);
Put00(0, Mov, r, 0, a);
Put00(0, Mov, a, 0, b);
ARMv6M.EmitBICSR(armcode, pc, ER(a), ER(r))
END
| Ior: (* R.a := R.b or R.c *)
ASSERT(~u, 104);
ASSERT(~v, 105);
IF a = b THEN
ARMv6M.EmitORRSR(armcode, pc, ER(a), ER(c))
ELSIF a = c THEN
ARMv6M.EmitORRSR(armcode, pc, ER(a), ER(b))
ELSIF b = c THEN HALT(1) (* R.a := R.b *)
ELSE
Put00(0, Mov, a, 0, b);
ARMv6M.EmitORRSR(armcode, pc, ER(a), ER(c))
END
| Xor: (* R.a := R.b xor R.c *)
ASSERT(~u, 109);
ASSERT(~v, 110);
IF a = b THEN
ARMv6M.EmitEORSR(armcode, pc, ER(a), ER(c))
ELSIF a = c THEN
ARMv6M.EmitEORSR(armcode, pc, ER(a), ER(b))
ELSIF b = c THEN HALT(1)
ELSE
Put00(0, Mov, a, 0, b);
ARMv6M.EmitEORSR(armcode, pc, ER(a), ER(c))
END
| Add: (* R.a := R.b + R.c *)
ASSERT(~v, 114);
IF ~u THEN
IF b = SP THEN
ARMv6M.EmitADDSPR(armcode, pc, ER(a), ER(c));
IF S = 1 THEN UpdateFlags(a) END
ELSIF c = SP THEN
ARMv6M.EmitADDSPR(armcode, pc, ER(a), ER(b));
IF S = 1 THEN UpdateFlags(a) END
ELSIF (ER(a) IN {0..7}) & (ER(b) IN {0..7}) & (ER(c) IN {0..7}) THEN
ARMv6M.EmitADDSR(armcode, pc, ER(a), ER(b), ER(c))
ELSIF a = b THEN
ARMv6M.EmitADDR(armcode, pc, ER(a), ER(c));
IF S = 1 THEN UpdateFlags(a) END
ELSIF a = c THEN
ARMv6M.EmitADDR(armcode, pc, ER(a), ER(b));
IF S = 1 THEN UpdateFlags(a) END
ELSE HALT(126)
END
ELSE (* with carry *)
IF a = b THEN
ARMv6M.EmitADCSR(armcode, pc, ER(a), ER(c))
ELSIF a = c THEN
ARMv6M.EmitADCSR(armcode, pc, ER(a), ER(b))
ELSE HALT(126)
END
END
| Sub: (* R.a := R.b - R.c *)
ASSERT(~v, 119);
IF ~u THEN
ARMv6M.EmitSUBSR(armcode, pc, ER(a), ER(b), ER(c))
ELSE (* with carry *)
ASSERT(a = b, 120);
ARMv6M.EmitSBCSR(armcode, pc, ER(a), ER(c))
END
| Mul: (* R.a := R.b * R.c *)
ASSERT(~v, 124);
IF ~u THEN
IF (a # b) & (a = c) THEN r := b; b := c; c := r END;
ASSERT(a = b, 126);
ARMv6M.EmitMULSR(armcode, pc, ER(a), ER(c))
ELSE
HALT(126)
END
| Div: (* R.a := R.b div R.c *)
ASSERT(~u, 103);
ASSERT(~v, 104);
ORS.Mark("not implemented")
| Fad,Fsb,Fml,Fdv:
ASSERT(~u, 108);
ASSERT(~v, 109);
ORS.Mark("not implemented")
END
END
END Put00;
PROCEDURE Put0 (op, a, b, c: INTEGER);
BEGIN
Put00(1, op, a, b, c)
END Put0;
(* R.a := im *)
(* NOTE: ARMv6MLinker.MovIm0 *)
PROCEDURE MovIm (S: INTEGER; a: INTEGER; im: INTEGER);
VAR shift: INTEGER;
BEGIN
ASSERT(S IN {0,1}, 20);
ASSERT(a IN {0..14}, 21);
INCL(RM, a);
IF a # SP THEN
shift := 0;
WHILE (shift < 32) & ~(
(SYSTEM.LSH(im, -shift) DIV 100H = 0)
& (im = SYSTEM.LSH(SYSTEM.LSH(im, -shift), shift))
) DO INC(shift)
END;
IF shift < 32 THEN
ARMv6M.EmitMOVSIm(armcode, pc, ER(a), SYSTEM.LSH(im, -shift));
IF shift # 0 THEN
ARMv6M.EmitLSLSIm(armcode, pc, ER(a), ER(a), shift)
END
ELSIF (im > 255) & (im <= 255 + 255) THEN
ARMv6M.EmitMOVSIm(armcode, pc, ER(a), 255);
ARMv6M.EmitADDSIm(armcode, pc, ER(a), ER(a), im - 255)
ELSIF (im >= -255) & (im < 0) THEN
ARMv6M.EmitMOVSIm(armcode, pc, ER(a), 0);
ARMv6M.EmitSUBSIm(armcode, pc, ER(a), ER(a), -im)
ELSE
shift := 8;
WHILE (shift < 32) & (SYSTEM.ROT(im DIV 100H * 100H, -shift) DIV 100H # 0) DO INC(shift) END;
IF shift < 32 THEN
ASSERT(im =
SYSTEM.LSH(SYSTEM.ROT(im DIV 100H * 100H, -shift), shift)
+ im MOD 100H);
ARMv6M.EmitMOVSIm(armcode, pc, ER(a), SYSTEM.ROT(im DIV 100H * 100H, -shift));
ARMv6M.EmitLSLSIm(armcode, pc, ER(a), ER(a), shift);
ARMv6M.EmitADDSIm(armcode, pc, ER(a), ER(a), im MOD 100H)
ELSE
(* TODO: 3 ops: mov; (add, lsl), (lsl, sub), (lsl, sub) *)
ARMv6M.EmitMOVSIm(armcode, pc, ER(a),
im DIV 1000000H MOD 100H);
IF im DIV 1000000H MOD 100H # 0 THEN
ARMv6M.EmitLSLSIm(armcode, pc, ER(a), ER(a), 8)
END;
IF im DIV 10000H MOD 100H # 0 THEN
ARMv6M.EmitADDSIm(armcode, pc, ER(a), ER(a),
im DIV 10000H MOD 100H)
END;
ARMv6M.EmitLSLSIm(armcode, pc, ER(a), ER(a), 8);
IF im DIV 100H MOD 100H # 0 THEN
ARMv6M.EmitADDSIm(armcode, pc, ER(a), ER(a),
im DIV 100H MOD 100H)
END;
ARMv6M.EmitLSLSIm(armcode, pc, ER(a), ER(a), 8);
IF im MOD 100H # 0 THEN
ARMv6M.EmitADDSIm(armcode, pc, ER(a), ER(a), im MOD 100H)
END
END
END
ELSE (* a = SP *)
ASSERT(RH < MT, 100);
ASSERT(RH # SP, 101);
MovIm(S, RH, im);
Put00(S, Mov, SP, 0, RH)
END
END MovIm;
(* op # Mov: R.a := R.b op im; op = Mov: R.a := im *)
(* change NZCV according R.a after *)
PROCEDURE Put10 (S: INTEGER; op, a, b, im: LONGINT);
VAR u, v: BOOLEAN;
r: INTEGER;
BEGIN (*emit format-1 instruction, -10000H <= im < 10000H
IF im < 0 THEN INC(op, V) END ;
code[pc] := (((a+40H) * 10H + b) * 10H + op) * 10000H + (im MOD 10000H); INC(pc) *)
ASSERT(S IN {0,1}, 20);
IF ORS.errcnt = 0 THEN
v := 12 IN BITS(op);
IF v THEN DEC(op, V) END;
ASSERT(~v, 100);
u := 13 IN BITS(op);
IF u THEN
ASSERT(im DIV 10000H = 0, 21);
DEC(op, U);
ASSERT(op = Mov, 100);
im := im * 10000H
END;
IF op MOD 10H = Ann THEN
op := (op DIV 10H) * 10H + And;
im := ORDSET(BITS(im) / {0..31}) (* im := ~im *)
END;
(* im: any const *)
ASSERT(op DIV 10H = 0, 22);
ASSERT(a DIV 10H = 0, 23);
ASSERT(b DIV 10H = 0, 24);
IF ~((op = Cmp) & (a = b) & (im = 0)) THEN (* ~Cmp *)
INCL(RM, a)
END;
RemoveRedundantCmp;
op := op MOD 10H;
IF op IN {Lsl,Asr,Ror} THEN
IF im = 0 THEN
Put00(S, Mov, a, 0, b)
ELSIF (im = 32) & (op = Ror) & (S = 1) THEN
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 100);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
ELSE
CASE op OF Lsl: (* R.a := R.b <- im *)
ARMv6M.EmitLSLSIm(armcode, pc, ER(a), ER(b), im)
| Asr: (* R.a := R.b -> im *)
ARMv6M.EmitASRSIm(armcode, pc, ER(a), ER(b), im)
| Ror: (* R.a := R.b rot im *)
IF a = b THEN
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 101);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
END
END
ELSIF op = Mov THEN
MovIm(S, a, im)
ELSE
CASE op OF And: (* R.a := R.b & im *)
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 102);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Ior: (* R.a := R.b or im *)
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 102);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Xor: (* R.a := R.b xor im *)
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 102);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Add: (* R.a := R.b + im *)
IF (ER(a) DIV 8 = 0) & (ER(b) DIV 8 = 0) & ((im DIV 8 = 0) OR (im DIV 100H = 0) & (a = b)) THEN
ARMv6M.EmitADDSIm(armcode, pc, ER(a), ER(b), im)
ELSIF (b = SP) & (im MOD 4 = 0) THEN
ARMv6M.EmitADDSPIm(armcode, pc, ER(a), im DIV 4);
IF S = 1 THEN UpdateFlags(a) END
ELSIF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 108);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Sub: (* R.a := R.b - im *)
IF (a = b) & (im = 0) THEN (* Cmp *)
ASSERT(S = 1, 100);
UpdateFlags(a)
ELSIF (ER(a) DIV 8 = 0) & (ER(b) DIV 8 = 0) & ((im DIV 8 = 0) OR (im DIV 100H = 0) & (a = b)) THEN
ARMv6M.EmitSUBSIm(armcode, pc, ER(a), ER(b), im)
ELSIF (a = SP) & (b = SP) & (im MOD 4 = 0) THEN
ARMv6M.EmitSUBSPIm(armcode, pc, im DIV 4);
IF S = 1 THEN UpdateFlags(a) END
ELSIF (b = LNK) & (a # b) THEN
Put00(0, Mov, a, 0, b);
Put10(S, Sub, a, a, im)
ELSIF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 111);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Mul: (* R.a := R.b * im *)
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 112);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Div: (* R.a := R.b div im *)
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 113);
MovIm(0, r, im);
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
| Fad,Fsb,Fml,Fdv:
IF a = b THEN
r := RH; IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 114);
MovIm(0, r, im); (* TODO: optimize: move to coprocessor register... *)
Put00(S, op, a, b, r)
ELSE
MovIm(0, a, im);
Put00(S, op, a, b, a)
END
END
END
END
END Put10;
PROCEDURE Put1 (op, a, b, im: INTEGER);
BEGIN
Put10(1, op, a, b, im)
END Put1;
PROCEDURE Put1a (op, a, b, im: LONGINT);
BEGIN (*same as Put1, but with range test -10000H <= im < 10000H
IF (im >= -10000H) & (im <= 0FFFFH) THEN Put1(op, a, b, im)
ELSE Put1(Mov+U, RH, 0, im DIV 10000H);
IF im MOD 10000H # 0 THEN Put1(Ior, RH, RH, im MOD 10000H) END ;
Put0(op, a, b, RH)
END *)
ASSERT(op DIV 10H = 0, 20);
Put1(op, a, b, im)
END Put1a;
PROCEDURE Put20 (S: INTEGER; op, a, b, off: LONGINT);
VAR v: BOOLEAN;
r: INTEGER;
BEGIN (*emit load/store instruction
code[pc] := ((op * 10H + a) * 10H + b) * 100000H + (off MOD 100000H); INC(pc) *)
ASSERT(S IN {0,1}, 20);
IF ORS.errcnt = 0 THEN
ASSERT(a DIV 10H = 0, 21);
ASSERT(b DIV 10H = 0, 22);
ASSERT(off >= 0, 23);
ASSERT(off < 100000H, 24);
v := ODD(op); IF v THEN DEC(op) END;
RemoveRedundantCmp;
IF op = Ldr THEN (* R.a := Mem[R.b + off] *)
INCL(RM, a);
IF ~v THEN (* load word *)
ASSERT(off MOD 4 = 0, 100);
IF (b = SP) OR (off DIV 4 DIV 32 = 0) THEN
ARMv6M.EmitLDRIm(armcode, pc, ER(a), ER(b), off DIV 4)
ELSIF a # b THEN
MovIm(0, a, off);
ARMv6M.EmitLDRR(armcode, pc, ER(a), ER(b), ER(a))
ELSE
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 101);
MovIm(0, r, off);
ARMv6M.EmitLDRR(armcode, pc, ER(a), ER(b), ER(r))
END
ELSE (* load byte *)
IF b # SP THEN
IF off DIV 32 = 0 THEN
ARMv6M.EmitLDRBIm(armcode, pc, ER(a), ER(b), off)
ELSIF a # b THEN
MovIm(0, a, off);
ARMv6M.EmitLDRBR(armcode, pc, ER(a), ER(b), ER(a))
ELSE
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 101);
MovIm(0, r, off);
ARMv6M.EmitLDRBR(armcode, pc, ER(a), ER(b), ER(r))
END
ELSE
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 101);
Put00(0, Mov, r, 0, b);
ARMv6M.EmitLDRBIm(armcode, pc, ER(a), ER(r), off)
END
END;
IF S = 1 THEN UpdateFlags(a) END
ELSIF op = Str THEN (* Mem[R.b + off] := R.a *)
IF ~v THEN (* store word *)
ASSERT(off MOD 4 = 0, 102);
IF (b = SP) OR (off DIV 4 DIV 32 = 0) THEN
ARMv6M.EmitSTRIm(armcode, pc, ER(a), ER(b), off DIV 4)
ELSE
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
IF (b < MT) & (r <= b) THEN r := b + 1 END;
ASSERT(r < MT, 101);
MovIm(0, r, off);
ARMv6M.EmitSTRR(armcode, pc, ER(a), ER(b), ER(r))
END
ELSE (* store byte *)
IF b # SP THEN
IF off DIV 32 = 0 THEN
ARMv6M.EmitSTRBIm(armcode, pc, ER(a), ER(b), off)
ELSE
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
IF (b < MT) & (r <= b) THEN r := b + 1 END;
ASSERT(r < MT, 101);
MovIm(0, r, off);
ARMv6M.EmitSTRBR(armcode, pc, ER(a), ER(b), ER(r))
END
ELSE
r := RH;
IF (a < MT) & (r <= a) THEN r := a + 1 END;
ASSERT(r < MT, 103);
Put00(0, Mov, r, 0, b);
ARMv6M.EmitSTRBIm(armcode, pc, ER(a), ER(r), off)
END
END
ELSE HALT(1) (* invalid operation *)
END
END
END Put20;
PROCEDURE Put2 (op, a, b, off: INTEGER);
BEGIN
Put20(1, op, a, b, off)
END Put2;
PROCEDURE CondRISCToARM (cond: INTEGER): INTEGER;
BEGIN
CASE cond OF MI: RETURN ARMv6M.MI
| EQ: RETURN ARMv6M.EQ
| 2: RETURN ARMv6M.CC
| LT: RETURN ARMv6M.LT
| LE: RETURN ARMv6M.LE
| 7: RETURN ARMv6M.AL
| PL: RETURN ARMv6M.PL
| NE: RETURN ARMv6M.NE
| 10: RETURN ARMv6M.CS
| GE: RETURN ARMv6M.GE
| GT: RETURN ARMv6M.GT
(* | 15: RETURN 15 *)
END
END CondRISCToARM;
(*
PROCEDURE CondARMToRISC (armcond: INTEGER): INTEGER;
BEGIN
CASE armcond OF ARMv6M.EQ: RETURN EQ
| ARMv6M.NE: RETURN NE
| ARMv6M.CS: RETURN 10
| ARMv6M.CC: RETURN 2
| ARMv6M.MI: RETURN MI
| ARMv6M.PL: RETURN PL
| ARMv6M.GE: RETURN GE
| ARMv6M.LT: RETURN LT
| ARMv6M.GT: RETURN GT
| ARMv6M.LE: RETURN LE
| ARMv6M.AL: RETURN 7
(* | 15: RETURN 15 *)
END
END CondARMToRISC;
*)
PROCEDURE ^ negated(cond: LONGINT): LONGINT;
PROCEDURE Put3 (op, cond, off: LONGINT);
VAR S, imm10, J1, J2, imm11, imm6: INTEGER;
pc0, pc1: INTEGER;
BEGIN (*emit branch instruction
code[pc] := ((op+12) * 10H + cond) * 1000000H + (off MOD 1000000H); INC(pc) *)
IF ORS.errcnt = 0 THEN
ASSERT(op DIV 4 = 0, 20);
ASSERT(cond DIV 10H = 0, 21);
CASE op OF BR: (* if cond, then PC := R.c *)
IF off IN {0..15} THEN
ASSERT(cond = 7, 102);
ARMv6M.EmitBX(armcode, pc, ER(off))
ELSIF off = 10H THEN
(* return from interrupt *)
HALT(126)
ELSE HALT(1)
END
| BLR:
IF off MOD 10H = MT THEN (* Trap or New *)
off := off DIV 10H MOD 10000000H;
(* see Kernel.Trap, System.Trap *)
IF off MOD 10H = 0 THEN (* New *)
ASSERT(cond = 7, 100);
(* NOTE: New() arguments in R0, R1 *)
ARMv6M.EmitSVC(armcode, pc, off MOD 10H)
ELSIF cond = 7 THEN
MovIm(0, 1, off DIV 10H); (* R1 := ORS.Pos *)
ARMv6M.EmitSVC(armcode, pc, off MOD 10H)
ELSE
pc0 := pc; Put3(BC, 0, 0);
MovIm(0, 1, off DIV 10H); (* R1 := ORS.Pos *)
ARMv6M.EmitSVC(armcode, pc, off MOD 10H);
pc1 := pc;
pc := pc0;
Put3(BC, negated(cond), pc1 - pc0 - 1);
pc := pc1
END
ELSE (* if cond, then LNK := PC+1; PC := R.c *)
ASSERT(off DIV 10H = 0, 101);
ASSERT(cond = 7, 102);
ASSERT(off # 15, 103);
INCL(RM, LNK);
ARMv6M.EmitBLX(armcode, pc, ER(off))
END
| BC: (* if cond, then PC := PC+1+offset *)
ASSERT(off >= -800000H, 102);
ASSERT(off < 800000H, 103);
DEC(off);
IF cond = 7 THEN
IF (off >= -1024) & (off <= 1023) THEN
ARMv6M.EmitB(armcode, pc, off)
ELSE
ORS.Mark("unconditional branch is too long")
END
ELSIF cond = 15 THEN
ARMv6M.EmitNOP(armcode, pc)
ELSE
IF (off >= -128) & (off <= 127) THEN
ARMv6M.EmitBC(armcode, pc, CondRISCToARM(cond), off)
ELSE
ORS.Mark("conditional branch is too long")
END
END
| BL: (* if cond, then LNK := PC+1; PC := PC+1+offset *)
ASSERT(off >= -800000H, 104);
ASSERT(off < 800000H, 105);
INCL(RM, LNK);
IF cond # 7 THEN
HALT(126)
ELSE
IF off # 0 THEN DEC(off) END;
ARMv6M.EmitBL(armcode, pc, off)
END
END
END
END Put3;
PROCEDURE incR;
BEGIN
IF RH < MT-1 THEN INC(RH) ELSE ORS.Mark("register stack overflow") END
END incR;
PROCEDURE CheckRegs*;
BEGIN
IF RH # 0 THEN ORS.Mark("Reg Stack"); RH := 0 END ;
IF pc >= maxCode - 40 THEN ORS.Mark("program too long") END;
IF frame # 0 THEN ORS.Mark("frame error"); frame := 0 END
END CheckRegs;
PROCEDURE SetCC(VAR x: Item; n: LONGINT);
BEGIN x.mode := Cond; x.a := 0; x.b := 0; x.r := n
END SetCC;
PROCEDURE Trap(cond, num: LONGINT);
BEGIN Put3(BLR, cond, ORS.Pos()*100H + num*10H + MT)
END Trap;
(*handling of forward reference, fixups of branch addresses and constant tables*)
PROCEDURE negated(cond: LONGINT): LONGINT;
BEGIN
IF cond < 8 THEN cond := cond+8 ELSE cond := cond-8 END ;
RETURN cond
END negated;
PROCEDURE invalSB;
BEGIN curSB := 1
END invalSB;
PROCEDURE fix (at, with: LONGINT);
BEGIN
IF ORS.errcnt = 0 THEN
ASSERT(armcode[at] DIV 10000000H MOD 10H = 0EH, 100) (* BC *)
END;
armcode[at] := armcode[at] DIV C24 * C24 + (with MOD C24)
END fix;
PROCEDURE FixOne*(at: LONGINT);
BEGIN fix(at, pc-at-1)
END FixOne;
PROCEDURE FixLink*(L: LONGINT);
VAR L1: LONGINT;
BEGIN invalSB;
WHILE L # 0 DO L1 := armcode[L] MOD 40000H; fix(L, pc-L-1); L := L1 END
END FixLink;
PROCEDURE FixLinkWith (L0, dst: LONGINT);
VAR L1: LONGINT;
BEGIN
WHILE L0 # 0 DO
L1 := armcode[L0] MOD C24;
armcode[L0] := armcode[L0] DIV C24 * C24 + ((dst - L0 - 1) MOD C24); L0 := L1
END
END FixLinkWith;
PROCEDURE merged (L0, L1: LONGINT): LONGINT;
VAR L2, L3: LONGINT;
BEGIN
IF L0 # 0 THEN L3 := L0;
REPEAT L2 := L3; L3 := armcode[L2] MOD 40000H UNTIL L3 = 0;
armcode[L2] := armcode[L2] + L1; L1 := L0
END;
RETURN L1
END merged;
(* loading of operands and addresses into registers *)
(* for fixups only *)
PROCEDURE Put1orig (op, a, b, im: LONGINT);
BEGIN (*emit format-1 instruction, -10000H <= im < 10000H*)
IF im < 0 THEN INC(op, V) END;
armcode[pc] := (((a+40H) * 10H + b) * 10H + op) * 10000H + (im MOD 10000H); INC(pc)
END Put1orig;
PROCEDURE Put2orig (op, a, b, off: LONGINT);
BEGIN (*emit load/store instruction*)
armcode[pc] := ((op * 10H + a) * 10H + b) * 100000H + (off MOD 100000H); INC(pc)
END Put2orig;
PROCEDURE Put3orig (op, cond, off: LONGINT);
BEGIN (*emit branch instruction*)
armcode[pc] := ((op+12) * 10H + cond) * 1000000H + (off MOD 1000000H); INC(pc)
END Put3orig;
PROCEDURE GetSB (base: LONGINT);
BEGIN
IF (version # 0) & ((base # curSB) OR (base # 0)) THEN
(* will be fixed up by linker/loader *)
INCL(RM, SB);
Put2orig(Ldr, ER(SB), -base, pc-fixorgD); fixorgD := pc-1; curSB := base
END
END GetSB;
PROCEDURE NilCheck;
BEGIN IF check THEN Trap(EQ, 4) END
END NilCheck;
PROCEDURE load0 (S: INTEGER; VAR x: Item);
VAR op, pc0, pc1: LONGINT;
BEGIN
ASSERT(S IN {0,1}, 20);
IF x.type.size = 1 THEN op := Ldr+1 ELSE op := Ldr END ;
IF x.mode # Reg THEN
IF x.mode = ORB.Const THEN
IF x.type.form = ORB.Proc THEN
IF x.r > 0 THEN ORS.Mark("not allowed")
ELSIF x.r = 0 THEN Put3(BL, 7, 0);
ASSERT(x.a MOD 2 = 0, 100);
Put10(S, Sub, RH, LNK, (pc*4 - x.a) DIV 2)
ELSE GetSB(x.r);
INCL(RM, RH);
Put1orig(Add, ER(RH), ER(SB), x.a + 100H); (*mark as progbase-relative*)
armcode[pc] := 00FFFFFFH; INC(pc)
END
(*
ELSIF (x.a <= 0FFFFH) & (x.a >= -10000H) THEN Put1(Mov, RH, 0, x.a)
ELSE Put1(Mov+U, RH, 0, x.a DIV 10000H MOD 10000H);
IF x.a MOD 10000H # 0 THEN Put1(Ior, RH, RH, x.a MOD 10000H) END
*)
ELSE Put10(S, Mov, RH, 0, x.a)
END;