diff --git a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py index 6b9849cf7f3..61750324238 100644 --- a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py +++ b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py @@ -1310,7 +1310,7 @@ def substrate_resistivity(self, substrate_input): ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) @property - def substrate_loss_tangent(self) -> Union[SubstrateType, str]: + def substrate_loss_tangent(self) -> Union[SubstrateEr, str]: """Substrate's loss tangent. The value can be either a string or an instance of the ``SubstrateEr`` enum. The default is ``0.0005`` for ``SubstrateEr.ALUMINA``. diff --git a/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg b/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg index d53e30325bd..4062cb29a22 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg +++ b/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg @@ -1,31 +1,31 @@ modsubType=2 -modsubEr=4.5 -modsubRho=5.8E+07 -modsubTand=0.035 -modsubH=0.002 -modsubT=5E-07 +modsubEr=9.8 +modsubRho=1.43 +modsubTand=0.0005 +modsubH=0.00127 +modsubT=2.54E-06 modsubS=0.00127 modsubC=0.00635 -modsubErsel=-1 -modsubRhosel=-1 -modsubTandsel=-1 -modsubTanddef=0 +modsubErsel=1 +modsubRhosel=3 +modsubTandsel=1 +modsubTanddef=1 modsubiSubSel=0 -modsubName=User Defined Substrate +modsubName=Alumina modsubBrow= -modsubNameVal=4.5 +modsubNameVal=Alumina: 9.8 modAnsSubIndex=0 modAWRSubIndex=0 webAWRSubIndex=0 locAWRSubIndex=0 -ModelData=2 +ModelData=0 ModelDataV=1 ModelInd=0 -ModelCap=3 +ModelCap=0 ModelRes=0 -ModelIndV=1 -ModelCapV=1 -ModelResV=1 +ModelIndV=0 +ModelCapV=0 +ModelResV=0 modRatLen=2 modRatZ=1 Interc=1 diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py index 488f05aa701..876c335be0a 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py @@ -50,7 +50,6 @@ class TestClass: def test_modelithics_inductor_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -59,7 +58,6 @@ def test_modelithics_inductor_list_count(self): def test_modelithics_inductor_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -72,7 +70,6 @@ def test_modelithics_inductor_list(self): def test_modelithics_inductor_selection(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -85,7 +82,6 @@ def test_modelithics_inductor_selection(self): def test_modelithics_inductor_family_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -98,7 +94,6 @@ def test_modelithics_inductor_family_list_count(self): def test_modelithics_inductor_family_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -113,7 +108,6 @@ def test_modelithics_inductor_family_list(self): def test_modelithics_inductor_family_list_add_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -128,7 +122,6 @@ def test_modelithics_inductor_family_list_add_family(self): def test_modelithics_inductor_family_list_remove_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_remove_family(second_modelithics_inductor) lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS @@ -143,16 +136,14 @@ def test_modelithics_inductor_family_list_remove_family(self): def test_modelithics_capacitor_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 140 + assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 143 def test_modelithics_capacitor_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -165,7 +156,6 @@ def test_modelithics_capacitor_list(self): def test_modelithics_capacitor_selection(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -178,7 +168,6 @@ def test_modelithics_capacitor_selection(self): def test_modelithics_capacitor_family_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -191,7 +180,6 @@ def test_modelithics_capacitor_family_list_count(self): def test_modelithics_capacitor_family_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -206,7 +194,6 @@ def test_modelithics_capacitor_family_list(self): def test_modelithics_capacitor_family_list_add_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -221,7 +208,6 @@ def test_modelithics_capacitor_family_list_add_family(self): def test_modelithics_capacitor_family_list_remove_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -237,7 +223,6 @@ def test_modelithics_capacitor_family_list_remove_family(self): def test_modelithics_resistor_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -246,7 +231,6 @@ def test_modelithics_resistor_list_count(self): def test_modelithics_resistor_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -259,7 +243,6 @@ def test_modelithics_resistor_list(self): def test_modelithics_resistor_selection(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -272,7 +255,6 @@ def test_modelithics_resistor_selection(self): def test_modelithics_resistor_family_list_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -285,7 +267,6 @@ def test_modelithics_resistor_family_list_count(self): def test_modelithics_resistor_family_list(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -300,7 +281,6 @@ def test_modelithics_resistor_family_list(self): def test_modelithics_resistor_family_list_add_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -315,7 +295,6 @@ def test_modelithics_resistor_family_list_add_family(self): def test_modelithics_resistor_family_list_remove_family(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -331,136 +310,117 @@ def test_modelithics_resistor_family_list_remove_family(self): def test_schematic_name(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.schematic_name = "my_schematic" assert lumpdesign.export_to_aedt.schematic_name == "my_schematic" def test_simulate_after_export_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.simulate_after_export_enabled == False lumpdesign.export_to_aedt.simulate_after_export_enabled = True assert lumpdesign.export_to_aedt.simulate_after_export_enabled == True def test_include_group_delay_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_group_delay_enabled == False lumpdesign.export_to_aedt.include_group_delay_enabled = True assert lumpdesign.export_to_aedt.include_group_delay_enabled == True def test_include_gt_gain_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_gt_gain_enabled == False lumpdesign.export_to_aedt.include_gt_gain_enabled = True assert lumpdesign.export_to_aedt.include_gt_gain_enabled == True def test_include_vgsl_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_vgsl_enabled == False lumpdesign.export_to_aedt.include_vgsl_enabled = True assert lumpdesign.export_to_aedt.include_vgsl_enabled == True def test_include_vgin_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_vgin_enabled == False lumpdesign.export_to_aedt.include_vgin_enabled = True assert lumpdesign.export_to_aedt.include_vgin_enabled == True def test_include_input_return_loss_s11_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == True lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled = False assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == False def test_include_forward_transfer_s21_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == True lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled = False assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == False def test_include_reverse_transfer_s12_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == False lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled = True assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == True def test_include_output_return_loss_s22_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == False lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled = True assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == True def test_db_format_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.db_format_enabled == True lumpdesign.export_to_aedt.db_format_enabled = False assert lumpdesign.export_to_aedt.db_format_enabled == False def test_rectangular_plot_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.rectangular_plot_enabled == True lumpdesign.export_to_aedt.rectangular_plot_enabled = False assert lumpdesign.export_to_aedt.rectangular_plot_enabled == False def test_smith_plot_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.smith_plot_enabled == False lumpdesign.export_to_aedt.smith_plot_enabled = True assert lumpdesign.export_to_aedt.smith_plot_enabled == True def test_polar_plot_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.polar_plot_enabled == False lumpdesign.export_to_aedt.polar_plot_enabled = True assert lumpdesign.export_to_aedt.polar_plot_enabled == True def test_table_data_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.table_data_enabled == False lumpdesign.export_to_aedt.table_data_enabled = True assert lumpdesign.export_to_aedt.table_data_enabled == True def test_optimitrics_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.optimitrics_enabled == True lumpdesign.export_to_aedt.optimitrics_enabled = False assert lumpdesign.export_to_aedt.optimitrics_enabled == False def test_optimize_after_export_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.optimize_after_export_enabled == False lumpdesign.export_to_aedt.optimize_after_export_enabled = True assert lumpdesign.export_to_aedt.optimize_after_export_enabled == True def test_load_library_parts_config(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts.cfg")) lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.substrate_er == "4.5" - assert lumpdesign.export_to_aedt.substrate_resistivity == "5.8E+07 " - assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "500 nm" - assert lumpdesign.export_to_aedt.substrate_dielectric_height == "2 mm" - assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.035 " + assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA + assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" + assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA def test_save_library_parts_config(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS lumpdesign.export_to_aedt.substrate_er = "2.25" lumpdesign.export_to_aedt.substrate_resistivity = "4.2E+07 " @@ -478,7 +438,6 @@ def test_save_library_parts_config(self): def test_import_tuned_variables(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.simulate_after_export_enabled = True lumpdesign.export_to_aedt.optimize_after_export_enabled = True lumpdesign.export_to_aedt.export_design() @@ -488,9 +447,6 @@ def test_import_tuned_variables(self): def test_part_libraries(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.export_to_aedt._open_aedt_export() - assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.LUMPED assert len(PartLibraries) == 3 lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS @@ -498,91 +454,78 @@ def test_part_libraries(self): def test_interconnect_length_to_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_length_to_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "3" def test_interconnect_minimum_length_to_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.5" lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio = "0.6" assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.6" def test_interconnect_maximum_length_to_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "3" def test_interconnect_line_to_termination_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "1" lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio = "2" assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "2" def test_interconnect_minimum_line_to_termination_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.5" lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio = "0.6" assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.6" def test_interconnect_maximum_line_to_termination_width_ratio(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "3" def test_interconnect_length_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_length_value == "2.54 mm" lumpdesign.export_to_aedt.interconnect_length_value = "3 mm" assert lumpdesign.export_to_aedt.interconnect_length_value == "3 mm" def test_interconnect_minimum_length_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "1.27 mm" lumpdesign.export_to_aedt.interconnect_minimum_length_value = "0.6 mm" assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "0.6 mm" def test_interconnect_maximum_length_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "5.08 mm" lumpdesign.export_to_aedt.interconnect_maximum_length_value = "6 mm" assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "6 mm" def test_interconnect_line_width_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_line_width_value == "1.27 mm" lumpdesign.export_to_aedt.interconnect_line_width_value = "2 mm" assert lumpdesign.export_to_aedt.interconnect_line_width_value == "2 mm" def test_interconnect_minimum_width_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "635 um" lumpdesign.export_to_aedt.interconnect_minimum_width_value = "725 um" assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "725 um" def test_interconnect_maximum_width_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "2.54 mm" lumpdesign.export_to_aedt.interconnect_maximum_width_value = "3 mm" assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "3 mm" def test_interconnect_inductor_tolerance_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "1" lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value = "10" @@ -590,7 +533,6 @@ def test_interconnect_inductor_tolerance_value(self): def test_interconnect_capacitor_tolerance_value(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "1" lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value = "10" @@ -598,14 +540,12 @@ def test_interconnect_capacitor_tolerance_value(self): def test_interconnect_geometry_optimization_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == True lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled = False assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == False def test_substrate_type(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_type == SubstrateType.MICROSTRIP assert len(SubstrateType) == 5 for substrate in SubstrateType: @@ -614,7 +554,6 @@ def test_substrate_type(self): def test_substrate_er(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for er in SubstrateEr: @@ -625,7 +564,6 @@ def test_substrate_er(self): def test_substrate_resistivity(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD assert len(SubstrateResistivity) == 11 for resistivity in SubstrateResistivity: @@ -636,7 +574,6 @@ def test_substrate_resistivity(self): def test_substrate_loss_tangent(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for loss in SubstrateEr: @@ -647,21 +584,18 @@ def test_substrate_loss_tangent(self): def test_substrate_conductor_thickness(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" lumpdesign.export_to_aedt.substrate_conductor_thickness = "1.25 um" assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "1.25 um" def test_substrate_dielectric_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" lumpdesign.export_to_aedt.substrate_dielectric_height = "1.22 mm" assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.22 mm" def test_substrate_unbalanced_lower_dielectric_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "6.35 mm" @@ -670,7 +604,6 @@ def test_substrate_unbalanced_lower_dielectric_height(self): def test_substrate_suspend_dielectric_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_type = SubstrateType.SUSPEND assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "1.27 mm" lumpdesign.export_to_aedt.substrate_suspend_dielectric_height = "3.2 mm" @@ -678,7 +611,6 @@ def test_substrate_suspend_dielectric_height(self): def test_substrate_cover_height(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_cover_height_enabled = True assert lumpdesign.export_to_aedt.substrate_cover_height == "6.35 mm" lumpdesign.export_to_aedt.substrate_cover_height = "2.5 mm" @@ -686,7 +618,6 @@ def test_substrate_cover_height(self): def test_substrate_unbalanced_stripline_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == False lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True @@ -694,7 +625,6 @@ def test_substrate_unbalanced_stripline_enabled(self): def test_substrate_cover_height_enabled(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == False lumpdesign.export_to_aedt.substrate_cover_height_enabled = True assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == True