From 6d7b0db413c0e14cb21bc8d8e1564f7c50a20dde Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Thu, 2 Nov 2023 17:44:48 +0000
Subject: [PATCH 1/2] jtag_devs: Fix the logic around the RISC-V debug entry so
 it gets enabled correctly when giving various combinations of
 `ENABLE_DEBUG=1` and `ENABLE_RISCV=1`

---
 src/target/jtag_devs.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/target/jtag_devs.c b/src/target/jtag_devs.c
index 7e06b4ad70b..e9e9afd604d 100644
--- a/src/target/jtag_devs.c
+++ b/src/target/jtag_devs.c
@@ -348,13 +348,17 @@ const jtag_dev_descr_s dev_descr[] = {
 				.ir_value = 1U,
 			},
 	},
-#ifdef ENABLE_DEBUG
+#ifdef ENABLE_RISCV
 	{
 		.idcode = 0x0000563dU,
 		.idmask = 0x0fffffffU,
+#ifdef ENABLE_DEBUG
 		.descr = "RISC-V debug v0.13.",
+#endif
 		.handler = riscv_jtag_dtm_handler,
 	},
+#endif
+#ifdef ENABLE_DEBUG
 	{
 		.idcode = 0x000007a3U,
 		.idmask = 0x00000fffU,

From cadc36d3ea810644028689f6f980b727ad56f6ff Mon Sep 17 00:00:00 2001
From: dragonmux <git@dragonmux.network>
Date: Thu, 2 Nov 2023 18:02:03 +0000
Subject: [PATCH 2/2] stm32f1: Improved the hygene of when gd32vf1_probe() gets
 defined so we don't pull it in when the RISC-V support is not enabled

---
 src/target/stm32f1.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c
index 46f651959cd..98639ecba51 100644
--- a/src/target/stm32f1.c
+++ b/src/target/stm32f1.c
@@ -182,6 +182,7 @@ bool gd32f1_probe(target_s *target)
 	return true;
 }
 
+#ifdef ENABLE_RISCV
 /* Identify RISC-V GD32VF1 chips */
 bool gd32vf1_probe(target_s *const target)
 {
@@ -210,6 +211,7 @@ bool gd32vf1_probe(target_s *const target)
 
 	return true;
 }
+#endif
 
 static bool at32f40_detect(target_s *target, const uint16_t part_id)
 {