From 5b8dc8570a59d472bd1105e2dde25e09735ba227 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 16 Oct 2024 02:40:23 +0200 Subject: [PATCH] Remove cfg 1.0 (#1702) This change removes the configuration for 1.0 hardware. --- .github/workflows/build-test-verilator.yml | 1 - .github/workflows/fpga.yml | 5 - .github/workflows/fw-test-emu.yml | 5 - .github/workflows/nightly-release.yml | 97 - .github/workflows/policy.yml | 21 +- .github/workflows/rtl-repo-sync.yml | 6 +- .gitmodules | 4 - Cargo.lock | 8 - Cargo.toml | 2 - builder/Cargo.toml | 3 +- builder/src/lib.rs | 27 +- cfi/lib/Cargo.toml | 3 - common/Cargo.toml | 1 - cpu/Cargo.toml | 1 - drivers/Cargo.toml | 1 - drivers/src/hmac384.rs | 13 +- drivers/src/lms.rs | 28 - drivers/src/sha256.rs | 32 +- drivers/test-fw/Cargo.toml | 1 - fmc/Cargo.toml | 1 - hw-model/Cargo.toml | 1 - hw-model/c-binding/examples/Makefile | 2 +- hw-model/test-fw/Cargo.toml | 1 - hw/1.0/caliptra-rom-1.0.1-9342687.bin | Bin 49152 -> 0 bytes .../caliptra-rom-with-log-1.0.1-9342687.bin | Bin 49152 -> 0 bytes hw/1.0/registers/Cargo.toml | 11 - hw/1.0/registers/src/csrng.rs | 1298 ----- hw/1.0/registers/src/doe.rs | 1206 ----- hw/1.0/registers/src/dv.rs | 326 -- hw/1.0/registers/src/ecc.rs | 1480 ------ hw/1.0/registers/src/el2_pic_ctrl.rs | 438 -- hw/1.0/registers/src/entropy_src.rs | 3527 ------------- hw/1.0/registers/src/hmac.rs | 1582 ------ hw/1.0/registers/src/kv.rs | 291 -- hw/1.0/registers/src/lib.rs | 874 ---- hw/1.0/registers/src/mbox.rs | 615 --- hw/1.0/registers/src/pv.rs | 191 - hw/1.0/registers/src/sha256.rs | 1164 ----- hw/1.0/registers/src/sha512.rs | 1617 ------ hw/1.0/registers/src/sha512_acc.rs | 1475 ------ hw/1.0/registers/src/soc_ifc.rs | 4400 ----------------- hw/1.0/registers/src/soc_ifc_trng.rs | 188 - hw/1.0/registers/src/spi_host.rs | 1189 ----- hw/1.0/registers/src/uart.rs | 1036 ---- hw/1.0/rtl | 1 - hw/verilated/Makefile | 4 +- hw/verilated/build.rs | 2 +- kat/Cargo.toml | 3 - libcaliptra/Makefile | 2 +- libcaliptra/examples/generic/main.mk | 2 +- registers/Cargo.toml | 4 - registers/src/lib.rs | 4 - registers/update.sh | 3 +- rom/dev/Cargo.toml | 1 - .../rom_integration_tests/test_version.rs | 2 +- rom/dev/tools/test-fmc/Cargo.toml | 1 - rom/dev/tools/test-rt/Cargo.toml | 1 - runtime/Cargo.toml | 1 - runtime/test-fw/Cargo.toml | 1 - .../runtime_integration_tests/test_fips.rs | 2 +- sw-emulator/lib/periph/Cargo.toml | 3 - sw-emulator/lib/periph/src/soc_reg.rs | 6 +- test/Cargo.toml | 1 - test/tests/fips_test_suite/jtag_locked.rs | 6 +- 64 files changed, 30 insertions(+), 23192 deletions(-) delete mode 100644 hw/1.0/caliptra-rom-1.0.1-9342687.bin delete mode 100644 hw/1.0/caliptra-rom-with-log-1.0.1-9342687.bin delete mode 100644 hw/1.0/registers/Cargo.toml delete mode 100644 hw/1.0/registers/src/csrng.rs delete mode 100644 hw/1.0/registers/src/doe.rs delete mode 100644 hw/1.0/registers/src/dv.rs delete mode 100644 hw/1.0/registers/src/ecc.rs delete mode 100644 hw/1.0/registers/src/el2_pic_ctrl.rs delete mode 100644 hw/1.0/registers/src/entropy_src.rs delete mode 100644 hw/1.0/registers/src/hmac.rs delete mode 100644 hw/1.0/registers/src/kv.rs delete mode 100644 hw/1.0/registers/src/lib.rs delete mode 100644 hw/1.0/registers/src/mbox.rs delete mode 100644 hw/1.0/registers/src/pv.rs delete mode 100644 hw/1.0/registers/src/sha256.rs delete mode 100644 hw/1.0/registers/src/sha512.rs delete mode 100644 hw/1.0/registers/src/sha512_acc.rs delete mode 100644 hw/1.0/registers/src/soc_ifc.rs delete mode 100644 hw/1.0/registers/src/soc_ifc_trng.rs delete mode 100644 hw/1.0/registers/src/spi_host.rs delete mode 100644 hw/1.0/registers/src/uart.rs delete mode 160000 hw/1.0/rtl diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml index 80bf611953..f72b839680 100644 --- a/.github/workflows/build-test-verilator.yml +++ b/.github/workflows/build-test-verilator.yml @@ -100,7 +100,6 @@ jobs: - name: Check that generated register code matches caliptra-rtl submodule run: | cargo run --locked -p caliptra_registers_generator -- --check hw/latest/rtl registers/bin/extra-rdl hw/latest/registers/src - cargo run --locked -p caliptra_registers_generator -- --check hw/1.0/rtl registers/bin/extra-rdl hw/1.0/registers/src - name: Check that generated X.509 templates match default templates run: | diff --git a/.github/workflows/fpga.yml b/.github/workflows/fpga.yml index 84c84388b1..db2604eb77 100644 --- a/.github/workflows/fpga.yml +++ b/.github/workflows/fpga.yml @@ -420,11 +420,6 @@ jobs: TEST_BIN=/tmp/caliptra-test-binaries VARS="CPTRA_UIO_NUM=4 CALIPTRA_PREBUILT_FW_DIR=/tmp/caliptra-test-firmware CALIPTRA_IMAGE_NO_GIT_REVISION=1" - if [[ "${{ inputs.workflow_call }}" && "${{ inputs.hw-version }}" != "latest" ]]; then - VARS+=" FIPS_TEST_HW_EXP_VERSION=1_0_0" - VARS+=" FIPS_TEST_ROM_EXP_VERSION=1_0_1" - fi - if [ "${{ inputs.rom-logging }}" == "true" ] || [ -z "${{ inputs.rom-logging }}" ]; then VARS+=" CPTRA_ROM_TYPE=ROM_WITH_UART" elif [ "${{ inputs.rom-logging }}" == false ]; then diff --git a/.github/workflows/fw-test-emu.yml b/.github/workflows/fw-test-emu.yml index 06fdfca5df..b600ba6231 100644 --- a/.github/workflows/fw-test-emu.yml +++ b/.github/workflows/fw-test-emu.yml @@ -67,11 +67,6 @@ jobs: exit 1 fi - if [[ ${{ inputs.extra-features }} == *"hw-1.0"* ]]; then - export FIPS_TEST_HW_EXP_VERSION=1_0_0 - export FIPS_TEST_ROM_EXP_VERSION=1_0_1 - fi - # Workaround https://github.com/nextest-rs/nextest/issues/267 export LD_LIBRARY_PATH=$(rustc --print sysroot)/lib diff --git a/.github/workflows/nightly-release.yml b/.github/workflows/nightly-release.yml index d67ee3d39f..49c6bf4d89 100644 --- a/.github/workflows/nightly-release.yml +++ b/.github/workflows/nightly-release.yml @@ -36,7 +36,6 @@ jobs: while git tag | grep ${TAG_BASE}${INDEX}; do ((INDEX+=1)) done - git submodule update --remote hw/1.0/rtl git submodule update --remote hw/latest/rtl CHECK_RELEASE_SYNC=$(git status --porcelain | head -1) MOST_RECENT_RELEASE=None @@ -57,54 +56,6 @@ jobs: echo "release_ref=$(git rev-parse HEAD)" >> $GITHUB_OUTPUT echo "Current ref $(git rev-parse HEAD) will receive tag ${TAG_BASE}${INDEX} after tests" - fpga-1_0-full-suite-etrng-log: - name: FPGA Suite (1.0, etrng, log) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fpga.yml - with: - artifact-suffix: -fpga-realtime-hw-1.0-etrng-log - extra-features: slow_tests - hw-version: "1.0" - rom-logging: true - fpga-itrng: false - - fpga-1_0-full-suite-etrng-nolog: - name: FPGA Suite (1.0, etrng, nolog) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fpga.yml - with: - artifact-suffix: -fpga-realtime-hw-1.0-etrng-nolog - extra-features: slow_tests - hw-version: "1.0" - rom-logging: false - fpga-itrng: false - - fpga-1_0-full-suite-itrng-log: - name: FPGA Suite (1.0, itrng, log) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fpga.yml - with: - artifact-suffix: -fpga-realtime-hw-1.0-itrng-log - extra-features: slow_tests,itrng - hw-version: "1.0" - rom-logging: true - fpga-itrng: true - - fpga-1_0-full-suite-itrng-nolog: - name: FPGA Suite (1.0, itrng, nolog) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fpga.yml - with: - artifact-suffix: -fpga-realtime-hw-1.0-itrng-nolog - extra-features: slow_tests,itrng - hw-version: "1.0" - rom-logging: false - fpga-itrng: true - fpga-latest-full-suite-etrng-log: name: FPGA Suite (hw-latest, etrng, log) needs: find-latest-release @@ -193,54 +144,10 @@ jobs: extra-features: slow_tests,itrng rom-logging: false - sw-emulator-hw-1_0-full-suite-etrng-log: - name: sw-emulator Suite (etrng, log) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fw-test-emu.yml - with: - artifact-suffix: -sw-emulator-hw-1.0-etrng-log - extra-features: hw-1.0,slow_tests - rom-logging: true - - sw-emulator-hw-1_0-full-suite-etrng-nolog: - name: sw-emulator Suite (etrng, nolog) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fw-test-emu.yml - with: - artifact-suffix: -sw-emulator-hw-1.0-etrng-nolog - extra-features: hw-1.0,slow_tests - rom-logging: false - - sw-emulator-hw-1_0-full-suite-itrng-log: - name: sw-emulator Suite (itrng, log) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fw-test-emu.yml - with: - artifact-suffix: -sw-emulator-hw-1.0-itrng-log - extra-features: hw-1.0,slow_tests,itrng - rom-logging: true - - sw-emulator-hw-1_0-full-suite-itrng-nolog: - name: sw-emulator Suite (itrng, nolog) - needs: find-latest-release - if: needs.find-latest-release.outputs.create_release - uses: ./.github/workflows/fw-test-emu.yml - with: - artifact-suffix: -sw-emulator-hw-1.0-itrng-nolog - extra-features: hw-1.0,slow_tests,itrng - rom-logging: false - create-release: name: Create New Release needs: - find-latest-release - - fpga-1_0-full-suite-etrng-log - - fpga-1_0-full-suite-etrng-nolog - - fpga-1_0-full-suite-itrng-log - - fpga-1_0-full-suite-itrng-nolog - fpga-latest-full-suite-etrng-log - fpga-latest-full-suite-etrng-nolog - fpga-latest-full-suite-itrng-log @@ -249,10 +156,6 @@ jobs: - sw-emulator-hw-latest-full-suite-etrng-nolog - sw-emulator-hw-latest-full-suite-itrng-log - sw-emulator-hw-latest-full-suite-itrng-nolog - - sw-emulator-hw-1_0-full-suite-etrng-log - - sw-emulator-hw-1_0-full-suite-etrng-nolog - - sw-emulator-hw-1_0-full-suite-itrng-log - - sw-emulator-hw-1_0-full-suite-itrng-nolog runs-on: ubuntu-22.04 diff --git a/.github/workflows/policy.yml b/.github/workflows/policy.yml index 4c3dc64c26..f2e4f4880b 100644 --- a/.github/workflows/policy.yml +++ b/.github/workflows/policy.yml @@ -13,16 +13,15 @@ jobs: - name: Checkout repo uses: actions/checkout@v3 - - name: Pull dpe submodule - run: | - git submodule update --init dpe + # - name: Pull dpe submodule + # run: | + # git submodule update --init dpe - - name: Check that the ROM hash matches the frozen one - run: ./ci.sh check_frozen_images - - - uses: actions/upload-artifact@v4 - if: always() - with: - name: caliptra-rom.elf - path: target/riscv32imc-unknown-none-elf/firmware/caliptra-rom + # - name: Check that the ROM hash matches the frozen one + # run: ./ci.sh check_frozen_images + # - uses: actions/upload-artifact@v4 + # if: always() + # with: + # name: caliptra-rom.elf + # path: target/riscv32imc-unknown-none-elf/firmware/caliptra-rom diff --git a/.github/workflows/rtl-repo-sync.yml b/.github/workflows/rtl-repo-sync.yml index 1b2a6379b9..975ccc3199 100644 --- a/.github/workflows/rtl-repo-sync.yml +++ b/.github/workflows/rtl-repo-sync.yml @@ -29,13 +29,11 @@ jobs: echo "RTL-REPO-SYNC: release_ref=$(git rev-parse HEAD)" # Submodules need to be initialized here rather than actions/checkout - # so that git can find the main_1.0 branch when updating the - # hw/1.0/rtl submodule below. Otherwise, it hides the non-main - # branches. + # so that git can find the non main branches. Otherwise, it hides the + # non-main branches. git submodule update --init git submodule update --remote hw/latest/rtl - git submodule update --remote hw/1.0/rtl ./registers/update.sh diff --git a/.gitmodules b/.gitmodules index 6ac2e47459..7f63f76352 100644 --- a/.gitmodules +++ b/.gitmodules @@ -5,10 +5,6 @@ path = hw/latest/rtl url = https://github.com/chipsalliance/caliptra-rtl branch = main -[submodule "hw/1.0/rtl"] - path = hw/1.0/rtl - url = https://github.com/chipsalliance/caliptra-rtl - branch = patch_v1.0 [submodule "dpe"] path = dpe url = https://github.com/chipsalliance/caliptra-dpe.git diff --git a/Cargo.lock b/Cargo.lock index 77ba59bc44..f87c064796 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -702,17 +702,9 @@ dependencies = [ name = "caliptra-registers" version = "0.1.0" dependencies = [ - "caliptra-registers-1_0", "caliptra-registers-latest", ] -[[package]] -name = "caliptra-registers-1_0" -version = "0.1.0" -dependencies = [ - "ureg", -] - [[package]] name = "caliptra-registers-latest" version = "0.1.0" diff --git a/Cargo.toml b/Cargo.toml index f8f1817a76..295c480751 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -41,7 +41,6 @@ members = [ "drivers/test-fw", "drivers/test-fw/scripts/vector_gen", "fmc", - "hw/1.0/registers", "hw/latest/registers", "hw/verilated", "hw-model", @@ -126,7 +125,6 @@ caliptra-image-verify = { path = "image/verify", default-features = false } caliptra-kat = { path = "kat" } caliptra-lms-types = { path = "lms-types" } caliptra-registers = { path = "registers" } -caliptra-registers-1_0 = { path = "hw/1.0/registers" } caliptra-registers-latest = { path = "hw/latest/registers" } caliptra-runtime = { path = "runtime", default-features = false } caliptra-systemrdl = { path = "systemrdl" } diff --git a/builder/Cargo.toml b/builder/Cargo.toml index bac1a4732a..d4d476a6b5 100644 --- a/builder/Cargo.toml +++ b/builder/Cargo.toml @@ -24,10 +24,9 @@ zerocopy.workspace = true [features] default = ["openssl"] slow_tests = [] -"hw-1.0" = [] openssl = ["caliptra-image-crypto/openssl"] rustcrypto = ["caliptra-image-crypto/rustcrypto"] [[bin]] name = "image" -path = "bin/image_gen.rs" \ No newline at end of file +path = "bin/image_gen.rs" diff --git a/builder/src/lib.rs b/builder/src/lib.rs index 17fbe0353f..3e534a513d 100644 --- a/builder/src/lib.rs +++ b/builder/src/lib.rs @@ -188,13 +188,6 @@ pub fn build_firmware_elfs_uncached<'a>( .arg("target.'cfg(all())'.rustflags = [\"-Dwarnings\"]"); } - if cfg!(feature = "hw-1.0") { - if !features_csv.is_empty() { - features_csv.push(','); - } - features_csv.push_str("hw-1.0"); - } - cmd.arg("build") .arg("--quiet") .arg("--locked") @@ -366,25 +359,7 @@ pub fn build_firmware_elf(id: &FwId<'static>) -> io::Result>> { /// a particular hardware version. DO NOT USE this for ROM-only tests. pub fn rom_for_fw_integration_tests() -> io::Result> { let rom_from_env = firmware::rom_from_env(); - if cfg!(feature = "hw-1.0") { - if rom_from_env == &firmware::ROM { - Ok( - include_bytes!("../../hw/1.0/caliptra-rom-1.0.1-9342687.bin") - .as_slice() - .into(), - ) - } else if rom_from_env == &firmware::ROM_WITH_UART { - Ok( - include_bytes!("../../hw/1.0/caliptra-rom-with-log-1.0.1-9342687.bin") - .as_slice() - .into(), - ) - } else { - Err(other_err(format!("Unexpected ROM fwid {rom_from_env:?}"))) - } - } else { - Ok(build_firmware_rom(rom_from_env)?.into()) - } + Ok(build_firmware_rom(rom_from_env)?.into()) } pub fn build_firmware_rom(id: &FwId<'static>) -> io::Result> { diff --git a/cfi/lib/Cargo.toml b/cfi/lib/Cargo.toml index baec231e1e..e5fec160f3 100644 --- a/cfi/lib/Cargo.toml +++ b/cfi/lib/Cargo.toml @@ -22,6 +22,3 @@ default = ["cfi", "cfi-counter", "cfi-test"] cfi = [] cfi-counter = [] cfi-test = [] -"hw-1.0" = ["caliptra-registers/hw-1.0"] - - diff --git a/common/Cargo.toml b/common/Cargo.toml index 44415377f6..2264dd310a 100644 --- a/common/Cargo.toml +++ b/common/Cargo.toml @@ -25,4 +25,3 @@ std = [] rom = [] fmc = [] runtime = [] -"hw-1.0" = ["caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0"] diff --git a/cpu/Cargo.toml b/cpu/Cargo.toml index d5fa691d26..6503f3f606 100644 --- a/cpu/Cargo.toml +++ b/cpu/Cargo.toml @@ -12,7 +12,6 @@ edition = "2021" # --profile=firmware \ # --features riscv riscv = [] -"hw-1.0" = ["caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0"] [lib] test = false diff --git a/drivers/Cargo.toml b/drivers/Cargo.toml index 98d0bfa77d..b5393a6bd7 100644 --- a/drivers/Cargo.toml +++ b/drivers/Cargo.toml @@ -35,7 +35,6 @@ fpga_realtime = ["caliptra-hw-model/fpga_realtime"] itrng = ["caliptra-hw-model/itrng"] verilator = ["caliptra-hw-model/verilator"] no-cfi = [] -"hw-1.0" = ["caliptra-builder/hw-1.0", "caliptra-registers/hw-1.0"] fips-test-hooks = [] [dev-dependencies] diff --git a/drivers/src/hmac384.rs b/drivers/src/hmac384.rs index 809026e19a..a6c39a11d6 100644 --- a/drivers/src/hmac384.rs +++ b/drivers/src/hmac384.rs @@ -175,16 +175,9 @@ impl Hmac384 { let hmac = self.hmac.regs_mut(); let rand_data = trng.generate()?; - cfg_if::cfg_if! { - if #[cfg(feature="hw-1.0")] { - use crate::Array4x5; - let iv: [u32; 5] = rand_data.0[..5].try_into().unwrap(); - KvAccess::copy_from_arr(&Array4x5::from(iv), hmac.lfsr_seed())?; - } else { - let iv: [u32; 12] = rand_data.0[..12].try_into().unwrap(); - KvAccess::copy_from_arr(&Array4x12::from(iv), hmac.lfsr_seed())?; - } - } + let iv: [u32; 12] = rand_data.0[..12].try_into().unwrap(); + KvAccess::copy_from_arr(&Array4x12::from(iv), hmac.lfsr_seed())?; + Ok(()) } diff --git a/drivers/src/lms.rs b/drivers/src/lms.rs index 7e2a239953..667e7038bb 100644 --- a/drivers/src/lms.rs +++ b/drivers/src/lms.rs @@ -310,7 +310,6 @@ impl Lms { } // This operation is accelerated in hardware by RTL1.1 and later. - #[cfg(not(feature = "hw-1.0"))] fn hash_chain( &self, sha256_driver: &mut impl Sha256Alg, @@ -342,33 +341,6 @@ impl Lms { Ok(*tmp) } - #[cfg(feature = "hw-1.0")] - fn hash_chain( - &self, - sha256_driver: &mut impl Sha256Alg, - wnt_prefix: &mut [u8; Self::WNT_PREFIX_SIZE], - coeff: u8, - params: &LmotsParameter, - tmp: &mut HashValue, - ) -> CaliptraResult> { - let iteration_count = ((1u16 << params.w) - 1) as u8; - - for j in coeff..iteration_count { - let mut digest = Array4x8::default(); - let mut hasher = sha256_driver.digest_init()?; - wnt_prefix[Self::ITER_COUNTER_OFFSET] = j; - let mut i = Self::TMP_OFFSET; - for val in tmp.0.iter().take(N) { - wnt_prefix[i..i + 4].clone_from_slice(&val.to_be_bytes()); - i += 4; - } - hasher.update(&wnt_prefix[0..Self::TMP_OFFSET + N * 4])?; - hasher.finalize(&mut digest)?; - *tmp = HashValue::::from(digest); - } - Ok(*tmp) - } - pub fn candidate_ots_signature( &self, sha256_driver: &mut impl Sha256Alg, diff --git a/drivers/src/sha256.rs b/drivers/src/sha256.rs index 6966e50e8f..d374d7690e 100644 --- a/drivers/src/sha256.rs +++ b/drivers/src/sha256.rs @@ -23,13 +23,13 @@ const SHA256_MAX_DATA_SIZE: usize = 1024 * 1024; pub trait Sha256DigestOp<'a> { fn update(&mut self, data: &[u8]) -> CaliptraResult<()>; - #[cfg(not(feature = "hw-1.0"))] + fn update_wntz(&mut self, data: &[u8], w_value: u8, n_mode: bool) -> CaliptraResult<()>; /// # Arguments /// /// * `digest` - result of the sha256 digest operation fn finalize(self, digest: &mut Array4x8) -> CaliptraResult<()>; - #[cfg(not(feature = "hw-1.0"))] + /// # Arguments /// /// * `digest` - result of the sha256 digest operation @@ -253,7 +253,6 @@ impl Sha256 { /// * `buf_size` - Total buffer size /// * `w_value` - Winternitz W value. /// * `n_mode` - Winternitz n value(SHA192/SHA256 --> n = 24/32) - #[cfg(not(feature = "hw-1.0"))] fn digest_wntz_partial_block( &mut self, slice: &[u8], @@ -319,7 +318,6 @@ impl Sha256 { /// * `first` - Flag indicating if this is the first block /// * `w_value` - Winternitz W value. /// * `n_mode` - Winternitz n value(SHA192/SHA256 --> n = 24/32) - #[cfg(not(feature = "hw-1.0"))] fn digest_wntz_block( &mut self, block: &[u8; SHA256_BLOCK_BYTE_SIZE], @@ -337,7 +335,6 @@ impl Sha256 { // # Arguments // /// * `first` - Flag indicating if this is the first block - #[cfg(not(feature = "hw-1.0"))] fn digest_op(&mut self, first: bool) -> CaliptraResult<()> { let sha256 = self.sha256.regs_mut(); @@ -354,29 +351,6 @@ impl Sha256 { Ok(()) } - // Perform the digest operation in the hardware - // - // # Arguments - // - /// * `first` - Flag indicating if this is the first block - #[cfg(feature = "hw-1.0")] - fn digest_op(&mut self, first: bool) -> CaliptraResult<()> { - let sha256 = self.sha256.regs_mut(); - - // Wait for the hardware to be ready - wait::until(|| sha256.status().read().ready()); - - sha256 - .ctrl() - .write(|w| w.mode(true).init(first).next(!first)); - - // Wait for the digest operation to finish - wait::until(|| sha256.status().read().valid()); - - Ok(()) - } - - #[cfg(not(feature = "hw-1.0"))] // Perform the digest operation in the hardware // // # Arguments @@ -476,7 +450,6 @@ impl<'a> Sha256DigestOp<'a> for Sha256DigestOpHw<'a> { Ok(()) } - #[cfg(not(feature = "hw-1.0"))] /// Update the digest with data /// /// # Arguments @@ -542,7 +515,6 @@ impl<'a> Sha256DigestOp<'a> for Sha256DigestOpHw<'a> { } /// Finalize the digest operations - #[cfg(not(feature = "hw-1.0"))] fn finalize_wntz( mut self, digest: &mut Array4x8, diff --git a/drivers/test-fw/Cargo.toml b/drivers/test-fw/Cargo.toml index 49016ca810..e913821aab 100644 --- a/drivers/test-fw/Cargo.toml +++ b/drivers/test-fw/Cargo.toml @@ -20,7 +20,6 @@ caliptra-cfi-lib = { workspace = true, default-features = false, features = ["cf [features] emu = ["caliptra-test-harness/emu"] fpga_realtime = [] -"hw-1.0" = ["caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0"] # This feature is used to filter all these binary targets during normal builds diff --git a/fmc/Cargo.toml b/fmc/Cargo.toml index ce8cbb61f9..a2e4fd245f 100644 --- a/fmc/Cargo.toml +++ b/fmc/Cargo.toml @@ -40,4 +40,3 @@ fpga_realtime = ["caliptra-hw-model/fpga_realtime"] itrng = ["caliptra-hw-model/itrng"] verilator = ["caliptra-hw-model/verilator"] fake-fmc = [] -"hw-1.0" = ["caliptra-builder/hw-1.0", "caliptra-cpu/hw-1.0", "caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0"] diff --git a/hw-model/Cargo.toml b/hw-model/Cargo.toml index 51709c5dc7..2a0f2df48d 100644 --- a/hw-model/Cargo.toml +++ b/hw-model/Cargo.toml @@ -13,7 +13,6 @@ verilator = ["dep:caliptra-verilated"] fpga_realtime = ["dep:uio"] itrng = ["caliptra-verilated?/itrng"] coverage = ["dep:caliptra-coverage"] -"hw-1.0" = ["caliptra-emu-periph/hw-1.0"] [dependencies] bitfield.workspace = true diff --git a/hw-model/c-binding/examples/Makefile b/hw-model/c-binding/examples/Makefile index 4360a17b12..67af094a07 100644 --- a/hw-model/c-binding/examples/Makefile +++ b/hw-model/c-binding/examples/Makefile @@ -16,7 +16,7 @@ EXTRA_CARGO_CONFIG = target.'cfg(all())'.rustflags = [\"-Dwarnings\"] OUT = out TARGET = $(OUT)/smoke_test -RTL_SOC_IFC_INCLUDE_PATH = ../../../hw/1.0/rtl/src/soc_ifc/rtl +RTL_SOC_IFC_INCLUDE_PATH = ../../../hw/latest/rtl/src/soc_ifc/rtl BUILDER_PATH = ../../../builder CALIPTRA_MODEL_PATH = ../out CFLAGS += -I$(RTL_SOC_IFC_INCLUDE_PATH) -I$(CALIPTRA_MODEL_PATH) diff --git a/hw-model/test-fw/Cargo.toml b/hw-model/test-fw/Cargo.toml index 77bb8a2649..62b70b0b90 100644 --- a/hw-model/test-fw/Cargo.toml +++ b/hw-model/test-fw/Cargo.toml @@ -9,7 +9,6 @@ edition = "2021" default = [] riscv = ["caliptra-test-harness/riscv"] emu = ["caliptra-test-harness/emu"] -"hw-1.0" = ["caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0"] [dependencies] caliptra-drivers.workspace = true diff --git a/hw/1.0/caliptra-rom-1.0.1-9342687.bin b/hw/1.0/caliptra-rom-1.0.1-9342687.bin deleted file mode 100644 index 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a/hw/1.0/registers/Cargo.toml b/hw/1.0/registers/Cargo.toml deleted file mode 100644 index 8e2b23ee31..0000000000 --- a/hw/1.0/registers/Cargo.toml +++ /dev/null @@ -1,11 +0,0 @@ -# Licensed under the Apache-2.0 license. - -[package] -name = "caliptra-registers-1_0" -version = "0.1.0" -edition = "2021" - -# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html - -[dependencies] -ureg.workspace = true diff --git a/hw/1.0/registers/src/csrng.rs b/hw/1.0/registers/src/csrng.rs deleted file mode 100644 index 1d3ee51b0f..0000000000 --- a/hw/1.0/registers/src/csrng.rs +++ /dev/null @@ -1,1298 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct CsrngReg { - _priv: (), -} -impl CsrngReg { - pub const PTR: *mut u32 = 0x20002000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Read value: [`csrng::regs::InterruptStateReadVal`]; Write value: [`csrng::regs::InterruptStateWriteVal`] - #[inline(always)] - pub fn interrupt_state(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::InterruptEnableReadVal`]; Write value: [`csrng::regs::InterruptEnableWriteVal`] - #[inline(always)] - pub fn interrupt_enable(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::InterruptTestReadVal`]; Write value: [`csrng::regs::InterruptTestWriteVal`] - #[inline(always)] - pub fn interrupt_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::AlertTestReadVal`]; Write value: [`csrng::regs::AlertTestWriteVal`] - #[inline(always)] - pub fn alert_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::RegwenReadVal`]; Write value: [`csrng::regs::RegwenWriteVal`] - #[inline(always)] - pub fn regwen(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::CtrlReadVal`]; Write value: [`csrng::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::CmdReqReadVal`]; Write value: [`csrng::regs::CmdReqWriteVal`] - #[inline(always)] - pub fn cmd_req(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::SwCmdStsReadVal`]; Write value: [`csrng::regs::SwCmdStsWriteVal`] - #[inline(always)] - pub fn sw_cmd_sts(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::GenbitsVldReadVal`]; Write value: [`csrng::regs::GenbitsVldWriteVal`] - #[inline(always)] - pub fn genbits_vld(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn genbits(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x24 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::IntStateNumReadVal`]; Write value: [`csrng::regs::IntStateNumWriteVal`] - #[inline(always)] - pub fn int_state_num(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x28 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn int_state_val(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x2c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::HwExcStsReadVal`]; Write value: [`csrng::regs::HwExcStsWriteVal`] - #[inline(always)] - pub fn hw_exc_sts(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x30 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::RecovAlertStsReadVal`]; Write value: [`csrng::regs::RecovAlertStsWriteVal`] - #[inline(always)] - pub fn recov_alert_sts(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x34 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::ErrCodeReadVal`]; Write value: [`csrng::regs::ErrCodeWriteVal`] - #[inline(always)] - pub fn err_code(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x38 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::ErrCodeTestReadVal`]; Write value: [`csrng::regs::ErrCodeTestWriteVal`] - #[inline(always)] - pub fn err_code_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x3c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`csrng::regs::MainSmStateReadVal`]; Write value: [`csrng::regs::MainSmStateWriteVal`] - #[inline(always)] - pub fn main_sm_state(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x40 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct AlertTestWriteVal(u32); - impl AlertTestWriteVal { - /// Write 1 to trigger one alert event of this kind. - #[inline(always)] - pub fn recov_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write 1 to trigger one alert event of this kind. - #[inline(always)] - pub fn fatal_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for AlertTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CmdReqWriteVal(u32); - impl CmdReqWriteVal { - /// Application Command: Selects one of five operations to perform. - /// The commands supported are instantiate, reseed, generate, update, - /// and uninstantiate. Each application interface port used by peripheral - /// hardware commands a unique instance number in CSRNG. - #[inline(always)] - pub fn acmd(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - /// Command Length: Number of 32-bit words that can optionally be appended - /// to the command. A value of zero will only transfer the command header. - /// A value of 4'hc will transfer the header plus an additional twelve - /// 32-bit words of data. - #[inline(always)] - pub fn clen(self, val: u32) -> Self { - Self((self.0 & !(0xf << 4)) | ((val & 0xf) << 4)) - } - /// Command Flag0: flag0 is associated with current command. Setting this - /// field to kMultiBitBool4True will enable flag0 to be enabled. Note that - /// flag0 is used for the instantiate and reseed commands only, for all other commands its value is ignored. - #[inline(always)] - pub fn flag0(self, val: u32) -> Self { - Self((self.0 & !(0xf << 8)) | ((val & 0xf) << 8)) - } - /// Generate Length: Only defined for the generate command, this field - /// is the total number of cryptographic entropy blocks requested. Each - /// unit represents 128 bits of entropy returned. The NIST reference name - /// is max_number_of_bit_per_request, and this field size supports the - /// maximum size of 219 bits. For the maximum size, this field should be - /// set to 4096, resulting in a max_number_of_bit_per_request value of - /// 4096 x 128 bits. For a smaller example, a value of 8 would return - /// a total of 1024 bits. - #[inline(always)] - pub fn glen(self, val: u32) -> Self { - Self((self.0 & !(0x1fff << 12)) | ((val & 0x1fff) << 12)) - } - } - impl From for CmdReqWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CmdReqWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CtrlReadVal(u32); - impl CtrlReadVal { - /// Setting this field to kMultiBitBool4True will enable the CSRNG module. The modules - /// of the entropy complex may only be enabled and disabled in a specific order, see - /// Programmers Guide for details. - #[inline(always)] - pub fn enable(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Setting this field to kMultiBitBool4True will enable reading from the !!GENBITS register. - /// This application interface for software (register based) will be enabled - /// only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding. - #[inline(always)] - pub fn sw_app_enable(&self) -> u32 { - (self.0 >> 4) & 0xf - } - /// Setting this field to kMultiBitBool4True will enable reading from the !!INT_STATE_VAL register. - /// Reading the internal state of the enable instances will be enabled - /// only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding. - #[inline(always)] - pub fn read_int_state(&self) -> u32 { - (self.0 >> 8) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CtrlWriteVal { - CtrlWriteVal(self.0) - } - } - impl From for CtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// Setting this field to kMultiBitBool4True will enable the CSRNG module. The modules - /// of the entropy complex may only be enabled and disabled in a specific order, see - /// Programmers Guide for details. - #[inline(always)] - pub fn enable(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - /// Setting this field to kMultiBitBool4True will enable reading from the !!GENBITS register. - /// This application interface for software (register based) will be enabled - /// only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding. - #[inline(always)] - pub fn sw_app_enable(self, val: u32) -> Self { - Self((self.0 & !(0xf << 4)) | ((val & 0xf) << 4)) - } - /// Setting this field to kMultiBitBool4True will enable reading from the !!INT_STATE_VAL register. - /// Reading the internal state of the enable instances will be enabled - /// only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding. - #[inline(always)] - pub fn read_int_state(self, val: u32) -> Self { - Self((self.0 & !(0xf << 8)) | ((val & 0xf) << 8)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrCodeReadVal(u32); - impl ErrCodeReadVal { - /// This bit will be set to one when an error has been detected for the - /// command stage command FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_cmd_err(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// command stage genbits FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_genbits_err(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// cmdreq FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_cmdreq_err(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// rcstage FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_rcstage_err(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// keyvrc FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_keyvrc_err(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// updreq FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_updreq_err(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// bencreq FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_bencreq_err(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// bencack FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_bencack_err(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// pdata FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_pdata_err(&self) -> bool { - ((self.0 >> 8) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// final FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_final_err(&self) -> bool { - ((self.0 >> 9) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// gbencack FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_gbencack_err(&self) -> bool { - ((self.0 >> 10) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// grcstage FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_grcstage_err(&self) -> bool { - ((self.0 >> 11) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// ggenreq FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_ggenreq_err(&self) -> bool { - ((self.0 >> 12) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// gadstage FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_gadstage_err(&self) -> bool { - ((self.0 >> 13) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// ggenbits FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_ggenbits_err(&self) -> bool { - ((self.0 >> 14) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// blkenc FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_blkenc_err(&self) -> bool { - ((self.0 >> 15) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// command stage state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn cmd_stage_sm_err(&self) -> bool { - ((self.0 >> 20) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// main state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn main_sm_err(&self) -> bool { - ((self.0 >> 21) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// ctr_drbg gen state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn drbg_gen_sm_err(&self) -> bool { - ((self.0 >> 22) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// ctr_drbg update block encode state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn drbg_updbe_sm_err(&self) -> bool { - ((self.0 >> 23) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// ctr_drbg update out block state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn drbg_updob_sm_err(&self) -> bool { - ((self.0 >> 24) & 1) != 0 - } - /// This bit will be set to one when an AES fatal error has been detected. - /// This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn aes_cipher_sm_err(&self) -> bool { - ((self.0 >> 25) & 1) != 0 - } - /// This bit will be set to one when a mismatch in any of the hardened counters - /// has been detected. - /// This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn cmd_gen_cnt_err(&self) -> bool { - ((self.0 >> 26) & 1) != 0 - } - /// This bit will be set to one when any of the source bits (bits 0 through 15 of this - /// this register) are asserted as a result of an error pulse generated from - /// any full FIFO that has been recieved a write pulse. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn fifo_write_err(&self) -> bool { - ((self.0 >> 28) & 1) != 0 - } - /// This bit will be set to one when any of the source bits (bits 0 through 15 of this - /// this register) are asserted as a result of an error pulse generated from - /// any empty FIFO that has recieved a read pulse. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn fifo_read_err(&self) -> bool { - ((self.0 >> 29) & 1) != 0 - } - /// This bit will be set to one when any of the source bits (bits 0 through 15 of this - /// this register) are asserted as a result of an error pulse generated from - /// any FIFO where both the empty and full status bits are set. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn fifo_state_err(&self) -> bool { - ((self.0 >> 30) & 1) != 0 - } - } - impl From for ErrCodeReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrCodeReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrCodeTestReadVal(u32); - impl ErrCodeTestReadVal { - /// Setting this field will set the bit number for which an error - /// will be forced in the hardware. This bit number is that same one - /// found in the !!ERR_CODE register. The action of writing this - /// register will force an error pulse. The sole purpose of this - /// register is to test that any error properly propagates to either - /// an interrupt or an alert. - #[inline(always)] - pub fn err_code_test(&self) -> u32 { - (self.0 >> 0) & 0x1f - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrCodeTestWriteVal { - ErrCodeTestWriteVal(self.0) - } - } - impl From for ErrCodeTestReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrCodeTestReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrCodeTestWriteVal(u32); - impl ErrCodeTestWriteVal { - /// Setting this field will set the bit number for which an error - /// will be forced in the hardware. This bit number is that same one - /// found in the !!ERR_CODE register. The action of writing this - /// register will force an error pulse. The sole purpose of this - /// register is to test that any error properly propagates to either - /// an interrupt or an alert. - #[inline(always)] - pub fn err_code_test(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 0)) | ((val & 0x1f) << 0)) - } - } - impl From for ErrCodeTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrCodeTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GenbitsVldReadVal(u32); - impl GenbitsVldReadVal { - /// This bit is set when genbits are available on this application interface. - #[inline(always)] - pub fn genbits_vld(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// This bit is set when genbits are FIPS/CC compliant. - #[inline(always)] - pub fn genbits_fips(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for GenbitsVldReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GenbitsVldReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct HwExcStsReadVal(u32); - impl HwExcStsReadVal { - /// Reading this register indicates whether one of the CSRNG HW instances has - /// encountered an exception. Each bit corresponds to a particular hardware - /// instance, with bit 0 corresponding to instance HW0, bit 1 corresponding - /// to instance HW1, and so forth. (To monitor the status of requests made - /// to the SW instance, check the !!SW_CMD_STS register). Writing a zero to this register - /// resets the status bits. - #[inline(always)] - pub fn hw_exc_sts(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> HwExcStsWriteVal { - HwExcStsWriteVal(self.0) - } - } - impl From for HwExcStsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: HwExcStsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct HwExcStsWriteVal(u32); - impl HwExcStsWriteVal { - /// Reading this register indicates whether one of the CSRNG HW instances has - /// encountered an exception. Each bit corresponds to a particular hardware - /// instance, with bit 0 corresponding to instance HW0, bit 1 corresponding - /// to instance HW1, and so forth. (To monitor the status of requests made - /// to the SW instance, check the !!SW_CMD_STS register). Writing a zero to this register - /// resets the status bits. - #[inline(always)] - pub fn hw_exc_sts(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - } - impl From for HwExcStsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: HwExcStsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableReadVal(u32); - impl InterruptEnableReadVal { - /// Enable interrupt when cs_cmd_req_done is set. - #[inline(always)] - pub fn cs_cmd_req_done(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable interrupt when cs_entropy_req is set. - #[inline(always)] - pub fn cs_entropy_req(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable interrupt when cs_hw_inst_exc is set. - #[inline(always)] - pub fn cs_hw_inst_exc(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable interrupt when cs_fatal_err is set. - #[inline(always)] - pub fn cs_fatal_err(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptEnableWriteVal { - InterruptEnableWriteVal(self.0) - } - } - impl From for InterruptEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableWriteVal(u32); - impl InterruptEnableWriteVal { - /// Enable interrupt when cs_cmd_req_done is set. - #[inline(always)] - pub fn cs_cmd_req_done(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable interrupt when cs_entropy_req is set. - #[inline(always)] - pub fn cs_entropy_req(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable interrupt when cs_hw_inst_exc is set. - #[inline(always)] - pub fn cs_hw_inst_exc(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable interrupt when cs_fatal_err is set. - #[inline(always)] - pub fn cs_fatal_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for InterruptEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateReadVal(u32); - impl InterruptStateReadVal { - /// Asserted when a command request is completed. - #[inline(always)] - pub fn cs_cmd_req_done(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Asserted when a request for entropy has been made. - #[inline(always)] - pub fn cs_entropy_req(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Asserted when a hardware-attached CSRNG instance encounters a command exception - #[inline(always)] - pub fn cs_hw_inst_exc(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Asserted when a FIFO error or a fatal alert occurs. Check the !!ERR_CODE register to get more information. - #[inline(always)] - pub fn cs_fatal_err(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptStateWriteVal { - InterruptStateWriteVal(self.0) - } - } - impl From for InterruptStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateWriteVal(u32); - impl InterruptStateWriteVal { - /// Asserted when a command request is completed. - #[inline(always)] - pub fn cs_cmd_req_done(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Asserted when a request for entropy has been made. - #[inline(always)] - pub fn cs_entropy_req(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Asserted when a hardware-attached CSRNG instance encounters a command exception - #[inline(always)] - pub fn cs_hw_inst_exc(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Asserted when a FIFO error or a fatal alert occurs. Check the !!ERR_CODE register to get more information. - #[inline(always)] - pub fn cs_fatal_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for InterruptStateWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptTestWriteVal(u32); - impl InterruptTestWriteVal { - /// Write 1 to force cs_cmd_req_done to 1. - #[inline(always)] - pub fn cs_cmd_req_done(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write 1 to force cs_entropy_req to 1. - #[inline(always)] - pub fn cs_entropy_req(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Write 1 to force cs_hw_inst_exc to 1. - #[inline(always)] - pub fn cs_hw_inst_exc(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Write 1 to force cs_fatal_err to 1. - #[inline(always)] - pub fn cs_fatal_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for InterruptTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntStateNumReadVal(u32); - impl IntStateNumReadVal { - /// Setting this field will set the number for which internal state can be - /// selected for a read access. Up to 16 internal state values can be chosen - /// from this register. The actual number of valid internal state fields - /// is set by parameter NHwApps plus 1 software app. For those selections that point - /// to reserved locations (greater than NHwApps plus 1), the returned value - /// will be zero. Writing this register will also reset the internal read - /// pointer for the !!INT_STATE_VAL register. - /// Note: This register should be read back after being written to ensure - /// that the !!INT_STATE_VAL read back is accurate. - #[inline(always)] - pub fn int_state_num(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> IntStateNumWriteVal { - IntStateNumWriteVal(self.0) - } - } - impl From for IntStateNumReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntStateNumReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntStateNumWriteVal(u32); - impl IntStateNumWriteVal { - /// Setting this field will set the number for which internal state can be - /// selected for a read access. Up to 16 internal state values can be chosen - /// from this register. The actual number of valid internal state fields - /// is set by parameter NHwApps plus 1 software app. For those selections that point - /// to reserved locations (greater than NHwApps plus 1), the returned value - /// will be zero. Writing this register will also reset the internal read - /// pointer for the !!INT_STATE_VAL register. - /// Note: This register should be read back after being written to ensure - /// that the !!INT_STATE_VAL read back is accurate. - #[inline(always)] - pub fn int_state_num(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - } - impl From for IntStateNumWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntStateNumWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MainSmStateReadVal(u32); - impl MainSmStateReadVal { - /// This is the state of the CSRNG main state machine. - /// See the RTL file `csrng_main_sm` for the meaning of the values. - #[inline(always)] - pub fn main_sm_state(&self) -> u32 { - (self.0 >> 0) & 0xff - } - } - impl From for MainSmStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MainSmStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RecovAlertStsReadVal(u32); - impl RecovAlertStsReadVal { - /// This bit is set when the ENABLE field in the !!CTRL register is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn enable_field_alert(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// This bit is set when the SW_APP_ENABLE field in the !!CTRL register is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn sw_app_enable_field_alert(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// This bit is set when the READ_INT_STATE field in the !!CTRL register is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn read_int_state_field_alert(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// This bit is set when the FLAG0 field in the Application Command is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn acmd_flag0_field_alert(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// This bit is set when the software application port genbits bus value is equal - /// to the prior valid value on the bus, indicating a possible attack. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn cs_bus_cmp_alert(&self) -> bool { - ((self.0 >> 12) & 1) != 0 - } - /// This bit is set when an unsupported/illegal CSRNG command is being processed. - /// The main FSM will hang unless the module enable field is set to the disabled state. - #[inline(always)] - pub fn cs_main_sm_alert(&self) -> bool { - ((self.0 >> 13) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> RecovAlertStsWriteVal { - RecovAlertStsWriteVal(self.0) - } - } - impl From for RecovAlertStsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RecovAlertStsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RecovAlertStsWriteVal(u32); - impl RecovAlertStsWriteVal { - /// This bit is set when the ENABLE field in the !!CTRL register is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn enable_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// This bit is set when the SW_APP_ENABLE field in the !!CTRL register is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn sw_app_enable_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// This bit is set when the READ_INT_STATE field in the !!CTRL register is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn read_int_state_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// This bit is set when the FLAG0 field in the Application Command is set to - /// a value other than kMultiBitBool4True or kMultiBitBool4False. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn acmd_flag0_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// This bit is set when the software application port genbits bus value is equal - /// to the prior valid value on the bus, indicating a possible attack. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn cs_bus_cmp_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 12)) | (u32::from(val) << 12)) - } - /// This bit is set when an unsupported/illegal CSRNG command is being processed. - /// The main FSM will hang unless the module enable field is set to the disabled state. - #[inline(always)] - pub fn cs_main_sm_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 13)) | (u32::from(val) << 13)) - } - } - impl From for RecovAlertStsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RecovAlertStsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RegwenReadVal(u32); - impl RegwenReadVal { - /// When true, all writeable registers can be modified. - /// When false, they become read-only. - #[inline(always)] - pub fn regwen(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> RegwenWriteVal { - RegwenWriteVal(self.0) - } - } - impl From for RegwenReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RegwenReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RegwenWriteVal(u32); - impl RegwenWriteVal { - /// When true, all writeable registers can be modified. - /// When false, they become read-only. - #[inline(always)] - pub fn regwen(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for RegwenWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RegwenWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct SwCmdStsReadVal(u32); - impl SwCmdStsReadVal { - /// This bit indicates when the command interface is ready to accept commands. - #[inline(always)] - pub fn cmd_rdy(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// This one bit field is the status code returned with the application command ack. - /// It is updated each time a command ack is asserted on the internal application - /// interface for software use. - /// 0b0: Request completed successfully - /// 0b1: Request completed with an error - #[inline(always)] - pub fn cmd_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for SwCmdStsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: SwCmdStsReadVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type InterruptState = ureg::ReadWriteReg32< - 0, - crate::csrng::regs::InterruptStateReadVal, - crate::csrng::regs::InterruptStateWriteVal, - >; - pub type InterruptEnable = ureg::ReadWriteReg32< - 0, - crate::csrng::regs::InterruptEnableReadVal, - crate::csrng::regs::InterruptEnableWriteVal, - >; - pub type InterruptTest = ureg::WriteOnlyReg32<0, crate::csrng::regs::InterruptTestWriteVal>; - pub type AlertTest = ureg::WriteOnlyReg32<0, crate::csrng::regs::AlertTestWriteVal>; - pub type Regwen = ureg::ReadWriteReg32< - 1, - crate::csrng::regs::RegwenReadVal, - crate::csrng::regs::RegwenWriteVal, - >; - pub type Ctrl = ureg::ReadWriteReg32< - 0x999, - crate::csrng::regs::CtrlReadVal, - crate::csrng::regs::CtrlWriteVal, - >; - pub type CmdReq = ureg::WriteOnlyReg32<0, crate::csrng::regs::CmdReqWriteVal>; - pub type SwCmdSts = ureg::ReadOnlyReg32; - pub type GenbitsVld = ureg::ReadOnlyReg32; - pub type Genbits = ureg::ReadOnlyReg32; - pub type IntStateNum = ureg::ReadWriteReg32< - 0, - crate::csrng::regs::IntStateNumReadVal, - crate::csrng::regs::IntStateNumWriteVal, - >; - pub type IntStateVal = ureg::ReadOnlyReg32; - pub type HwExcSts = ureg::ReadWriteReg32< - 0, - crate::csrng::regs::HwExcStsReadVal, - crate::csrng::regs::HwExcStsWriteVal, - >; - pub type RecovAlertSts = ureg::ReadWriteReg32< - 0, - crate::csrng::regs::RecovAlertStsReadVal, - crate::csrng::regs::RecovAlertStsWriteVal, - >; - pub type ErrCode = ureg::ReadOnlyReg32; - pub type ErrCodeTest = ureg::ReadWriteReg32< - 0, - crate::csrng::regs::ErrCodeTestReadVal, - crate::csrng::regs::ErrCodeTestWriteVal, - >; - pub type MainSmState = ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/doe.rs b/hw/1.0/registers/src/doe.rs deleted file mode 100644 index fc7905f6e9..0000000000 --- a/hw/1.0/registers/src/doe.rs +++ /dev/null @@ -1,1206 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct DoeReg { - _priv: (), -} -impl DoeReg { - pub const PTR: *mut u32 = 0x10000000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// 4 32-bit registers storing the 128-bit IV. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn iv(&self) -> ureg::Array<4, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the de-obfuscation command to run - /// - /// Read value: [`doe::regs::CtrlReadVal`]; Write value: [`doe::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides status of the DOE block and the status of the flows it runs - /// - /// Read value: [`doe::regs::StatusReadVal`]; Write value: [`doe::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrEnTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::NotifIntrEnTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error0_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error1_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error2_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error3_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error0_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error1_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error2_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error3_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x210 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CtrlReadVal(u32); - impl CtrlReadVal { - /// Indicates the command for DOE to run - #[inline(always)] - pub fn cmd(&self) -> super::enums::DoeCmdE { - super::enums::DoeCmdE::try_from((self.0 >> 0) & 3).unwrap() - } - /// Key Vault entry to store the result. - #[inline(always)] - pub fn dest(&self) -> u32 { - (self.0 >> 2) & 0x1f - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CtrlWriteVal { - CtrlWriteVal(self.0) - } - } - impl From for CtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// Indicates the command for DOE to run - #[inline(always)] - pub fn cmd( - self, - f: impl FnOnce(super::enums::selector::DoeCmdESelector) -> super::enums::DoeCmdE, - ) -> Self { - Self( - (self.0 & !(3 << 0)) - | (u32::from(f(super::enums::selector::DoeCmdESelector())) << 0), - ) - } - /// Key Vault entry to store the result. - #[inline(always)] - pub fn dest(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 2)) | ((val & 0x1f) << 2)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Status ready bit - Indicates if the core is ready to take a control command and process the block. - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Status valid bit - Indicates if the process is done and the results have been stored in the keyvault. - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// UDS Flow Completed - #[inline(always)] - pub fn uds_flow_done(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// FE flow completed - #[inline(always)] - pub fn fe_flow_done(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Clear Secrets flow completed - #[inline(always)] - pub fn deobf_secrets_cleared(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTReadVal(u32); - impl GlobalIntrEnTReadVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> GlobalIntrEnTWriteVal { - GlobalIntrEnTWriteVal(self.0) - } - } - impl From for GlobalIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTWriteVal(u32); - impl GlobalIntrEnTWriteVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for GlobalIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrTReadVal(u32); - impl GlobalIntrTReadVal { - /// Interrupt Event Aggregation status bit - #[inline(always)] - pub fn agg_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for GlobalIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntrCountIncrTReadVal(u32); - impl IntrCountIncrTReadVal { - /// Pulse mirrors interrupt event occurrence - #[inline(always)] - pub fn pulse(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for IntrCountIncrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntrCountIncrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum DoeCmdE { - DoeIdle = 0, - DoeUds = 1, - DoeFe = 2, - DoeClearObfSecrets = 3, - } - impl DoeCmdE { - #[inline(always)] - pub fn doe_idle(&self) -> bool { - *self == Self::DoeIdle - } - #[inline(always)] - pub fn doe_uds(&self) -> bool { - *self == Self::DoeUds - } - #[inline(always)] - pub fn doe_fe(&self) -> bool { - *self == Self::DoeFe - } - #[inline(always)] - pub fn doe_clear_obf_secrets(&self) -> bool { - *self == Self::DoeClearObfSecrets - } - } - impl TryFrom for DoeCmdE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 4 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: DoeCmdE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct DoeCmdESelector(); - impl DoeCmdESelector { - #[inline(always)] - pub fn doe_idle(&self) -> super::DoeCmdE { - super::DoeCmdE::DoeIdle - } - #[inline(always)] - pub fn doe_uds(&self) -> super::DoeCmdE { - super::DoeCmdE::DoeUds - } - #[inline(always)] - pub fn doe_fe(&self) -> super::DoeCmdE { - super::DoeCmdE::DoeFe - } - #[inline(always)] - pub fn doe_clear_obf_secrets(&self) -> super::DoeCmdE { - super::DoeCmdE::DoeClearObfSecrets - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Iv = ureg::ReadWriteReg32<0, u32, u32>; - pub type Ctrl = - ureg::ReadWriteReg32<0, crate::doe::regs::CtrlReadVal, crate::doe::regs::CtrlWriteVal>; - pub type Status = ureg::ReadOnlyReg32; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrEnTReadVal, - crate::sha512_acc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrEnTReadVal, - crate::sha512_acc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTReadVal, - crate::sha512_acc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTReadVal, - crate::sha512_acc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTrigTReadVal, - crate::sha512_acc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTrigTReadVal, - crate::sha512_acc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfError0IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError1IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError2IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError3IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdDoneIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError0IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError1IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError2IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError3IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdDoneIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/dv.rs b/hw/1.0/registers/src/dv.rs deleted file mode 100644 index 0310b52ad9..0000000000 --- a/hw/1.0/registers/src/dv.rs +++ /dev/null @@ -1,326 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct DvReg { - _priv: (), -} -impl DvReg { - pub const PTR: *mut u32 = 0x1001c000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Controls for the Sticky Data Vault Entries (cleared on hard reset) - /// - /// Read value: [`dv::regs::DatavaultctrlReadVal`]; Write value: [`dv::regs::DatavaultctrlWriteVal`] - #[inline(always)] - pub fn sticky_data_vault_ctrl( - &self, - ) -> ureg::Array<10, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn sticky_data_vault_entry( - &self, - ) -> ureg::Array<10, ureg::Array<12, ureg::RegRef>> - { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x28 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls for the Data Vault Entries (cleared on warm reset) - /// - /// Read value: [`dv::regs::DatavaultctrlReadVal`]; Write value: [`dv::regs::DatavaultctrlWriteVal`] - #[inline(always)] - pub fn data_vault_ctrl( - &self, - ) -> ureg::Array<10, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn data_vault_entry( - &self, - ) -> ureg::Array<10, ureg::Array<12, ureg::RegRef>> - { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x230 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Scratch Register Controls (cleared on warm reset) - /// - /// Read value: [`dv::regs::LockablescratchregctrlReadVal`]; Write value: [`dv::regs::LockablescratchregctrlWriteVal`] - #[inline(always)] - pub fn lockable_scratch_reg_ctrl( - &self, - ) -> ureg::Array<10, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x410 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Scratch Register Entrie (cleared on hard reset) - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn lockable_scratch_reg( - &self, - ) -> ureg::Array<10, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x438 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn non_sticky_generic_scratch_reg( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x460 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Sticky Scratch Register Controls (cleared on hard reset) - /// - /// Read value: [`dv::regs::LockablescratchregctrlReadVal`]; Write value: [`dv::regs::LockablescratchregctrlWriteVal`] - #[inline(always)] - pub fn sticky_lockable_scratch_reg_ctrl( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x480 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Sticky Scratch Register Entries (cleared on hard reset) - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn sticky_lockable_scratch_reg( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x4a0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct DatavaultctrlReadVal(u32); - impl DatavaultctrlReadVal { - /// Lock writes to this entry. Writes will be suppressed when locked. - #[inline(always)] - pub fn lock_entry(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> DatavaultctrlWriteVal { - DatavaultctrlWriteVal(self.0) - } - } - impl From for DatavaultctrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: DatavaultctrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct DatavaultctrlWriteVal(u32); - impl DatavaultctrlWriteVal { - /// Lock writes to this entry. Writes will be suppressed when locked. - #[inline(always)] - pub fn lock_entry(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for DatavaultctrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: DatavaultctrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct LockablescratchregctrlReadVal(u32); - impl LockablescratchregctrlReadVal { - /// Lock writes to the Scratch registers. Writes will be suppressed when locked. - #[inline(always)] - pub fn lock_entry(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> LockablescratchregctrlWriteVal { - LockablescratchregctrlWriteVal(self.0) - } - } - impl From for LockablescratchregctrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: LockablescratchregctrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct LockablescratchregctrlWriteVal(u32); - impl LockablescratchregctrlWriteVal { - /// Lock writes to the Scratch registers. Writes will be suppressed when locked. - #[inline(always)] - pub fn lock_entry(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for LockablescratchregctrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: LockablescratchregctrlWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Stickydatavaultctrl = ureg::ReadWriteReg32< - 0, - crate::dv::regs::DatavaultctrlReadVal, - crate::dv::regs::DatavaultctrlWriteVal, - >; - pub type StickyDataVaultEntry = ureg::ReadWriteReg32<0, u32, u32>; - pub type Datavaultctrl = ureg::ReadWriteReg32< - 0, - crate::dv::regs::DatavaultctrlReadVal, - crate::dv::regs::DatavaultctrlWriteVal, - >; - pub type DataVaultEntry = ureg::ReadWriteReg32<0, u32, u32>; - pub type Lockablescratchregctrl = ureg::ReadWriteReg32< - 0, - crate::dv::regs::LockablescratchregctrlReadVal, - crate::dv::regs::LockablescratchregctrlWriteVal, - >; - pub type Lockablescratchreg = ureg::ReadWriteReg32<0, u32, u32>; - pub type Nonstickygenericscratchreg = ureg::ReadWriteReg32<0, u32, u32>; - pub type Stickylockablescratchregctrl = ureg::ReadWriteReg32< - 0, - crate::dv::regs::LockablescratchregctrlReadVal, - crate::dv::regs::LockablescratchregctrlWriteVal, - >; - pub type Stickylockablescratchreg = ureg::ReadWriteReg32<0, u32, u32>; -} diff --git a/hw/1.0/registers/src/ecc.rs b/hw/1.0/registers/src/ecc.rs deleted file mode 100644 index a9f7a91a7c..0000000000 --- a/hw/1.0/registers/src/ecc.rs +++ /dev/null @@ -1,1480 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct EccReg { - _priv: (), -} -impl EccReg { - pub const PTR: *mut u32 = 0x10008000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Two 32-bit read-only registers repereseting of the name - /// of ECC component. These registers are located at - /// ECC_base_address + 0x0000_0000 and 0x0000_0004 addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn name(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Two 32-bit read-only registers repereseting of the version - /// of ECC component. These registers are located at - /// ECC_base_address + 0x0000_0008 and 0x0000_000C addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn version(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 4-bit register to set the type of ECC operations. - /// [br] bit #[1:0]: This can be: - /// [br] 00 for NONE - /// [br] 01 for KEYGEN - /// [br] 10 for SIGNING - /// [br] 11 for VERIFYING - /// [br] bit #2: Zeroize all internal registers after ECC process, to avoid SCA leakage. - /// [br] bit #3: Run ECC Signing flow to sign PCRs. - /// [br] This register is located at ECC_base_address + 0x0000_0010. - /// - /// Read value: [`ecc::regs::CtrlReadVal`]; Write value: [`ecc::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 2-bit register including the following flags: - /// bit #0: READY : ​Indicates if the core is ready to take - /// a control command and process the block. - /// bit #1: VALID : ​Indicates if the process is done and the - /// hash value stored in DIGEST registers is valid. - /// This register is located at ECC_base_address + 0x0000_0018. - /// - /// Read value: [`ecc::regs::StatusReadVal`]; Write value: [`ecc::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the 384-bit seed for keygen. - /// The seed can be any 384-bit value in [0 : 2^384-1]. - /// These registers are located at ECC_base_address + - /// 0x0000_0080 to 0x0000_00AC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn seed(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x80 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the hash of the message respect - /// to SHA384 algorithm. - /// The hashed message can be any 384-bit value in [0 : 2^384-1]. - /// These registers are located at ECC_base_address + - /// 0x0000_0100 to 0x0000_012C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn msg(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the private key for keygen. - /// These registers is read by ECC user after keygen operation. - /// The private key is in [1 : q-1] while q is the group - /// order of the Secp384r1 curve. - /// These registers are located at ECC_base_address + - /// 0x0000_0180 to 0x0000_01AC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn privkey_out( - &self, - ) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the x coordinate of public key. - /// These registers is read by ECC user after keygen operation, - /// or be set before verifying operation. - /// The public key x should be in [1 : p-1] while p is the prime - /// number of the Secp384r1 curve. - /// These registers are located at ECC_base_address + - /// 0x0000_0200 to 0x0000_022C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn pubkey_x(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the y coordinate of public key. - /// These registers is read by ECC user after keygen operation, - /// or be set before verifying operation. - /// The public key y should be in [1 : p-1] while p is the prime - /// number of the Secp384r1 curve. - /// These registers are located at ECC_base_address + - /// 0x0000_0280 to 0x0000_02AC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn pubkey_y(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x280 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the signature R of the message. - /// These registers is read by ECC user after signing operation, - /// or be set before verifying operation. - /// The signature R should be in [1 : q-1] while q is the group - /// order of the Secp384r1 curve. - /// Based on RFC6979, If R turns out to be zero, a new nonce (by changing - /// the private key or the message) should be selected and R computed - /// again (this is an utterly improbable occurrence). - /// These registers are located at ECC_base_address + - /// 0x0000_0300 to 0x0000_032C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn sign_r(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x300 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the signature S of the message. - /// These registers is read by ECC user after signing operation, - /// or be set before verifying operation. - /// The signature S should be in [1 : q-1] while q is the group - /// order of the Secp384r1 curve. - /// These registers are located at ECC_base_address + - /// 0x0000_0380 to 0x0000_03AC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn sign_s(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x380 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the result of verifying operation. - /// Firmware is responsible for comparing the computed result with - /// the signature R, and if they are equal the signature is valid. - /// The verify R result should be in [1 : q-1] while q is the group - /// order of the Secp384r1 curve. - /// These registers are located at ECC_base_address + - /// 0x0000_0400 to 0x0000_042C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn verify_r(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x400 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the 384-bit IV required - /// for SCA countermeasures to randomize the inputs with no change - /// on the ECC outputs. - /// The IV can be any 384-bit value in [0 : 2^384-1]. - /// These registers are located at ECC_base_address + - /// 0x0000_0480 to 0x0000_04AC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn iv(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x480 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the 384-bit nonce for keygen. - /// The nonce can be any 384-bit value in [0 : 2^384-1]. - /// These registers are located at ECC_base_address + - /// 0x0000_0500 to 0x0000_052C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn nonce(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x500 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the private key for signing. - /// These registers is set before signing operation. - /// The private key should be in [1 : q-1] while q is the group - /// order of the Secp384r1 curve. - /// These registers are located at ECC_base_address + - /// 0x0000_0580 to 0x0000_05AC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn privkey_in(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x580 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault read access for this engine - /// - /// Read value: [`regs::KvReadCtrlRegReadVal`]; Write value: [`regs::KvReadCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_rd_pkey_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x600 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_rd_pkey_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x604 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault read access for this engine - /// - /// Read value: [`regs::KvReadCtrlRegReadVal`]; Write value: [`regs::KvReadCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_rd_seed_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x608 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_rd_seed_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x60c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault write access for this engine - /// - /// Read value: [`regs::KvWriteCtrlRegReadVal`]; Write value: [`regs::KvWriteCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_wr_pkey_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x610 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_wr_pkey_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x614 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`ecc::regs::ErrorIntrEnTReadVal`]; Write value: [`ecc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`ecc::regs::NotifIntrEnTReadVal`]; Write value: [`ecc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`ecc::regs::ErrorIntrTReadVal`]; Write value: [`ecc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`ecc::regs::NotifIntrTReadVal`]; Write value: [`ecc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`ecc::regs::ErrorIntrTrigTReadVal`]; Write value: [`ecc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`ecc::regs::NotifIntrTrigTReadVal`]; Write value: [`ecc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_internal_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// Control command field - #[inline(always)] - pub fn ctrl( - self, - f: impl FnOnce(super::enums::selector::CtrlSelector) -> super::enums::Ctrl, - ) -> Self { - Self((self.0 & !(3 << 0)) | (u32::from(f(super::enums::selector::CtrlSelector())) << 0)) - } - /// Zeroize all internal registers - #[inline(always)] - pub fn zeroize(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Run PCR Signing flow - #[inline(always)] - pub fn pcr_sign(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Status ready bit - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Status valid bit - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Internal Errors - #[inline(always)] - pub fn error_internal_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Internal Errors - #[inline(always)] - pub fn error_internal_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Internal Errors status bit - #[inline(always)] - pub fn error_internal_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Internal Errors status bit - #[inline(always)] - pub fn error_internal_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Internal Errors trigger bit - #[inline(always)] - pub fn error_internal_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Internal Errors trigger bit - #[inline(always)] - pub fn error_internal_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Done - #[inline(always)] - pub fn notif_cmd_done_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Done - #[inline(always)] - pub fn notif_cmd_done_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Done status bit - #[inline(always)] - pub fn notif_cmd_done_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Done status bit - #[inline(always)] - pub fn notif_cmd_done_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Command Done trigger bit - #[inline(always)] - pub fn notif_cmd_done_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Command Done trigger bit - #[inline(always)] - pub fn notif_cmd_done_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum Ctrl { - None = 0, - Keygen = 1, - Signing = 2, - Verifying = 3, - } - impl Ctrl { - #[inline(always)] - pub fn none(&self) -> bool { - *self == Self::None - } - #[inline(always)] - pub fn keygen(&self) -> bool { - *self == Self::Keygen - } - #[inline(always)] - pub fn signing(&self) -> bool { - *self == Self::Signing - } - #[inline(always)] - pub fn verifying(&self) -> bool { - *self == Self::Verifying - } - } - impl TryFrom for Ctrl { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 4 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: Ctrl) -> Self { - val as u32 - } - } - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum KvErrorE { - Success = 0, - KvReadFail = 1, - KvWriteFail = 2, - Reserved3 = 3, - Reserved4 = 4, - Reserved5 = 5, - Reserved6 = 6, - Reserved7 = 7, - Reserved8 = 8, - Reserved9 = 9, - Reserved10 = 10, - Reserved11 = 11, - Reserved12 = 12, - Reserved13 = 13, - Reserved14 = 14, - Reserved15 = 15, - Reserved16 = 16, - Reserved17 = 17, - Reserved18 = 18, - Reserved19 = 19, - Reserved20 = 20, - Reserved21 = 21, - Reserved22 = 22, - Reserved23 = 23, - Reserved24 = 24, - Reserved25 = 25, - Reserved26 = 26, - Reserved27 = 27, - Reserved28 = 28, - Reserved29 = 29, - Reserved30 = 30, - Reserved31 = 31, - Reserved32 = 32, - Reserved33 = 33, - Reserved34 = 34, - Reserved35 = 35, - Reserved36 = 36, - Reserved37 = 37, - Reserved38 = 38, - Reserved39 = 39, - Reserved40 = 40, - Reserved41 = 41, - Reserved42 = 42, - Reserved43 = 43, - Reserved44 = 44, - Reserved45 = 45, - Reserved46 = 46, - Reserved47 = 47, - Reserved48 = 48, - Reserved49 = 49, - Reserved50 = 50, - Reserved51 = 51, - Reserved52 = 52, - Reserved53 = 53, - Reserved54 = 54, - Reserved55 = 55, - Reserved56 = 56, - Reserved57 = 57, - Reserved58 = 58, - Reserved59 = 59, - Reserved60 = 60, - Reserved61 = 61, - Reserved62 = 62, - Reserved63 = 63, - Reserved64 = 64, - Reserved65 = 65, - Reserved66 = 66, - Reserved67 = 67, - Reserved68 = 68, - Reserved69 = 69, - Reserved70 = 70, - Reserved71 = 71, - Reserved72 = 72, - Reserved73 = 73, - Reserved74 = 74, - Reserved75 = 75, - Reserved76 = 76, - Reserved77 = 77, - Reserved78 = 78, - Reserved79 = 79, - Reserved80 = 80, - Reserved81 = 81, - Reserved82 = 82, - Reserved83 = 83, - Reserved84 = 84, - Reserved85 = 85, - Reserved86 = 86, - Reserved87 = 87, - Reserved88 = 88, - Reserved89 = 89, - Reserved90 = 90, - Reserved91 = 91, - Reserved92 = 92, - Reserved93 = 93, - Reserved94 = 94, - Reserved95 = 95, - Reserved96 = 96, - Reserved97 = 97, - Reserved98 = 98, - Reserved99 = 99, - Reserved100 = 100, - Reserved101 = 101, - Reserved102 = 102, - Reserved103 = 103, - Reserved104 = 104, - Reserved105 = 105, - Reserved106 = 106, - Reserved107 = 107, - Reserved108 = 108, - Reserved109 = 109, - Reserved110 = 110, - Reserved111 = 111, - Reserved112 = 112, - Reserved113 = 113, - Reserved114 = 114, - Reserved115 = 115, - Reserved116 = 116, - Reserved117 = 117, - Reserved118 = 118, - Reserved119 = 119, - Reserved120 = 120, - Reserved121 = 121, - Reserved122 = 122, - Reserved123 = 123, - Reserved124 = 124, - Reserved125 = 125, - Reserved126 = 126, - Reserved127 = 127, - Reserved128 = 128, - Reserved129 = 129, - Reserved130 = 130, - Reserved131 = 131, - Reserved132 = 132, - Reserved133 = 133, - Reserved134 = 134, - Reserved135 = 135, - Reserved136 = 136, - Reserved137 = 137, - Reserved138 = 138, - Reserved139 = 139, - Reserved140 = 140, - Reserved141 = 141, - Reserved142 = 142, - Reserved143 = 143, - Reserved144 = 144, - Reserved145 = 145, - Reserved146 = 146, - Reserved147 = 147, - Reserved148 = 148, - Reserved149 = 149, - Reserved150 = 150, - Reserved151 = 151, - Reserved152 = 152, - Reserved153 = 153, - Reserved154 = 154, - Reserved155 = 155, - Reserved156 = 156, - Reserved157 = 157, - Reserved158 = 158, - Reserved159 = 159, - Reserved160 = 160, - Reserved161 = 161, - Reserved162 = 162, - Reserved163 = 163, - Reserved164 = 164, - Reserved165 = 165, - Reserved166 = 166, - Reserved167 = 167, - Reserved168 = 168, - Reserved169 = 169, - Reserved170 = 170, - Reserved171 = 171, - Reserved172 = 172, - Reserved173 = 173, - Reserved174 = 174, - Reserved175 = 175, - Reserved176 = 176, - Reserved177 = 177, - Reserved178 = 178, - Reserved179 = 179, - Reserved180 = 180, - Reserved181 = 181, - Reserved182 = 182, - Reserved183 = 183, - Reserved184 = 184, - Reserved185 = 185, - Reserved186 = 186, - Reserved187 = 187, - Reserved188 = 188, - Reserved189 = 189, - Reserved190 = 190, - Reserved191 = 191, - Reserved192 = 192, - Reserved193 = 193, - Reserved194 = 194, - Reserved195 = 195, - Reserved196 = 196, - Reserved197 = 197, - Reserved198 = 198, - Reserved199 = 199, - Reserved200 = 200, - Reserved201 = 201, - Reserved202 = 202, - Reserved203 = 203, - Reserved204 = 204, - Reserved205 = 205, - Reserved206 = 206, - Reserved207 = 207, - Reserved208 = 208, - Reserved209 = 209, - Reserved210 = 210, - Reserved211 = 211, - Reserved212 = 212, - Reserved213 = 213, - Reserved214 = 214, - Reserved215 = 215, - Reserved216 = 216, - Reserved217 = 217, - Reserved218 = 218, - Reserved219 = 219, - Reserved220 = 220, - Reserved221 = 221, - Reserved222 = 222, - Reserved223 = 223, - Reserved224 = 224, - Reserved225 = 225, - Reserved226 = 226, - Reserved227 = 227, - Reserved228 = 228, - Reserved229 = 229, - Reserved230 = 230, - Reserved231 = 231, - Reserved232 = 232, - Reserved233 = 233, - Reserved234 = 234, - Reserved235 = 235, - Reserved236 = 236, - Reserved237 = 237, - Reserved238 = 238, - Reserved239 = 239, - Reserved240 = 240, - Reserved241 = 241, - Reserved242 = 242, - Reserved243 = 243, - Reserved244 = 244, - Reserved245 = 245, - Reserved246 = 246, - Reserved247 = 247, - Reserved248 = 248, - Reserved249 = 249, - Reserved250 = 250, - Reserved251 = 251, - Reserved252 = 252, - Reserved253 = 253, - Reserved254 = 254, - Reserved255 = 255, - } - impl KvErrorE { - #[inline(always)] - pub fn success(&self) -> bool { - *self == Self::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> bool { - *self == Self::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> bool { - *self == Self::KvWriteFail - } - } - impl TryFrom for KvErrorE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 0x100 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: KvErrorE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct CtrlSelector(); - impl CtrlSelector { - #[inline(always)] - pub fn none(&self) -> super::Ctrl { - super::Ctrl::None - } - #[inline(always)] - pub fn keygen(&self) -> super::Ctrl { - super::Ctrl::Keygen - } - #[inline(always)] - pub fn signing(&self) -> super::Ctrl { - super::Ctrl::Signing - } - #[inline(always)] - pub fn verifying(&self) -> super::Ctrl { - super::Ctrl::Verifying - } - } - pub struct KvErrorESelector(); - impl KvErrorESelector { - #[inline(always)] - pub fn success(&self) -> super::KvErrorE { - super::KvErrorE::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvWriteFail - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Name = ureg::ReadOnlyReg32; - pub type Version = ureg::ReadOnlyReg32; - pub type Ctrl = ureg::WriteOnlyReg32<0, crate::ecc::regs::CtrlWriteVal>; - pub type Status = ureg::ReadOnlyReg32; - pub type Seed = ureg::WriteOnlyReg32<0, u32>; - pub type Msg = ureg::WriteOnlyReg32<0, u32>; - pub type PrivkeyOut = ureg::ReadOnlyReg32; - pub type PubkeyX = ureg::ReadWriteReg32<0, u32, u32>; - pub type PubkeyY = ureg::ReadWriteReg32<0, u32, u32>; - pub type SignR = ureg::ReadWriteReg32<0, u32, u32>; - pub type SignS = ureg::ReadWriteReg32<0, u32, u32>; - pub type VerifyR = ureg::ReadOnlyReg32; - pub type Iv = ureg::WriteOnlyReg32<0, u32>; - pub type Nonce = ureg::WriteOnlyReg32<0, u32>; - pub type PrivkeyIn = ureg::WriteOnlyReg32<0, u32>; - pub type KvRdPkeyCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvReadCtrlRegReadVal, - crate::regs::KvReadCtrlRegWriteVal, - >; - pub type KvRdPkeyStatus = ureg::ReadOnlyReg32; - pub type KvRdSeedCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvReadCtrlRegReadVal, - crate::regs::KvReadCtrlRegWriteVal, - >; - pub type KvRdSeedStatus = ureg::ReadOnlyReg32; - pub type KvWrPkeyCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvWriteCtrlRegReadVal, - crate::regs::KvWriteCtrlRegWriteVal, - >; - pub type KvWrPkeyStatus = ureg::ReadOnlyReg32; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::ecc::regs::ErrorIntrEnTReadVal, - crate::ecc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::ecc::regs::NotifIntrEnTReadVal, - crate::ecc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::ecc::regs::ErrorIntrTReadVal, - crate::ecc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::ecc::regs::NotifIntrTReadVal, - crate::ecc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::ecc::regs::ErrorIntrTrigTReadVal, - crate::ecc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::ecc::regs::NotifIntrTrigTReadVal, - crate::ecc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfErrorInternalIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdDoneIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorInternalIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdDoneIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/el2_pic_ctrl.rs b/hw/1.0/registers/src/el2_pic_ctrl.rs deleted file mode 100644 index c1c3bb3309..0000000000 --- a/hw/1.0/registers/src/el2_pic_ctrl.rs +++ /dev/null @@ -1,438 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct El2PicCtrl { - _priv: (), -} -impl El2PicCtrl { - pub const PTR: *mut u32 = 0x60000000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// There are 255 priority level registers, one for each external - /// interrupt source. Implementing individual priority level - /// registers allows a debugger to autonomously discover how many - /// priority level bits are supported for this interrupt source. - /// Firmware must initialize the priority level for each used - /// interrupt source. Firmware may also read the priority level. - /// - /// Read value: [`el2_pic_ctrl::regs::MeiplReadVal`]; Write value: [`el2_pic_ctrl::regs::MeiplWriteVal`] - #[inline(always)] - pub fn meipl( - &self, - ) -> ureg::Array<256, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Eight external interrupt pending registers are needed to - /// report the current status of up to 255 independent external - /// interrupt sources. Each bit of these registers corresponds - /// to an interrupt pending indication of a single external - /// interrupt source. These registers only provide the status - /// of pending interrupts and cannot be written. - /// - /// Read value: [`el2_pic_ctrl::regs::MeipReadVal`]; Write value: [`el2_pic_ctrl::regs::MeipWriteVal`] - #[inline(always)] - pub fn meip(&self) -> ureg::Array<256, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x1000 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Each of the up to 255 independently controlled external - /// interrupt sources has a dedicated interrupt enable register. - /// Separate registers per interrupt source were chosen for - /// ease-of-use and compatibility with existing controllers. - /// - /// Read value: [`el2_pic_ctrl::regs::MeieReadVal`]; Write value: [`el2_pic_ctrl::regs::MeieWriteVal`] - #[inline(always)] - pub fn meie(&self) -> ureg::Array<256, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x2000 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// The PIC configuration register is used to select the operational - /// parameters of the PIC. - /// - /// Read value: [`el2_pic_ctrl::regs::MpiccfgReadVal`]; Write value: [`el2_pic_ctrl::regs::MpiccfgWriteVal`] - #[inline(always)] - pub fn mpiccfg(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x3000 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Each configurable gateway has a dedicated configuration register - /// to control the interrupt type (i.e., edge- vs. level-triggered) - /// as well as the interrupt signal polarity (i.e., low-to-high vs. - /// high-to-low transition for edge-triggered interrupts, active-high - /// vs. -low for level-triggered interrupts). - /// - /// Read value: [`el2_pic_ctrl::regs::MeigwctrlReadVal`]; Write value: [`el2_pic_ctrl::regs::MeigwctrlWriteVal`] - #[inline(always)] - pub fn meigwctrl( - &self, - ) -> ureg::Array<256, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x4000 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Each configurable gateway has a dedicated clear register - /// to reset its interrupt pending (IP) bit. For edge-triggered - /// interrupts, firmware must clear the gateway’s IP bit while - /// servicing the external interrupt of source ID S by writing to - /// the meigwclrS register. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn meigwclr( - &self, - ) -> ureg::Array<256, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x5000 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct MeieReadVal(u32); - impl MeieReadVal { - /// External interrupt enable - #[inline(always)] - pub fn inten(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MeieWriteVal { - MeieWriteVal(self.0) - } - } - impl From for MeieReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeieReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeieWriteVal(u32); - impl MeieWriteVal { - /// External interrupt enable - #[inline(always)] - pub fn inten(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for MeieWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeieWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeigwctrlReadVal(u32); - impl MeigwctrlReadVal { - /// External interrupt polarity - /// 0b0: Active-high interrupt - /// 0b1: Active-low interrupt - #[inline(always)] - pub fn polarity(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// External interrupt type - /// 0b0: Level-triggered interrupt - /// 0b1: Edge-triggered interrupt - #[inline(always)] - pub fn inttype(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MeigwctrlWriteVal { - MeigwctrlWriteVal(self.0) - } - } - impl From for MeigwctrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeigwctrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeigwctrlWriteVal(u32); - impl MeigwctrlWriteVal { - /// External interrupt polarity - /// 0b0: Active-high interrupt - /// 0b1: Active-low interrupt - #[inline(always)] - pub fn polarity(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// External interrupt type - /// 0b0: Level-triggered interrupt - /// 0b1: Edge-triggered interrupt - #[inline(always)] - pub fn inttype(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for MeigwctrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeigwctrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeipReadVal(u32); - impl MeipReadVal { - /// External interrupt pending - #[inline(always)] - pub fn intpend(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for MeipReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeipReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeiplReadVal(u32); - impl MeiplReadVal { - /// External interrupt priority level - #[inline(always)] - pub fn priority(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MeiplWriteVal { - MeiplWriteVal(self.0) - } - } - impl From for MeiplReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeiplReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeiplWriteVal(u32); - impl MeiplWriteVal { - /// External interrupt priority level - #[inline(always)] - pub fn priority(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - } - impl From for MeiplWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeiplWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MpiccfgReadVal(u32); - impl MpiccfgReadVal { - /// Interrupt priority order - /// 0b0: RISC-V standard compliant priority order (0=lowest to 15=highest) - /// 0b1: Reverse priority order (15=lowest to 0=highest) - #[inline(always)] - pub fn priord(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MpiccfgWriteVal { - MpiccfgWriteVal(self.0) - } - } - impl From for MpiccfgReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MpiccfgReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MpiccfgWriteVal(u32); - impl MpiccfgWriteVal { - /// Interrupt priority order - /// 0b0: RISC-V standard compliant priority order (0=lowest to 15=highest) - /// 0b1: Reverse priority order (15=lowest to 0=highest) - #[inline(always)] - pub fn priord(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for MpiccfgWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MpiccfgWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Meipl = ureg::ReadWriteReg32< - 0, - crate::el2_pic_ctrl::regs::MeiplReadVal, - crate::el2_pic_ctrl::regs::MeiplWriteVal, - >; - pub type Meip = ureg::ReadOnlyReg32; - pub type Meie = ureg::ReadWriteReg32< - 0, - crate::el2_pic_ctrl::regs::MeieReadVal, - crate::el2_pic_ctrl::regs::MeieWriteVal, - >; - pub type Mpiccfg = ureg::ReadWriteReg32< - 0, - crate::el2_pic_ctrl::regs::MpiccfgReadVal, - crate::el2_pic_ctrl::regs::MpiccfgWriteVal, - >; - pub type Meigwctrl = ureg::ReadWriteReg32< - 0, - crate::el2_pic_ctrl::regs::MeigwctrlReadVal, - crate::el2_pic_ctrl::regs::MeigwctrlWriteVal, - >; - pub type Meigwclr = ureg::ReadWriteReg32<0, u32, u32>; -} diff --git a/hw/1.0/registers/src/entropy_src.rs b/hw/1.0/registers/src/entropy_src.rs deleted file mode 100644 index 577f9dd686..0000000000 --- a/hw/1.0/registers/src/entropy_src.rs +++ /dev/null @@ -1,3527 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct EntropySrcReg { - _priv: (), -} -impl EntropySrcReg { - pub const PTR: *mut u32 = 0x20003000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Read value: [`entropy_src::regs::InterruptStateReadVal`]; Write value: [`entropy_src::regs::InterruptStateWriteVal`] - #[inline(always)] - pub fn interrupt_state( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::InterruptEnableReadVal`]; Write value: [`entropy_src::regs::InterruptEnableWriteVal`] - #[inline(always)] - pub fn interrupt_enable( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::InterruptTestReadVal`]; Write value: [`entropy_src::regs::InterruptTestWriteVal`] - #[inline(always)] - pub fn interrupt_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AlertTestReadVal`]; Write value: [`entropy_src::regs::AlertTestWriteVal`] - #[inline(always)] - pub fn alert_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::MeRegwenReadVal`]; Write value: [`entropy_src::regs::MeRegwenWriteVal`] - #[inline(always)] - pub fn me_regwen(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::SwRegupdReadVal`]; Write value: [`entropy_src::regs::SwRegupdWriteVal`] - #[inline(always)] - pub fn sw_regupd(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RegwenReadVal`]; Write value: [`entropy_src::regs::RegwenWriteVal`] - #[inline(always)] - pub fn regwen(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RevReadVal`]; Write value: [`entropy_src::regs::RevWriteVal`] - #[inline(always)] - pub fn rev(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ModuleEnableReadVal`]; Write value: [`entropy_src::regs::ModuleEnableWriteVal`] - #[inline(always)] - pub fn module_enable(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ConfReadVal`]; Write value: [`entropy_src::regs::ConfWriteVal`] - #[inline(always)] - pub fn conf(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x24 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::EntropyControlReadVal`]; Write value: [`entropy_src::regs::EntropyControlWriteVal`] - #[inline(always)] - pub fn entropy_control( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x28 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn entropy_data(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x2c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::HealthTestWindowsReadVal`]; Write value: [`entropy_src::regs::HealthTestWindowsWriteVal`] - #[inline(always)] - pub fn health_test_windows( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x30 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RepcntThresholdsReadVal`]; Write value: [`entropy_src::regs::RepcntThresholdsWriteVal`] - #[inline(always)] - pub fn repcnt_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x34 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RepcntsThresholdsReadVal`]; Write value: [`entropy_src::regs::RepcntsThresholdsWriteVal`] - #[inline(always)] - pub fn repcnts_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x38 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AdaptpHiThresholdsReadVal`]; Write value: [`entropy_src::regs::AdaptpHiThresholdsWriteVal`] - #[inline(always)] - pub fn adaptp_hi_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x3c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AdaptpLoThresholdsReadVal`]; Write value: [`entropy_src::regs::AdaptpLoThresholdsWriteVal`] - #[inline(always)] - pub fn adaptp_lo_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x40 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::BucketThresholdsReadVal`]; Write value: [`entropy_src::regs::BucketThresholdsWriteVal`] - #[inline(always)] - pub fn bucket_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x44 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::MarkovHiThresholdsReadVal`]; Write value: [`entropy_src::regs::MarkovHiThresholdsWriteVal`] - #[inline(always)] - pub fn markov_hi_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x48 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::MarkovLoThresholdsReadVal`]; Write value: [`entropy_src::regs::MarkovLoThresholdsWriteVal`] - #[inline(always)] - pub fn markov_lo_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x4c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ExthtHiThresholdsReadVal`]; Write value: [`entropy_src::regs::ExthtHiThresholdsWriteVal`] - #[inline(always)] - pub fn extht_hi_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x50 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ExthtLoThresholdsReadVal`]; Write value: [`entropy_src::regs::ExthtLoThresholdsWriteVal`] - #[inline(always)] - pub fn extht_lo_thresholds( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x54 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RepcntHiWatermarksReadVal`]; Write value: [`entropy_src::regs::RepcntHiWatermarksWriteVal`] - #[inline(always)] - pub fn repcnt_hi_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x58 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RepcntsHiWatermarksReadVal`]; Write value: [`entropy_src::regs::RepcntsHiWatermarksWriteVal`] - #[inline(always)] - pub fn repcnts_hi_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x5c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AdaptpHiWatermarksReadVal`]; Write value: [`entropy_src::regs::AdaptpHiWatermarksWriteVal`] - #[inline(always)] - pub fn adaptp_hi_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x60 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AdaptpLoWatermarksReadVal`]; Write value: [`entropy_src::regs::AdaptpLoWatermarksWriteVal`] - #[inline(always)] - pub fn adaptp_lo_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x64 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ExthtHiWatermarksReadVal`]; Write value: [`entropy_src::regs::ExthtHiWatermarksWriteVal`] - #[inline(always)] - pub fn extht_hi_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x68 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ExthtLoWatermarksReadVal`]; Write value: [`entropy_src::regs::ExthtLoWatermarksWriteVal`] - #[inline(always)] - pub fn extht_lo_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x6c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::BucketHiWatermarksReadVal`]; Write value: [`entropy_src::regs::BucketHiWatermarksWriteVal`] - #[inline(always)] - pub fn bucket_hi_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x70 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::MarkovHiWatermarksReadVal`]; Write value: [`entropy_src::regs::MarkovHiWatermarksWriteVal`] - #[inline(always)] - pub fn markov_hi_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x74 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::MarkovLoWatermarksReadVal`]; Write value: [`entropy_src::regs::MarkovLoWatermarksWriteVal`] - #[inline(always)] - pub fn markov_lo_watermarks( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x78 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn repcnt_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x7c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn repcnts_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x80 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn adaptp_hi_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x84 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn adaptp_lo_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x88 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn bucket_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x8c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn markov_hi_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x90 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn markov_lo_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x94 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn extht_hi_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x98 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn extht_lo_total_fails( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x9c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AlertThresholdReadVal`]; Write value: [`entropy_src::regs::AlertThresholdWriteVal`] - #[inline(always)] - pub fn alert_threshold( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xa0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AlertSummaryFailCountsReadVal`]; Write value: [`entropy_src::regs::AlertSummaryFailCountsWriteVal`] - #[inline(always)] - pub fn alert_summary_fail_counts( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xa4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::AlertFailCountsReadVal`]; Write value: [`entropy_src::regs::AlertFailCountsWriteVal`] - #[inline(always)] - pub fn alert_fail_counts( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xa8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ExthtFailCountsReadVal`]; Write value: [`entropy_src::regs::ExthtFailCountsWriteVal`] - #[inline(always)] - pub fn extht_fail_counts( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xac / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::FwOvControlReadVal`]; Write value: [`entropy_src::regs::FwOvControlWriteVal`] - #[inline(always)] - pub fn fw_ov_control(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xb0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::FwOvSha3StartReadVal`]; Write value: [`entropy_src::regs::FwOvSha3StartWriteVal`] - #[inline(always)] - pub fn fw_ov_sha3_start( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xb4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::FwOvWrFifoFullReadVal`]; Write value: [`entropy_src::regs::FwOvWrFifoFullWriteVal`] - #[inline(always)] - pub fn fw_ov_wr_fifo_full( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xb8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::FwOvRdFifoOverflowReadVal`]; Write value: [`entropy_src::regs::FwOvRdFifoOverflowWriteVal`] - #[inline(always)] - pub fn fw_ov_rd_fifo_overflow( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xbc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fw_ov_rd_data(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fw_ov_wr_data(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ObserveFifoThreshReadVal`]; Write value: [`entropy_src::regs::ObserveFifoThreshWriteVal`] - #[inline(always)] - pub fn observe_fifo_thresh( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ObserveFifoDepthReadVal`]; Write value: [`entropy_src::regs::ObserveFifoDepthWriteVal`] - #[inline(always)] - pub fn observe_fifo_depth( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xcc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::DebugStatusReadVal`]; Write value: [`entropy_src::regs::DebugStatusWriteVal`] - #[inline(always)] - pub fn debug_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xd0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::RecovAlertStsReadVal`]; Write value: [`entropy_src::regs::RecovAlertStsWriteVal`] - #[inline(always)] - pub fn recov_alert_sts(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xd4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ErrCodeReadVal`]; Write value: [`entropy_src::regs::ErrCodeWriteVal`] - #[inline(always)] - pub fn err_code(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xd8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::ErrCodeTestReadVal`]; Write value: [`entropy_src::regs::ErrCodeTestWriteVal`] - #[inline(always)] - pub fn err_code_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xdc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`entropy_src::regs::MainSmStateReadVal`]; Write value: [`entropy_src::regs::MainSmStateWriteVal`] - #[inline(always)] - pub fn main_sm_state(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xe0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct AdaptpHiThresholdsReadVal(u32); - impl AdaptpHiThresholdsReadVal { - /// This is the threshold size for the adaptive proportion health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the adaptive proportion health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> AdaptpHiThresholdsWriteVal { - AdaptpHiThresholdsWriteVal(self.0) - } - } - impl From for AdaptpHiThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AdaptpHiThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AdaptpHiThresholdsWriteVal(u32); - impl AdaptpHiThresholdsWriteVal { - /// This is the threshold size for the adaptive proportion health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the adaptive proportion health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for AdaptpHiThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AdaptpHiThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AdaptpHiWatermarksReadVal(u32); - impl AdaptpHiWatermarksReadVal { - /// High watermark value of the adaptive proportion test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// High watermark value of the adaptive proportion test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for AdaptpHiWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AdaptpHiWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AdaptpLoThresholdsReadVal(u32); - impl AdaptpLoThresholdsReadVal { - /// This is the threshold size for the adaptive proportion health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the adaptive proportion health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> AdaptpLoThresholdsWriteVal { - AdaptpLoThresholdsWriteVal(self.0) - } - } - impl From for AdaptpLoThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AdaptpLoThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AdaptpLoThresholdsWriteVal(u32); - impl AdaptpLoThresholdsWriteVal { - /// This is the threshold size for the adaptive proportion health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the adaptive proportion health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for AdaptpLoThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AdaptpLoThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AdaptpLoWatermarksReadVal(u32); - impl AdaptpLoWatermarksReadVal { - /// Low watermark value of the adaptive proportion test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// Low watermark value of the adaptive proportion test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for AdaptpLoWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AdaptpLoWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AlertFailCountsReadVal(u32); - impl AlertFailCountsReadVal { - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn repcnt_fail_count(&self) -> u32 { - (self.0 >> 4) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn adaptp_hi_fail_count(&self) -> u32 { - (self.0 >> 8) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn adaptp_lo_fail_count(&self) -> u32 { - (self.0 >> 12) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn bucket_fail_count(&self) -> u32 { - (self.0 >> 16) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn markov_hi_fail_count(&self) -> u32 { - (self.0 >> 20) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn markov_lo_fail_count(&self) -> u32 { - (self.0 >> 24) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn repcnts_fail_count(&self) -> u32 { - (self.0 >> 28) & 0xf - } - } - impl From for AlertFailCountsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertFailCountsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AlertSummaryFailCountsReadVal(u32); - impl AlertSummaryFailCountsReadVal { - /// This field will hold a running count of - /// the total alert count, which is a sum of all of the other - /// counters in the !!ALERT_FAIL_COUNTS register. - /// It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn any_fail_count(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - } - impl From for AlertSummaryFailCountsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertSummaryFailCountsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AlertTestWriteVal(u32); - impl AlertTestWriteVal { - /// Write 1 to trigger one alert event of this kind. - #[inline(always)] - pub fn recov_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write 1 to trigger one alert event of this kind. - #[inline(always)] - pub fn fatal_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for AlertTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AlertThresholdReadVal(u32); - impl AlertThresholdReadVal { - /// This is the threshold size that will signal an alert when - /// value is reached. A value of zero will disable alerts. - /// The default value is 2. - #[inline(always)] - pub fn alert_threshold(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This should be set to the value above, but inverted. - #[inline(always)] - pub fn alert_threshold_inv(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> AlertThresholdWriteVal { - AlertThresholdWriteVal(self.0) - } - } - impl From for AlertThresholdReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertThresholdReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct AlertThresholdWriteVal(u32); - impl AlertThresholdWriteVal { - /// This is the threshold size that will signal an alert when - /// value is reached. A value of zero will disable alerts. - /// The default value is 2. - #[inline(always)] - pub fn alert_threshold(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This should be set to the value above, but inverted. - #[inline(always)] - pub fn alert_threshold_inv(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for AlertThresholdWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertThresholdWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct BucketHiWatermarksReadVal(u32); - impl BucketHiWatermarksReadVal { - /// High watermark value of the bucket test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// High watermark value of the bucket test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for BucketHiWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: BucketHiWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct BucketThresholdsReadVal(u32); - impl BucketThresholdsReadVal { - /// This is the threshold size for the bucket health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the bucket health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> BucketThresholdsWriteVal { - BucketThresholdsWriteVal(self.0) - } - } - impl From for BucketThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: BucketThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct BucketThresholdsWriteVal(u32); - impl BucketThresholdsWriteVal { - /// This is the threshold size for the bucket health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the bucket health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for BucketThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: BucketThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ConfReadVal(u32); - impl ConfReadVal { - /// Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be - /// generated. - #[inline(always)] - pub fn fips_enable(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Setting this field to kMultiBitBool4True will enable reading entropy values from the - /// ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read - /// input vector is set to the enable encoding. - #[inline(always)] - pub fn entropy_data_reg_enable(&self) -> u32 { - (self.0 >> 4) & 0xf - } - /// This field controls the scope (either by-line or by-sum) of the health checks. - /// If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all - /// RNG input lines into a single score, and thresholds will be applied to the sum all - /// the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored - /// individually. A statistical deviation in any one input line, be it due to - /// coincidence or failure, will force rejection of the sample, and count toward the - /// total alert count. - #[inline(always)] - pub fn threshold_scope(&self) -> u32 { - (self.0 >> 12) & 0xf - } - /// Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only - /// one bit is sampled. - #[inline(always)] - pub fn rng_bit_enable(&self) -> u32 { - (self.0 >> 20) & 0xf - } - /// When the above bit iset, this field selects which bit from the RNG bus will - /// be processed when in single RNG bit mode. - /// This two bit field selects the RNG bit stream: - /// 0b00: RNG bit 0 - /// 0b01: RNG bit 1 - /// 0b10: RNG bit 2 - /// 0b11: RNG bit 3 - #[inline(always)] - pub fn rng_bit_sel(&self) -> u32 { - (self.0 >> 24) & 3 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ConfWriteVal { - ConfWriteVal(self.0) - } - } - impl From for ConfReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ConfReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ConfWriteVal(u32); - impl ConfWriteVal { - /// Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be - /// generated. - #[inline(always)] - pub fn fips_enable(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - /// Setting this field to kMultiBitBool4True will enable reading entropy values from the - /// ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read - /// input vector is set to the enable encoding. - #[inline(always)] - pub fn entropy_data_reg_enable(self, val: u32) -> Self { - Self((self.0 & !(0xf << 4)) | ((val & 0xf) << 4)) - } - /// This field controls the scope (either by-line or by-sum) of the health checks. - /// If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all - /// RNG input lines into a single score, and thresholds will be applied to the sum all - /// the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored - /// individually. A statistical deviation in any one input line, be it due to - /// coincidence or failure, will force rejection of the sample, and count toward the - /// total alert count. - #[inline(always)] - pub fn threshold_scope(self, val: u32) -> Self { - Self((self.0 & !(0xf << 12)) | ((val & 0xf) << 12)) - } - /// Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only - /// one bit is sampled. - #[inline(always)] - pub fn rng_bit_enable(self, val: u32) -> Self { - Self((self.0 & !(0xf << 20)) | ((val & 0xf) << 20)) - } - /// When the above bit iset, this field selects which bit from the RNG bus will - /// be processed when in single RNG bit mode. - /// This two bit field selects the RNG bit stream: - /// 0b00: RNG bit 0 - /// 0b01: RNG bit 1 - /// 0b10: RNG bit 2 - /// 0b11: RNG bit 3 - #[inline(always)] - pub fn rng_bit_sel(self, val: u32) -> Self { - Self((self.0 & !(3 << 24)) | ((val & 3) << 24)) - } - } - impl From for ConfWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ConfWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct DebugStatusReadVal(u32); - impl DebugStatusReadVal { - /// This is the depth of the entropy source FIFO. - #[inline(always)] - pub fn entropy_fifo_depth(&self) -> u32 { - (self.0 >> 0) & 7 - } - /// This is the SHA3 finite state machine current state. - #[inline(always)] - pub fn sha3_fsm(&self) -> u32 { - (self.0 >> 3) & 7 - } - /// This is the SHA3 block processed signal current state. - #[inline(always)] - pub fn sha3_block_pr(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// This is the SHA3 squeezing signal current state. - #[inline(always)] - pub fn sha3_squeezing(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// This is the SHA3 absorbed signal current state. - #[inline(always)] - pub fn sha3_absorbed(&self) -> bool { - ((self.0 >> 8) & 1) != 0 - } - /// This is a logic-or of all of the SHA3 error signals. - #[inline(always)] - pub fn sha3_err(&self) -> bool { - ((self.0 >> 9) & 1) != 0 - } - /// The entropy_src main state machine is in the idle state. - #[inline(always)] - pub fn main_sm_idle(&self) -> bool { - ((self.0 >> 16) & 1) != 0 - } - /// The entropy_src main state machine is in the boot phase done state. - #[inline(always)] - pub fn main_sm_boot_done(&self) -> bool { - ((self.0 >> 17) & 1) != 0 - } - } - impl From for DebugStatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: DebugStatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct EntropyControlReadVal(u32); - impl EntropyControlReadVal { - /// Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA - /// register to be read by firmware. When this field is kMultiBitBool4False, the generated - /// entropy will be forwarded out of this module to the hardware interface. - #[inline(always)] - pub fn es_route(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy - /// data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy - /// will be brought the ENTROPY_DATA register, after being conditioned. - #[inline(always)] - pub fn es_type(&self) -> u32 { - (self.0 >> 4) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> EntropyControlWriteVal { - EntropyControlWriteVal(self.0) - } - } - impl From for EntropyControlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: EntropyControlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct EntropyControlWriteVal(u32); - impl EntropyControlWriteVal { - /// Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA - /// register to be read by firmware. When this field is kMultiBitBool4False, the generated - /// entropy will be forwarded out of this module to the hardware interface. - #[inline(always)] - pub fn es_route(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - /// Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy - /// data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy - /// will be brought the ENTROPY_DATA register, after being conditioned. - #[inline(always)] - pub fn es_type(self, val: u32) -> Self { - Self((self.0 & !(0xf << 4)) | ((val & 0xf) << 4)) - } - } - impl From for EntropyControlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: EntropyControlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrCodeReadVal(u32); - impl ErrCodeReadVal { - /// This bit will be set to one when an error has been detected for the - /// esrng FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_esrng_err(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// observe FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_observe_err(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// This bit will be set to one when an error has been detected for the - /// esfinal FIFO. The type of error is reflected in the type status - /// bits (bits 28 through 30 of this register). - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sfifo_esfinal_err(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// ES ack stage state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn es_ack_sm_err(&self) -> bool { - ((self.0 >> 20) & 1) != 0 - } - /// This bit will be set to one when an illegal state has been detected for the - /// ES main stage state machine. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn es_main_sm_err(&self) -> bool { - ((self.0 >> 21) & 1) != 0 - } - /// This bit will be set to one when a hardened counter has detected an error - /// condition. This error will signal a fatal alert, and also - /// an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn es_cntr_err(&self) -> bool { - ((self.0 >> 22) & 1) != 0 - } - /// This bit will be set to one when a SHA3 state error has been detected. - /// This error will signal a fatal alert, and also an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sha3_state_err(&self) -> bool { - ((self.0 >> 23) & 1) != 0 - } - /// This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being - /// active has been detected. - /// This error will signal a fatal alert, and also an interrupt if enabled. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn sha3_rst_storage_err(&self) -> bool { - ((self.0 >> 24) & 1) != 0 - } - /// This bit will be set to one when any of the source bits (bits 0 through 1 of this - /// this register) are asserted as a result of an error pulse generated from - /// any full FIFO that has been recieved a write pulse. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn fifo_write_err(&self) -> bool { - ((self.0 >> 28) & 1) != 0 - } - /// This bit will be set to one when any of the source bits (bits 0 through 1 of this - /// this register) are asserted as a result of an error pulse generated from - /// any empty FIFO that has recieved a read pulse. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn fifo_read_err(&self) -> bool { - ((self.0 >> 29) & 1) != 0 - } - /// This bit will be set to one when any of the source bits (bits 0 through 1 of this - /// this register) are asserted as a result of an error pulse generated from - /// any FIFO where both the empty and full status bits are set. - /// This bit will stay set until the next reset. - #[inline(always)] - pub fn fifo_state_err(&self) -> bool { - ((self.0 >> 30) & 1) != 0 - } - } - impl From for ErrCodeReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrCodeReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrCodeTestReadVal(u32); - impl ErrCodeTestReadVal { - /// Setting this field will set the bit number for which an error - /// will be forced in the hardware. This bit number is that same one - /// found in the !!ERR_CODE register. The action of writing this - /// register will force an error pulse. The sole purpose of this - /// register is to test that any error properly propagates to either - /// an interrupt or an alert. - #[inline(always)] - pub fn err_code_test(&self) -> u32 { - (self.0 >> 0) & 0x1f - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrCodeTestWriteVal { - ErrCodeTestWriteVal(self.0) - } - } - impl From for ErrCodeTestReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrCodeTestReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrCodeTestWriteVal(u32); - impl ErrCodeTestWriteVal { - /// Setting this field will set the bit number for which an error - /// will be forced in the hardware. This bit number is that same one - /// found in the !!ERR_CODE register. The action of writing this - /// register will force an error pulse. The sole purpose of this - /// register is to test that any error properly propagates to either - /// an interrupt or an alert. - #[inline(always)] - pub fn err_code_test(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 0)) | ((val & 0x1f) << 0)) - } - } - impl From for ErrCodeTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrCodeTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtFailCountsReadVal(u32); - impl ExthtFailCountsReadVal { - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn extht_hi_fail_count(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// This field will hold a running count of test failures that - /// contribute to the total alert count. It will be reset after every - /// passing test sequence. If an alert is signaled, this value - /// will persist until it is cleared. - #[inline(always)] - pub fn extht_lo_fail_count(&self) -> u32 { - (self.0 >> 4) & 0xf - } - } - impl From for ExthtFailCountsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtFailCountsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtHiThresholdsReadVal(u32); - impl ExthtHiThresholdsReadVal { - /// This is the threshold size for the external health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the external health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ExthtHiThresholdsWriteVal { - ExthtHiThresholdsWriteVal(self.0) - } - } - impl From for ExthtHiThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtHiThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtHiThresholdsWriteVal(u32); - impl ExthtHiThresholdsWriteVal { - /// This is the threshold size for the external health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the external health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for ExthtHiThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtHiThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtHiWatermarksReadVal(u32); - impl ExthtHiWatermarksReadVal { - /// High watermark value of the external health test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// High watermark value of the external health test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for ExthtHiWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtHiWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtLoThresholdsReadVal(u32); - impl ExthtLoThresholdsReadVal { - /// This is the threshold size for the external health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the external health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ExthtLoThresholdsWriteVal { - ExthtLoThresholdsWriteVal(self.0) - } - } - impl From for ExthtLoThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtLoThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtLoThresholdsWriteVal(u32); - impl ExthtLoThresholdsWriteVal { - /// This is the threshold size for the external health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the external health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for ExthtLoThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtLoThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExthtLoWatermarksReadVal(u32); - impl ExthtLoWatermarksReadVal { - /// Low watermark value of the external health test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// Low watermark value of the external health test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for ExthtLoWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExthtLoWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvControlReadVal(u32); - impl FwOvControlReadVal { - /// Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. - /// In this mode, firmware can monitor the post-health test entropy by reading - /// the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over - /// input vector is set to the enable encoding. - #[inline(always)] - pub fn fw_ov_mode(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner - /// packer FIFO. Firmware can directly write into the packer FIFO, enabling - /// the ability to insert entropy bits back into the hardware flow. Firmware - /// can read data from the health check packer FIFO, then do optional health - /// checks or optional conditioning, then insert the results back into the flow. - /// Also, the !!FW_OV_CONTROL.FW_OV_MODE bit must be set. - #[inline(always)] - pub fn fw_ov_entropy_insert(&self) -> u32 { - (self.0 >> 4) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FwOvControlWriteVal { - FwOvControlWriteVal(self.0) - } - } - impl From for FwOvControlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvControlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvControlWriteVal(u32); - impl FwOvControlWriteVal { - /// Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. - /// In this mode, firmware can monitor the post-health test entropy by reading - /// the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over - /// input vector is set to the enable encoding. - #[inline(always)] - pub fn fw_ov_mode(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - /// Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner - /// packer FIFO. Firmware can directly write into the packer FIFO, enabling - /// the ability to insert entropy bits back into the hardware flow. Firmware - /// can read data from the health check packer FIFO, then do optional health - /// checks or optional conditioning, then insert the results back into the flow. - /// Also, the !!FW_OV_CONTROL.FW_OV_MODE bit must be set. - #[inline(always)] - pub fn fw_ov_entropy_insert(self, val: u32) -> Self { - Self((self.0 & !(0xf << 4)) | ((val & 0xf) << 4)) - } - } - impl From for FwOvControlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvControlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvRdFifoOverflowReadVal(u32); - impl FwOvRdFifoOverflowReadVal { - /// This bit is set by hardware whenever RNG data is lost due to an overflow condition - /// in the Observe FIFO. The RNG data rate is slow enough that firmware should always - /// be able to keep up. This register meanwhile provides an additional check to confirm - /// that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. - /// If an overflow event occurs, this bit must be cleared by software. - #[inline(always)] - pub fn fw_ov_rd_fifo_overflow(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FwOvRdFifoOverflowWriteVal { - FwOvRdFifoOverflowWriteVal(self.0) - } - } - impl From for FwOvRdFifoOverflowReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvRdFifoOverflowReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvRdFifoOverflowWriteVal(u32); - impl FwOvRdFifoOverflowWriteVal { - /// This bit is set by hardware whenever RNG data is lost due to an overflow condition - /// in the Observe FIFO. The RNG data rate is slow enough that firmware should always - /// be able to keep up. This register meanwhile provides an additional check to confirm - /// that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. - /// If an overflow event occurs, this bit must be cleared by software. - #[inline(always)] - pub fn fw_ov_rd_fifo_overflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for FwOvRdFifoOverflowWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvRdFifoOverflowWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvSha3StartReadVal(u32); - impl FwOvSha3StartReadVal { - /// Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine - /// to start the SHA3 process and be ready to accept entropy data. This field should - /// be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, - /// this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish - /// processing and push the result into the ESFINAL FIFO. - /// - /// Note that clearing this bit to kMultiBitBool4False while there is still unprocessed - /// entropy in the !!FW_OV_WR_DATA will start the SHA3 engine before data can be added - /// to the input message, and will also signal a recoverable alert in - /// !!RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that - /// !!FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False. - #[inline(always)] - pub fn fw_ov_insert_start(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FwOvSha3StartWriteVal { - FwOvSha3StartWriteVal(self.0) - } - } - impl From for FwOvSha3StartReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvSha3StartReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvSha3StartWriteVal(u32); - impl FwOvSha3StartWriteVal { - /// Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine - /// to start the SHA3 process and be ready to accept entropy data. This field should - /// be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, - /// this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish - /// processing and push the result into the ESFINAL FIFO. - /// - /// Note that clearing this bit to kMultiBitBool4False while there is still unprocessed - /// entropy in the !!FW_OV_WR_DATA will start the SHA3 engine before data can be added - /// to the input message, and will also signal a recoverable alert in - /// !!RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that - /// !!FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False. - #[inline(always)] - pub fn fw_ov_insert_start(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - } - impl From for FwOvSha3StartWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvSha3StartWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FwOvWrFifoFullReadVal(u32); - impl FwOvWrFifoFullReadVal { - /// "When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. - /// If this bit is set, it is the equivalent to a FIFO full condition, and writes - /// to the FW_OV_WR_DATA register must be delayed until this bit is reset. - #[inline(always)] - pub fn fw_ov_wr_fifo_full(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for FwOvWrFifoFullReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FwOvWrFifoFullReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct HealthTestWindowsReadVal(u32); - impl HealthTestWindowsReadVal { - /// This is the window size for all health tests. This value is used in normal mode - /// when entropy is being tested in FIPS/CC compliance mode. - /// The default value is (2048 bits * 1 clock/4 bits); - #[inline(always)] - pub fn fips_window(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the window size for all health tests when running in bypass mode. This mode - /// is active after reset for the first and only test run, or when this mode is - /// programmed by firmware. - /// The default value is (384 bits * 1 clock/4 bits); - /// - /// Note that currently only a window size of 384 is supported and tested (this - /// corresponds to the register default value 0x60). Do not use any other values, - /// unless you know what you are doing. - #[inline(always)] - pub fn bypass_window(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> HealthTestWindowsWriteVal { - HealthTestWindowsWriteVal(self.0) - } - } - impl From for HealthTestWindowsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: HealthTestWindowsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct HealthTestWindowsWriteVal(u32); - impl HealthTestWindowsWriteVal { - /// This is the window size for all health tests. This value is used in normal mode - /// when entropy is being tested in FIPS/CC compliance mode. - /// The default value is (2048 bits * 1 clock/4 bits); - #[inline(always)] - pub fn fips_window(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the window size for all health tests when running in bypass mode. This mode - /// is active after reset for the first and only test run, or when this mode is - /// programmed by firmware. - /// The default value is (384 bits * 1 clock/4 bits); - /// - /// Note that currently only a window size of 384 is supported and tested (this - /// corresponds to the register default value 0x60). Do not use any other values, - /// unless you know what you are doing. - #[inline(always)] - pub fn bypass_window(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for HealthTestWindowsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: HealthTestWindowsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableReadVal(u32); - impl InterruptEnableReadVal { - /// Enable interrupt when es_entropy_valid is set. - #[inline(always)] - pub fn es_entropy_valid(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable interrupt when es_health_test_failed is set. - #[inline(always)] - pub fn es_health_test_failed(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable interrupt when es_observe_fifo_ready is set. - #[inline(always)] - pub fn es_observe_fifo_ready(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable interrupt when es_fatal_err is set. - #[inline(always)] - pub fn es_fatal_err(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptEnableWriteVal { - InterruptEnableWriteVal(self.0) - } - } - impl From for InterruptEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableWriteVal(u32); - impl InterruptEnableWriteVal { - /// Enable interrupt when es_entropy_valid is set. - #[inline(always)] - pub fn es_entropy_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable interrupt when es_health_test_failed is set. - #[inline(always)] - pub fn es_health_test_failed(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable interrupt when es_observe_fifo_ready is set. - #[inline(always)] - pub fn es_observe_fifo_ready(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable interrupt when es_fatal_err is set. - #[inline(always)] - pub fn es_fatal_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for InterruptEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateReadVal(u32); - impl InterruptStateReadVal { - /// Asserted when entropy source bits are available. - #[inline(always)] - pub fn es_entropy_valid(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Asserted when the alert count has been met. - #[inline(always)] - pub fn es_health_test_failed(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Asserted when the observe FIFO has filled to the threshold level. - #[inline(always)] - pub fn es_observe_fifo_ready(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Asserted when a FIFO error occurs, or if an illegal state machine state is reached. - #[inline(always)] - pub fn es_fatal_err(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptStateWriteVal { - InterruptStateWriteVal(self.0) - } - } - impl From for InterruptStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateWriteVal(u32); - impl InterruptStateWriteVal { - /// Asserted when entropy source bits are available. - #[inline(always)] - pub fn es_entropy_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Asserted when the alert count has been met. - #[inline(always)] - pub fn es_health_test_failed(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Asserted when the observe FIFO has filled to the threshold level. - #[inline(always)] - pub fn es_observe_fifo_ready(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Asserted when a FIFO error occurs, or if an illegal state machine state is reached. - #[inline(always)] - pub fn es_fatal_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for InterruptStateWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptTestWriteVal(u32); - impl InterruptTestWriteVal { - /// Write 1 to force es_entropy_valid to 1. - #[inline(always)] - pub fn es_entropy_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write 1 to force es_health_test_failed to 1. - #[inline(always)] - pub fn es_health_test_failed(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Write 1 to force es_observe_fifo_ready to 1. - #[inline(always)] - pub fn es_observe_fifo_ready(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Write 1 to force es_fatal_err to 1. - #[inline(always)] - pub fn es_fatal_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for InterruptTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MainSmStateReadVal(u32); - impl MainSmStateReadVal { - /// This is the state of the ENTROPY_SRC main state machine. - /// See the RTL file `entropy_src_main_sm` for the meaning of the values. - #[inline(always)] - pub fn main_sm_state(&self) -> u32 { - (self.0 >> 0) & 0x1ff - } - } - impl From for MainSmStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MainSmStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MarkovHiThresholdsReadVal(u32); - impl MarkovHiThresholdsReadVal { - /// This is the threshold size for the Markov health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the Markov health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MarkovHiThresholdsWriteVal { - MarkovHiThresholdsWriteVal(self.0) - } - } - impl From for MarkovHiThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MarkovHiThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MarkovHiThresholdsWriteVal(u32); - impl MarkovHiThresholdsWriteVal { - /// This is the threshold size for the Markov health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the Markov health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for MarkovHiThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MarkovHiThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MarkovHiWatermarksReadVal(u32); - impl MarkovHiWatermarksReadVal { - /// High watermark value of the Markov test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// High watermark value of the Markov test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for MarkovHiWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MarkovHiWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MarkovLoThresholdsReadVal(u32); - impl MarkovLoThresholdsReadVal { - /// This is the threshold size for the Markov health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the Markov health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MarkovLoThresholdsWriteVal { - MarkovLoThresholdsWriteVal(self.0) - } - } - impl From for MarkovLoThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MarkovLoThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MarkovLoThresholdsWriteVal(u32); - impl MarkovLoThresholdsWriteVal { - /// This is the threshold size for the Markov health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the Markov health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is greater than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for MarkovLoThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MarkovLoThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MarkovLoWatermarksReadVal(u32); - impl MarkovLoWatermarksReadVal { - /// Low watermark value of the Markov test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// Low watermark value of the Markov test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for MarkovLoWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MarkovLoWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeRegwenReadVal(u32); - impl MeRegwenReadVal { - /// When true, the !!MODULE_ENABLE register can be modified. - /// When false, it becomes read-only. - #[inline(always)] - pub fn me_regwen(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> MeRegwenWriteVal { - MeRegwenWriteVal(self.0) - } - } - impl From for MeRegwenReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeRegwenReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct MeRegwenWriteVal(u32); - impl MeRegwenWriteVal { - /// When true, the !!MODULE_ENABLE register can be modified. - /// When false, it becomes read-only. - #[inline(always)] - pub fn me_regwen(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for MeRegwenWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: MeRegwenWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ModuleEnableReadVal(u32); - impl ModuleEnableReadVal { - /// Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting - /// this field to kMultiBitBool4False will effectively reset the module. The modules of - /// the entropy complex may only be enabled and disabled in a specific order, see - /// Programmers Guide for details. - #[inline(always)] - pub fn module_enable(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ModuleEnableWriteVal { - ModuleEnableWriteVal(self.0) - } - } - impl From for ModuleEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ModuleEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ModuleEnableWriteVal(u32); - impl ModuleEnableWriteVal { - /// Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting - /// this field to kMultiBitBool4False will effectively reset the module. The modules of - /// the entropy complex may only be enabled and disabled in a specific order, see - /// Programmers Guide for details. - #[inline(always)] - pub fn module_enable(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - } - impl From for ModuleEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ModuleEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ObserveFifoDepthReadVal(u32); - impl ObserveFifoDepthReadVal { - /// This field will hold the current depth of the Observe FIFO. - #[inline(always)] - pub fn observe_fifo_depth(&self) -> u32 { - (self.0 >> 0) & 0x7f - } - } - impl From for ObserveFifoDepthReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ObserveFifoDepthReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ObserveFifoThreshReadVal(u32); - impl ObserveFifoThreshReadVal { - /// This field will set the threshold that the depth of the Observe FIFO - /// will be compared with when setting the interrupt status bit. - /// Note: a value of zero is reserved and not to be used. - #[inline(always)] - pub fn observe_fifo_thresh(&self) -> u32 { - (self.0 >> 0) & 0x7f - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ObserveFifoThreshWriteVal { - ObserveFifoThreshWriteVal(self.0) - } - } - impl From for ObserveFifoThreshReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ObserveFifoThreshReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ObserveFifoThreshWriteVal(u32); - impl ObserveFifoThreshWriteVal { - /// This field will set the threshold that the depth of the Observe FIFO - /// will be compared with when setting the interrupt status bit. - /// Note: a value of zero is reserved and not to be used. - #[inline(always)] - pub fn observe_fifo_thresh(self, val: u32) -> Self { - Self((self.0 & !(0x7f << 0)) | ((val & 0x7f) << 0)) - } - } - impl From for ObserveFifoThreshWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ObserveFifoThreshWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RecovAlertStsReadVal(u32); - impl RecovAlertStsReadVal { - /// This bit is set when the FIPS_ENABLE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fips_enable_field_alert(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// This bit is set when the ENTROPY_DATA_REG_ENABLE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn entropy_data_reg_en_field_alert(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// This bit is set when the MODULE_ENABLE field in the !!MODULE_ENABLE register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn module_enable_field_alert(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn threshold_scope_field_alert(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// This bit is set when the RNG_BIT_ENABLE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn rng_bit_enable_field_alert(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// This bit is set when the FW_OV_SHA3_START field in the !!FW_OV_SHA3_START register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fw_ov_sha3_start_field_alert(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// This bit is set when the FW_OV_MODE field in the !!FW_OV_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fw_ov_mode_field_alert(&self) -> bool { - ((self.0 >> 8) & 1) != 0 - } - /// This bit is set when the FW_OV_ENTROPY_INSERT field in the !!FW_OV_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fw_ov_entropy_insert_field_alert(&self) -> bool { - ((self.0 >> 9) & 1) != 0 - } - /// This bit is set when the ES_ROUTE field in the !!ENTROPY_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_route_field_alert(&self) -> bool { - ((self.0 >> 10) & 1) != 0 - } - /// This bit is set when the ES_TYPE field in the !!ENTROPY_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_type_field_alert(&self) -> bool { - ((self.0 >> 11) & 1) != 0 - } - /// This bit is set when the main state machine detects a threshhold failure state. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_main_sm_alert(&self) -> bool { - ((self.0 >> 12) & 1) != 0 - } - /// This bit is set when the interal entropy bus value is equal to the prior - /// valid value on the bus, indicating a possible attack. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_bus_cmp_alert(&self) -> bool { - ((self.0 >> 13) & 1) != 0 - } - /// This bit is set when the !!ALERT_THRESHOLD register is not configured properly. - /// The upper field must be the exact inverse of the lower field. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_thresh_cfg_alert(&self) -> bool { - ((self.0 >> 14) & 1) != 0 - } - /// This bit is set when the packer FIFO has been written but was full at the time, - /// and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. - /// This alert would normally be the result of not monitoring the !!FW_OV_WR_FIFO_FULL - /// register before each write to the !!FW_OV_WR_DATA register. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_fw_ov_wr_alert(&self) -> bool { - ((self.0 >> 15) & 1) != 0 - } - /// This bit is set when !!FW_OV_SHA3_START has been set to MuBi4 False, without - /// waiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO - /// will not be included in the SHA3 digest. (Rather it will be added to the - /// subsequent SHA3 digest.) To avoid this alert, monitor !!FW_OV_WR_FIFO_FULL before - /// clearing !!FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and - /// FW_OV_ENTROPY_INSERT are set to MuBi4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_fw_ov_disable_alert(&self) -> bool { - ((self.0 >> 16) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> RecovAlertStsWriteVal { - RecovAlertStsWriteVal(self.0) - } - } - impl From for RecovAlertStsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RecovAlertStsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RecovAlertStsWriteVal(u32); - impl RecovAlertStsWriteVal { - /// This bit is set when the FIPS_ENABLE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fips_enable_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// This bit is set when the ENTROPY_DATA_REG_ENABLE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn entropy_data_reg_en_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// This bit is set when the MODULE_ENABLE field in the !!MODULE_ENABLE register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn module_enable_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// This bit is set when the THRESHOLD_SCOPE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn threshold_scope_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// This bit is set when the RNG_BIT_ENABLE field in the !!CONF register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn rng_bit_enable_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// This bit is set when the FW_OV_SHA3_START field in the !!FW_OV_SHA3_START register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fw_ov_sha3_start_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - /// This bit is set when the FW_OV_MODE field in the !!FW_OV_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fw_ov_mode_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 8)) | (u32::from(val) << 8)) - } - /// This bit is set when the FW_OV_ENTROPY_INSERT field in the !!FW_OV_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn fw_ov_entropy_insert_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 9)) | (u32::from(val) << 9)) - } - /// This bit is set when the ES_ROUTE field in the !!ENTROPY_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_route_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 10)) | (u32::from(val) << 10)) - } - /// This bit is set when the ES_TYPE field in the !!ENTROPY_CONTROL register is set to - /// a value other than kMultiBitBool4False or kMultiBitBool4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_type_field_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 11)) | (u32::from(val) << 11)) - } - /// This bit is set when the main state machine detects a threshhold failure state. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_main_sm_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 12)) | (u32::from(val) << 12)) - } - /// This bit is set when the interal entropy bus value is equal to the prior - /// valid value on the bus, indicating a possible attack. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_bus_cmp_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 13)) | (u32::from(val) << 13)) - } - /// This bit is set when the !!ALERT_THRESHOLD register is not configured properly. - /// The upper field must be the exact inverse of the lower field. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_thresh_cfg_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 14)) | (u32::from(val) << 14)) - } - /// This bit is set when the packer FIFO has been written but was full at the time, - /// and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. - /// This alert would normally be the result of not monitoring the !!FW_OV_WR_FIFO_FULL - /// register before each write to the !!FW_OV_WR_DATA register. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_fw_ov_wr_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 15)) | (u32::from(val) << 15)) - } - /// This bit is set when !!FW_OV_SHA3_START has been set to MuBi4 False, without - /// waiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO - /// will not be included in the SHA3 digest. (Rather it will be added to the - /// subsequent SHA3 digest.) To avoid this alert, monitor !!FW_OV_WR_FIFO_FULL before - /// clearing !!FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and - /// FW_OV_ENTROPY_INSERT are set to MuBi4True. - /// Writing a zero resets this status bit. - #[inline(always)] - pub fn es_fw_ov_disable_alert(self, val: bool) -> Self { - Self((self.0 & !(1 << 16)) | (u32::from(val) << 16)) - } - } - impl From for RecovAlertStsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RecovAlertStsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RegwenReadVal(u32); - impl RegwenReadVal { - /// This read-only write enable bit will allow write access - /// to control and theshold registers that are associated with this bit, - /// but only when the MODULE_ENABLE field is set to kMultiBitBool4False and the - /// SW_REGUPD write enable bit is set to true. - /// When read as false, these registers become read-only. - #[inline(always)] - pub fn regwen(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for RegwenReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RegwenReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RepcntsHiWatermarksReadVal(u32); - impl RepcntsHiWatermarksReadVal { - /// High watermark value of the REPCNTS test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// High watermark value of the REPCNTS test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for RepcntsHiWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RepcntsHiWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RepcntsThresholdsReadVal(u32); - impl RepcntsThresholdsReadVal { - /// This is the threshold size for the repetition count symbol health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the repetition count symbol health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> RepcntsThresholdsWriteVal { - RepcntsThresholdsWriteVal(self.0) - } - } - impl From for RepcntsThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RepcntsThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RepcntsThresholdsWriteVal(u32); - impl RepcntsThresholdsWriteVal { - /// This is the threshold size for the repetition count symbol health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the repetition count symbol health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for RepcntsThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RepcntsThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RepcntHiWatermarksReadVal(u32); - impl RepcntHiWatermarksReadVal { - /// High watermark value of the REPCNT test in FIPS mode. - #[inline(always)] - pub fn fips_watermark(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// High watermark value of the REPCNT test in bypass mode. - #[inline(always)] - pub fn bypass_watermark(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for RepcntHiWatermarksReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RepcntHiWatermarksReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RepcntThresholdsReadVal(u32); - impl RepcntThresholdsReadVal { - /// This is the threshold size for the repetition count health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// This is the threshold size for the repetition count health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> RepcntThresholdsWriteVal { - RepcntThresholdsWriteVal(self.0) - } - } - impl From for RepcntThresholdsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RepcntThresholdsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RepcntThresholdsWriteVal(u32); - impl RepcntThresholdsWriteVal { - /// This is the threshold size for the repetition count health test. - /// This value is used in normal mode when entropy is being tested in - /// FIPS/CC compliance mode. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn fips_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// This is the threshold size for the repetition count health test - /// running in bypass mode. This mode is active after reset for the - /// first and only test run, or when this mode is programmed by firmware. - /// This register must be written before the module is enabled. - /// Writing to this register will only update the register if the - /// written value is less than the current value of this register. - /// A read from this register always reflects the current value. - #[inline(always)] - pub fn bypass_thresh(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for RepcntThresholdsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RepcntThresholdsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RevReadVal(u32); - impl RevReadVal { - /// Read of this register shows the ABI of this block. - #[inline(always)] - pub fn abi_revision(&self) -> u32 { - (self.0 >> 0) & 0xff - } - /// Read of this register shows the revision of this block. - #[inline(always)] - pub fn hw_revision(&self) -> u32 { - (self.0 >> 8) & 0xff - } - /// Read of this register shows the type of chip using this block. - #[inline(always)] - pub fn chip_type(&self) -> u32 { - (self.0 >> 16) & 0xff - } - } - impl From for RevReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RevReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct SwRegupdReadVal(u32); - impl SwRegupdReadVal { - /// When this bit true and the MODULE_ENABLE field is false, - /// the REGWEN write enable bit read as true, and is distributed to - /// all associated control and threshold registers. - /// When false, these registers become read-only. - #[inline(always)] - pub fn sw_regupd(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> SwRegupdWriteVal { - SwRegupdWriteVal(self.0) - } - } - impl From for SwRegupdReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: SwRegupdReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct SwRegupdWriteVal(u32); - impl SwRegupdWriteVal { - /// When this bit true and the MODULE_ENABLE field is false, - /// the REGWEN write enable bit read as true, and is distributed to - /// all associated control and threshold registers. - /// When false, these registers become read-only. - #[inline(always)] - pub fn sw_regupd(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for SwRegupdWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: SwRegupdWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type InterruptState = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::InterruptStateReadVal, - crate::entropy_src::regs::InterruptStateWriteVal, - >; - pub type InterruptEnable = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::InterruptEnableReadVal, - crate::entropy_src::regs::InterruptEnableWriteVal, - >; - pub type InterruptTest = - ureg::WriteOnlyReg32<0, crate::entropy_src::regs::InterruptTestWriteVal>; - pub type AlertTest = ureg::WriteOnlyReg32<0, crate::entropy_src::regs::AlertTestWriteVal>; - pub type MeRegwen = ureg::ReadWriteReg32< - 1, - crate::entropy_src::regs::MeRegwenReadVal, - crate::entropy_src::regs::MeRegwenWriteVal, - >; - pub type SwRegupd = ureg::ReadWriteReg32< - 1, - crate::entropy_src::regs::SwRegupdReadVal, - crate::entropy_src::regs::SwRegupdWriteVal, - >; - pub type Regwen = ureg::ReadOnlyReg32; - pub type Rev = ureg::ReadOnlyReg32; - pub type ModuleEnable = ureg::ReadWriteReg32< - 9, - crate::entropy_src::regs::ModuleEnableReadVal, - crate::entropy_src::regs::ModuleEnableWriteVal, - >; - pub type Conf = ureg::ReadWriteReg32< - 0x909099, - crate::entropy_src::regs::ConfReadVal, - crate::entropy_src::regs::ConfWriteVal, - >; - pub type EntropyControl = ureg::ReadWriteReg32< - 0x99, - crate::entropy_src::regs::EntropyControlReadVal, - crate::entropy_src::regs::EntropyControlWriteVal, - >; - pub type EntropyData = ureg::ReadOnlyReg32; - pub type HealthTestWindows = ureg::ReadWriteReg32< - 0x600200, - crate::entropy_src::regs::HealthTestWindowsReadVal, - crate::entropy_src::regs::HealthTestWindowsWriteVal, - >; - pub type RepcntThresholds = ureg::ReadWriteReg32< - 0xffffffff, - crate::entropy_src::regs::RepcntThresholdsReadVal, - crate::entropy_src::regs::RepcntThresholdsWriteVal, - >; - pub type RepcntsThresholds = ureg::ReadWriteReg32< - 0xffffffff, - crate::entropy_src::regs::RepcntsThresholdsReadVal, - crate::entropy_src::regs::RepcntsThresholdsWriteVal, - >; - pub type AdaptpHiThresholds = ureg::ReadWriteReg32< - 0xffffffff, - crate::entropy_src::regs::AdaptpHiThresholdsReadVal, - crate::entropy_src::regs::AdaptpHiThresholdsWriteVal, - >; - pub type AdaptpLoThresholds = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::AdaptpLoThresholdsReadVal, - crate::entropy_src::regs::AdaptpLoThresholdsWriteVal, - >; - pub type BucketThresholds = ureg::ReadWriteReg32< - 0xffffffff, - crate::entropy_src::regs::BucketThresholdsReadVal, - crate::entropy_src::regs::BucketThresholdsWriteVal, - >; - pub type MarkovHiThresholds = ureg::ReadWriteReg32< - 0xffffffff, - crate::entropy_src::regs::MarkovHiThresholdsReadVal, - crate::entropy_src::regs::MarkovHiThresholdsWriteVal, - >; - pub type MarkovLoThresholds = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::MarkovLoThresholdsReadVal, - crate::entropy_src::regs::MarkovLoThresholdsWriteVal, - >; - pub type ExthtHiThresholds = ureg::ReadWriteReg32< - 0xffffffff, - crate::entropy_src::regs::ExthtHiThresholdsReadVal, - crate::entropy_src::regs::ExthtHiThresholdsWriteVal, - >; - pub type ExthtLoThresholds = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::ExthtLoThresholdsReadVal, - crate::entropy_src::regs::ExthtLoThresholdsWriteVal, - >; - pub type RepcntHiWatermarks = - ureg::ReadOnlyReg32; - pub type RepcntsHiWatermarks = - ureg::ReadOnlyReg32; - pub type AdaptpHiWatermarks = - ureg::ReadOnlyReg32; - pub type AdaptpLoWatermarks = - ureg::ReadOnlyReg32; - pub type ExthtHiWatermarks = - ureg::ReadOnlyReg32; - pub type ExthtLoWatermarks = - ureg::ReadOnlyReg32; - pub type BucketHiWatermarks = - ureg::ReadOnlyReg32; - pub type MarkovHiWatermarks = - ureg::ReadOnlyReg32; - pub type MarkovLoWatermarks = - ureg::ReadOnlyReg32; - pub type RepcntTotalFails = ureg::ReadOnlyReg32; - pub type RepcntsTotalFails = ureg::ReadOnlyReg32; - pub type AdaptpHiTotalFails = ureg::ReadOnlyReg32; - pub type AdaptpLoTotalFails = ureg::ReadOnlyReg32; - pub type BucketTotalFails = ureg::ReadOnlyReg32; - pub type MarkovHiTotalFails = ureg::ReadOnlyReg32; - pub type MarkovLoTotalFails = ureg::ReadOnlyReg32; - pub type ExthtHiTotalFails = ureg::ReadOnlyReg32; - pub type ExthtLoTotalFails = ureg::ReadOnlyReg32; - pub type AlertThreshold = ureg::ReadWriteReg32< - 0xfffd0002, - crate::entropy_src::regs::AlertThresholdReadVal, - crate::entropy_src::regs::AlertThresholdWriteVal, - >; - pub type AlertSummaryFailCounts = - ureg::ReadOnlyReg32; - pub type AlertFailCounts = - ureg::ReadOnlyReg32; - pub type ExthtFailCounts = - ureg::ReadOnlyReg32; - pub type FwOvControl = ureg::ReadWriteReg32< - 0x99, - crate::entropy_src::regs::FwOvControlReadVal, - crate::entropy_src::regs::FwOvControlWriteVal, - >; - pub type FwOvSha3Start = ureg::ReadWriteReg32< - 9, - crate::entropy_src::regs::FwOvSha3StartReadVal, - crate::entropy_src::regs::FwOvSha3StartWriteVal, - >; - pub type FwOvWrFifoFull = ureg::ReadOnlyReg32; - pub type FwOvRdFifoOverflow = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::FwOvRdFifoOverflowReadVal, - crate::entropy_src::regs::FwOvRdFifoOverflowWriteVal, - >; - pub type FwOvRdData = ureg::ReadOnlyReg32; - pub type FwOvWrData = ureg::WriteOnlyReg32<0, u32>; - pub type ObserveFifoThresh = ureg::ReadWriteReg32< - 0x20, - crate::entropy_src::regs::ObserveFifoThreshReadVal, - crate::entropy_src::regs::ObserveFifoThreshWriteVal, - >; - pub type ObserveFifoDepth = - ureg::ReadOnlyReg32; - pub type DebugStatus = ureg::ReadOnlyReg32; - pub type RecovAlertSts = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::RecovAlertStsReadVal, - crate::entropy_src::regs::RecovAlertStsWriteVal, - >; - pub type ErrCode = ureg::ReadOnlyReg32; - pub type ErrCodeTest = ureg::ReadWriteReg32< - 0, - crate::entropy_src::regs::ErrCodeTestReadVal, - crate::entropy_src::regs::ErrCodeTestWriteVal, - >; - pub type MainSmState = ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/hmac.rs b/hw/1.0/registers/src/hmac.rs deleted file mode 100644 index 032cabb62e..0000000000 --- a/hw/1.0/registers/src/hmac.rs +++ /dev/null @@ -1,1582 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct HmacReg { - _priv: (), -} -impl HmacReg { - pub const PTR: *mut u32 = 0x10010000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Two 32-bit read-only registers repereseting of the name - /// of HMAC384 component. These registers are located at - /// HMAC384_base_address + 0x0000_0000 and 0x0000_0004 addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn name(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Two 32-bit read-only registers repereseting of the version - /// of HMAC384 component. These registers are located at - /// HMAC384_base_address + 0x0000_0008 and 0x0000_000C addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn version(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 3-bit register including the following flags: - /// bit #0: INIT : Trigs the HMAC384 core to start the - /// processing for the key and the first padded - /// message block. - /// bit #1: NEXT: ​Trigs the HMAC384 core to start the - /// processing for the remining padded message block. - /// bit #3: Zeroize all internal registers after HMAC process, to avoid SCA leakage. - /// This register is located at HMAC384_base_address + 0x0000_0010 - /// After each software write, hardware will erase the register. - /// - /// Read value: [`hmac::regs::CtrlReadVal`]; Write value: [`hmac::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 2-bit register including the following flags: - /// bit #0: READY : ​Indicates if the core is ready to take - /// a control command and process the block. - /// bit #1: Valid: ​Indicates if the process is done and the - /// results stored in TAG registers are valid. - /// This register is located at HMAC384_base_address + 0x0000_0018. - /// - /// Read value: [`hmac::regs::StatusReadVal`]; Write value: [`hmac::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the 384-bit key. - /// These registers are located at HMAC384_base_address + - /// 0x0000_0040 to 0x0000_006C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn key(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x40 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 32 32-bit registers storing the 1024-bit padded input. - /// These registers are located at HMAC384_base_address + - /// 0x0000_0080 to 0x0000_00FC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn block(&self) -> ureg::Array<32, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x80 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the 384-bit digest output. - /// These registers are located at HMAC384_base_address + - /// 0x0000_0100 to 0x0000_012C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn tag(&self) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 5 32-bit registers storing the 160-bit lfsr seed input. - /// These registers are located at HMAC384_base_address + - /// 0x0000_0130 to 0x0000_0140 in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn lfsr_seed(&self) -> ureg::Array<5, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x130 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault read access for this engine - /// - /// Read value: [`regs::KvReadCtrlRegReadVal`]; Write value: [`regs::KvReadCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_rd_key_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x600 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_rd_key_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x604 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault read access for this engine - /// - /// Read value: [`regs::KvReadCtrlRegReadVal`]; Write value: [`regs::KvReadCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_rd_block_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x608 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_rd_block_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x60c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault write access for this engine - /// - /// Read value: [`regs::KvWriteCtrlRegReadVal`]; Write value: [`regs::KvWriteCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_wr_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x610 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_wr_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x614 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrEnTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::NotifIntrEnTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error0_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error1_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error2_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error3_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error0_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error1_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error2_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error3_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x210 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// Control init command bit - #[inline(always)] - pub fn init(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Control next command bit - #[inline(always)] - pub fn next(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Zeroize all internal registers - #[inline(always)] - pub fn zeroize(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Status ready bit - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Status valid bit - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTReadVal(u32); - impl GlobalIntrEnTReadVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> GlobalIntrEnTWriteVal { - GlobalIntrEnTWriteVal(self.0) - } - } - impl From for GlobalIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTWriteVal(u32); - impl GlobalIntrEnTWriteVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for GlobalIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrTReadVal(u32); - impl GlobalIntrTReadVal { - /// Interrupt Event Aggregation status bit - #[inline(always)] - pub fn agg_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for GlobalIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntrCountIncrTReadVal(u32); - impl IntrCountIncrTReadVal { - /// Pulse mirrors interrupt event occurrence - #[inline(always)] - pub fn pulse(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for IntrCountIncrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntrCountIncrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum KvErrorE { - Success = 0, - KvReadFail = 1, - KvWriteFail = 2, - Reserved3 = 3, - Reserved4 = 4, - Reserved5 = 5, - Reserved6 = 6, - Reserved7 = 7, - Reserved8 = 8, - Reserved9 = 9, - Reserved10 = 10, - Reserved11 = 11, - Reserved12 = 12, - Reserved13 = 13, - Reserved14 = 14, - Reserved15 = 15, - Reserved16 = 16, - Reserved17 = 17, - Reserved18 = 18, - Reserved19 = 19, - Reserved20 = 20, - Reserved21 = 21, - Reserved22 = 22, - Reserved23 = 23, - Reserved24 = 24, - Reserved25 = 25, - Reserved26 = 26, - Reserved27 = 27, - Reserved28 = 28, - Reserved29 = 29, - Reserved30 = 30, - Reserved31 = 31, - Reserved32 = 32, - Reserved33 = 33, - Reserved34 = 34, - Reserved35 = 35, - Reserved36 = 36, - Reserved37 = 37, - Reserved38 = 38, - Reserved39 = 39, - Reserved40 = 40, - Reserved41 = 41, - Reserved42 = 42, - Reserved43 = 43, - Reserved44 = 44, - Reserved45 = 45, - Reserved46 = 46, - Reserved47 = 47, - Reserved48 = 48, - Reserved49 = 49, - Reserved50 = 50, - Reserved51 = 51, - Reserved52 = 52, - Reserved53 = 53, - Reserved54 = 54, - Reserved55 = 55, - Reserved56 = 56, - Reserved57 = 57, - Reserved58 = 58, - Reserved59 = 59, - Reserved60 = 60, - Reserved61 = 61, - Reserved62 = 62, - Reserved63 = 63, - Reserved64 = 64, - Reserved65 = 65, - Reserved66 = 66, - Reserved67 = 67, - Reserved68 = 68, - Reserved69 = 69, - Reserved70 = 70, - Reserved71 = 71, - Reserved72 = 72, - Reserved73 = 73, - Reserved74 = 74, - Reserved75 = 75, - Reserved76 = 76, - Reserved77 = 77, - Reserved78 = 78, - Reserved79 = 79, - Reserved80 = 80, - Reserved81 = 81, - Reserved82 = 82, - Reserved83 = 83, - Reserved84 = 84, - Reserved85 = 85, - Reserved86 = 86, - Reserved87 = 87, - Reserved88 = 88, - Reserved89 = 89, - Reserved90 = 90, - Reserved91 = 91, - Reserved92 = 92, - Reserved93 = 93, - Reserved94 = 94, - Reserved95 = 95, - Reserved96 = 96, - Reserved97 = 97, - Reserved98 = 98, - Reserved99 = 99, - Reserved100 = 100, - Reserved101 = 101, - Reserved102 = 102, - Reserved103 = 103, - Reserved104 = 104, - Reserved105 = 105, - Reserved106 = 106, - Reserved107 = 107, - Reserved108 = 108, - Reserved109 = 109, - Reserved110 = 110, - Reserved111 = 111, - Reserved112 = 112, - Reserved113 = 113, - Reserved114 = 114, - Reserved115 = 115, - Reserved116 = 116, - Reserved117 = 117, - Reserved118 = 118, - Reserved119 = 119, - Reserved120 = 120, - Reserved121 = 121, - Reserved122 = 122, - Reserved123 = 123, - Reserved124 = 124, - Reserved125 = 125, - Reserved126 = 126, - Reserved127 = 127, - Reserved128 = 128, - Reserved129 = 129, - Reserved130 = 130, - Reserved131 = 131, - Reserved132 = 132, - Reserved133 = 133, - Reserved134 = 134, - Reserved135 = 135, - Reserved136 = 136, - Reserved137 = 137, - Reserved138 = 138, - Reserved139 = 139, - Reserved140 = 140, - Reserved141 = 141, - Reserved142 = 142, - Reserved143 = 143, - Reserved144 = 144, - Reserved145 = 145, - Reserved146 = 146, - Reserved147 = 147, - Reserved148 = 148, - Reserved149 = 149, - Reserved150 = 150, - Reserved151 = 151, - Reserved152 = 152, - Reserved153 = 153, - Reserved154 = 154, - Reserved155 = 155, - Reserved156 = 156, - Reserved157 = 157, - Reserved158 = 158, - Reserved159 = 159, - Reserved160 = 160, - Reserved161 = 161, - Reserved162 = 162, - Reserved163 = 163, - Reserved164 = 164, - Reserved165 = 165, - Reserved166 = 166, - Reserved167 = 167, - Reserved168 = 168, - Reserved169 = 169, - Reserved170 = 170, - Reserved171 = 171, - Reserved172 = 172, - Reserved173 = 173, - Reserved174 = 174, - Reserved175 = 175, - Reserved176 = 176, - Reserved177 = 177, - Reserved178 = 178, - Reserved179 = 179, - Reserved180 = 180, - Reserved181 = 181, - Reserved182 = 182, - Reserved183 = 183, - Reserved184 = 184, - Reserved185 = 185, - Reserved186 = 186, - Reserved187 = 187, - Reserved188 = 188, - Reserved189 = 189, - Reserved190 = 190, - Reserved191 = 191, - Reserved192 = 192, - Reserved193 = 193, - Reserved194 = 194, - Reserved195 = 195, - Reserved196 = 196, - Reserved197 = 197, - Reserved198 = 198, - Reserved199 = 199, - Reserved200 = 200, - Reserved201 = 201, - Reserved202 = 202, - Reserved203 = 203, - Reserved204 = 204, - Reserved205 = 205, - Reserved206 = 206, - Reserved207 = 207, - Reserved208 = 208, - Reserved209 = 209, - Reserved210 = 210, - Reserved211 = 211, - Reserved212 = 212, - Reserved213 = 213, - Reserved214 = 214, - Reserved215 = 215, - Reserved216 = 216, - Reserved217 = 217, - Reserved218 = 218, - Reserved219 = 219, - Reserved220 = 220, - Reserved221 = 221, - Reserved222 = 222, - Reserved223 = 223, - Reserved224 = 224, - Reserved225 = 225, - Reserved226 = 226, - Reserved227 = 227, - Reserved228 = 228, - Reserved229 = 229, - Reserved230 = 230, - Reserved231 = 231, - Reserved232 = 232, - Reserved233 = 233, - Reserved234 = 234, - Reserved235 = 235, - Reserved236 = 236, - Reserved237 = 237, - Reserved238 = 238, - Reserved239 = 239, - Reserved240 = 240, - Reserved241 = 241, - Reserved242 = 242, - Reserved243 = 243, - Reserved244 = 244, - Reserved245 = 245, - Reserved246 = 246, - Reserved247 = 247, - Reserved248 = 248, - Reserved249 = 249, - Reserved250 = 250, - Reserved251 = 251, - Reserved252 = 252, - Reserved253 = 253, - Reserved254 = 254, - Reserved255 = 255, - } - impl KvErrorE { - #[inline(always)] - pub fn success(&self) -> bool { - *self == Self::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> bool { - *self == Self::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> bool { - *self == Self::KvWriteFail - } - } - impl TryFrom for KvErrorE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 0x100 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: KvErrorE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct KvErrorESelector(); - impl KvErrorESelector { - #[inline(always)] - pub fn success(&self) -> super::KvErrorE { - super::KvErrorE::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvWriteFail - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Name = ureg::ReadOnlyReg32; - pub type Version = ureg::ReadOnlyReg32; - pub type Ctrl = ureg::WriteOnlyReg32<0, crate::hmac::regs::CtrlWriteVal>; - pub type Status = ureg::ReadOnlyReg32; - pub type Key = ureg::WriteOnlyReg32<0, u32>; - pub type Block = ureg::WriteOnlyReg32<0, u32>; - pub type Tag = ureg::ReadOnlyReg32; - pub type LfsrSeed = ureg::WriteOnlyReg32<0x3cabffb0, u32>; - pub type KvRdKeyCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvReadCtrlRegReadVal, - crate::regs::KvReadCtrlRegWriteVal, - >; - pub type KvRdKeyStatus = ureg::ReadOnlyReg32; - pub type KvRdBlockCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvReadCtrlRegReadVal, - crate::regs::KvReadCtrlRegWriteVal, - >; - pub type KvRdBlockStatus = ureg::ReadOnlyReg32; - pub type KvWrCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvWriteCtrlRegReadVal, - crate::regs::KvWriteCtrlRegWriteVal, - >; - pub type KvWrStatus = ureg::ReadOnlyReg32; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrEnTReadVal, - crate::sha512_acc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrEnTReadVal, - crate::sha512_acc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTReadVal, - crate::sha512_acc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTReadVal, - crate::sha512_acc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTrigTReadVal, - crate::sha512_acc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTrigTReadVal, - crate::sha512_acc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfError0IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError1IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError2IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError3IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdDoneIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError0IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError1IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError2IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError3IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdDoneIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/kv.rs b/hw/1.0/registers/src/kv.rs deleted file mode 100644 index e193cecd63..0000000000 --- a/hw/1.0/registers/src/kv.rs +++ /dev/null @@ -1,291 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct KvReg { - _priv: (), -} -impl KvReg { - pub const PTR: *mut u32 = 0x10018000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Controls for each keyvault and pcr entry - /// - /// Read value: [`kv::regs::KvctrlReadVal`]; Write value: [`kv::regs::KvctrlWriteVal`] - #[inline(always)] - pub fn key_ctrl(&self) -> ureg::Array<32, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Key Entries are not readable or writeable by software - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn key_entry( - &self, - ) -> ureg::Array<32, ureg::Array<12, ureg::RegRef>> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x600 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`kv::regs::ClearSecretsReadVal`]; Write value: [`kv::regs::ClearSecretsWriteVal`] - #[inline(always)] - pub fn clear_secrets(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc00 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct ClearSecretsReadVal(u32); - impl ClearSecretsReadVal { - /// Fill the keyvault with debug values - #[inline(always)] - pub fn wr_debug_values(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Selects between debug value 0 or 1 parameter to write to keyvault - #[inline(always)] - pub fn sel_debug_value(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ClearSecretsWriteVal { - ClearSecretsWriteVal(self.0) - } - } - impl From for ClearSecretsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ClearSecretsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ClearSecretsWriteVal(u32); - impl ClearSecretsWriteVal { - /// Fill the keyvault with debug values - #[inline(always)] - pub fn wr_debug_values(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Selects between debug value 0 or 1 parameter to write to keyvault - #[inline(always)] - pub fn sel_debug_value(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for ClearSecretsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ClearSecretsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct KvctrlReadVal(u32); - impl KvctrlReadVal { - /// Lock writes to this entry. Writes will be suppressed and an error will be recorded. - #[inline(always)] - pub fn lock_wr(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Lock use of this entry. Reads will be suppressed and an error will be recorded. - #[inline(always)] - pub fn lock_use(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Clear the data stored in this entry. Lock write will prevent this clear. - #[inline(always)] - pub fn clear(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Reserved - #[inline(always)] - pub fn rsvd0(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Reserved - #[inline(always)] - pub fn rsvd1(&self) -> u32 { - (self.0 >> 4) & 0x1f - } - /// Destination valid bits stored as an array for ease of use in RTL. - /// [br]dest_valid[0] = hmac_key_dest_valid - /// [br]dest_valid[1] = hmac_block_dest_valid - /// [br]dest_valid[2] = sha_block_dest_valid - /// [br]dest_valid[3] = ecc_pkey_dest_valid - /// [br]dest_valid[4] = ecc_seed_dest_valid - /// [br]dest_valid[5] = rsvd - /// [br]dest_valid[6] = rsvd - /// [br]dest_valid[7] = rsvd - #[inline(always)] - pub fn dest_valid(&self) -> u32 { - (self.0 >> 9) & 0xff - } - /// Stores the offset of the last valid dword, used to indicate last cycle on reads. - #[inline(always)] - pub fn last_dword(&self) -> u32 { - (self.0 >> 17) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> KvctrlWriteVal { - KvctrlWriteVal(self.0) - } - } - impl From for KvctrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvctrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct KvctrlWriteVal(u32); - impl KvctrlWriteVal { - /// Lock writes to this entry. Writes will be suppressed and an error will be recorded. - #[inline(always)] - pub fn lock_wr(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Lock use of this entry. Reads will be suppressed and an error will be recorded. - #[inline(always)] - pub fn lock_use(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Clear the data stored in this entry. Lock write will prevent this clear. - #[inline(always)] - pub fn clear(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Reserved - #[inline(always)] - pub fn rsvd0(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Reserved - #[inline(always)] - pub fn rsvd1(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 4)) | ((val & 0x1f) << 4)) - } - } - impl From for KvctrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvctrlWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type KeyCtrl = - ureg::ReadWriteReg32<0, crate::kv::regs::KvctrlReadVal, crate::kv::regs::KvctrlWriteVal>; - pub type KeyEntry = ureg::WriteOnlyReg32<0, u32>; - pub type ClearSecrets = ureg::ReadWriteReg32< - 0, - crate::kv::regs::ClearSecretsReadVal, - crate::kv::regs::ClearSecretsWriteVal, - >; -} diff --git a/hw/1.0/registers/src/lib.rs b/hw/1.0/registers/src/lib.rs deleted file mode 100644 index 3c10625ba8..0000000000 --- a/hw/1.0/registers/src/lib.rs +++ /dev/null @@ -1,874 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![no_std] -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct KvReadCtrlRegReadVal(u32); - impl KvReadCtrlRegReadVal { - /// Indicates that the read data is to come from the key vault. - /// Setting this bit to 1 initiates copying of data from the key vault. - #[inline(always)] - pub fn read_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Key Vault entry to retrieve the read data from for the engine - #[inline(always)] - pub fn read_entry(&self) -> u32 { - (self.0 >> 1) & 0x1f - } - /// Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines - #[inline(always)] - pub fn pcr_hash_extend(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// Reserved field - #[inline(always)] - pub fn rsvd(&self) -> u32 { - (self.0 >> 7) & 0x1ffffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> KvReadCtrlRegWriteVal { - KvReadCtrlRegWriteVal(self.0) - } - } - impl From for KvReadCtrlRegReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvReadCtrlRegReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct KvReadCtrlRegWriteVal(u32); - impl KvReadCtrlRegWriteVal { - /// Indicates that the read data is to come from the key vault. - /// Setting this bit to 1 initiates copying of data from the key vault. - #[inline(always)] - pub fn read_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Key Vault entry to retrieve the read data from for the engine - #[inline(always)] - pub fn read_entry(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 1)) | ((val & 0x1f) << 1)) - } - /// Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines - #[inline(always)] - pub fn pcr_hash_extend(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// Reserved field - #[inline(always)] - pub fn rsvd(self, val: u32) -> Self { - Self((self.0 & !(0x1ffffff << 7)) | ((val & 0x1ffffff) << 7)) - } - } - impl From for KvReadCtrlRegWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvReadCtrlRegWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct KvStatusRegReadVal(u32); - impl KvStatusRegReadVal { - /// Key Vault control is ready for use - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Key Vault flow is done - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Indicates the error status of a key vault flow - #[inline(always)] - pub fn error(&self) -> super::enums::KvErrorE { - super::enums::KvErrorE::try_from((self.0 >> 2) & 0xff).unwrap() - } - } - impl From for KvStatusRegReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvStatusRegReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct KvWriteCtrlRegReadVal(u32); - impl KvWriteCtrlRegReadVal { - /// Indicates that the result is to be stored in the key vault. - /// Setting this bit to 1 will copy the result to the keyvault when it is ready. - #[inline(always)] - pub fn write_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Key Vault entry to store the result - #[inline(always)] - pub fn write_entry(&self) -> u32 { - (self.0 >> 1) & 0x1f - } - /// HMAC KEY is a valid destination - #[inline(always)] - pub fn hmac_key_dest_valid(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// HMAC BLOCK is a valid destination - #[inline(always)] - pub fn hmac_block_dest_valid(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// SHA BLOCK is a valid destination - #[inline(always)] - pub fn sha_block_dest_valid(&self) -> bool { - ((self.0 >> 8) & 1) != 0 - } - /// ECC PKEY is a valid destination - #[inline(always)] - pub fn ecc_pkey_dest_valid(&self) -> bool { - ((self.0 >> 9) & 1) != 0 - } - /// ECC SEED is a valid destination - #[inline(always)] - pub fn ecc_seed_dest_valid(&self) -> bool { - ((self.0 >> 10) & 1) != 0 - } - /// Reserved field - #[inline(always)] - pub fn rsvd(&self) -> u32 { - (self.0 >> 11) & 0x1fffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> KvWriteCtrlRegWriteVal { - KvWriteCtrlRegWriteVal(self.0) - } - } - impl From for KvWriteCtrlRegReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvWriteCtrlRegReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct KvWriteCtrlRegWriteVal(u32); - impl KvWriteCtrlRegWriteVal { - /// Indicates that the result is to be stored in the key vault. - /// Setting this bit to 1 will copy the result to the keyvault when it is ready. - #[inline(always)] - pub fn write_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Key Vault entry to store the result - #[inline(always)] - pub fn write_entry(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 1)) | ((val & 0x1f) << 1)) - } - /// HMAC KEY is a valid destination - #[inline(always)] - pub fn hmac_key_dest_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// HMAC BLOCK is a valid destination - #[inline(always)] - pub fn hmac_block_dest_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - /// SHA BLOCK is a valid destination - #[inline(always)] - pub fn sha_block_dest_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 8)) | (u32::from(val) << 8)) - } - /// ECC PKEY is a valid destination - #[inline(always)] - pub fn ecc_pkey_dest_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 9)) | (u32::from(val) << 9)) - } - /// ECC SEED is a valid destination - #[inline(always)] - pub fn ecc_seed_dest_valid(self, val: bool) -> Self { - Self((self.0 & !(1 << 10)) | (u32::from(val) << 10)) - } - /// Reserved field - #[inline(always)] - pub fn rsvd(self, val: u32) -> Self { - Self((self.0 & !(0x1fffff << 11)) | ((val & 0x1fffff) << 11)) - } - } - impl From for KvWriteCtrlRegWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: KvWriteCtrlRegWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum KvErrorE { - Success = 0, - KvReadFail = 1, - KvWriteFail = 2, - Reserved3 = 3, - Reserved4 = 4, - Reserved5 = 5, - Reserved6 = 6, - Reserved7 = 7, - Reserved8 = 8, - Reserved9 = 9, - Reserved10 = 10, - Reserved11 = 11, - Reserved12 = 12, - Reserved13 = 13, - Reserved14 = 14, - Reserved15 = 15, - Reserved16 = 16, - Reserved17 = 17, - Reserved18 = 18, - Reserved19 = 19, - Reserved20 = 20, - Reserved21 = 21, - Reserved22 = 22, - Reserved23 = 23, - Reserved24 = 24, - Reserved25 = 25, - Reserved26 = 26, - Reserved27 = 27, - Reserved28 = 28, - Reserved29 = 29, - Reserved30 = 30, - Reserved31 = 31, - Reserved32 = 32, - Reserved33 = 33, - Reserved34 = 34, - Reserved35 = 35, - Reserved36 = 36, - Reserved37 = 37, - Reserved38 = 38, - Reserved39 = 39, - Reserved40 = 40, - Reserved41 = 41, - Reserved42 = 42, - Reserved43 = 43, - Reserved44 = 44, - Reserved45 = 45, - Reserved46 = 46, - Reserved47 = 47, - Reserved48 = 48, - Reserved49 = 49, - Reserved50 = 50, - Reserved51 = 51, - Reserved52 = 52, - Reserved53 = 53, - Reserved54 = 54, - Reserved55 = 55, - Reserved56 = 56, - Reserved57 = 57, - Reserved58 = 58, - Reserved59 = 59, - Reserved60 = 60, - Reserved61 = 61, - Reserved62 = 62, - Reserved63 = 63, - Reserved64 = 64, - Reserved65 = 65, - Reserved66 = 66, - Reserved67 = 67, - Reserved68 = 68, - Reserved69 = 69, - Reserved70 = 70, - Reserved71 = 71, - Reserved72 = 72, - Reserved73 = 73, - Reserved74 = 74, - Reserved75 = 75, - Reserved76 = 76, - Reserved77 = 77, - Reserved78 = 78, - Reserved79 = 79, - Reserved80 = 80, - Reserved81 = 81, - Reserved82 = 82, - Reserved83 = 83, - Reserved84 = 84, - Reserved85 = 85, - Reserved86 = 86, - Reserved87 = 87, - Reserved88 = 88, - Reserved89 = 89, - Reserved90 = 90, - Reserved91 = 91, - Reserved92 = 92, - Reserved93 = 93, - Reserved94 = 94, - Reserved95 = 95, - Reserved96 = 96, - Reserved97 = 97, - Reserved98 = 98, - Reserved99 = 99, - Reserved100 = 100, - Reserved101 = 101, - Reserved102 = 102, - Reserved103 = 103, - Reserved104 = 104, - Reserved105 = 105, - Reserved106 = 106, - Reserved107 = 107, - Reserved108 = 108, - Reserved109 = 109, - Reserved110 = 110, - Reserved111 = 111, - Reserved112 = 112, - Reserved113 = 113, - Reserved114 = 114, - Reserved115 = 115, - Reserved116 = 116, - Reserved117 = 117, - Reserved118 = 118, - Reserved119 = 119, - Reserved120 = 120, - Reserved121 = 121, - Reserved122 = 122, - Reserved123 = 123, - Reserved124 = 124, - Reserved125 = 125, - Reserved126 = 126, - Reserved127 = 127, - Reserved128 = 128, - Reserved129 = 129, - Reserved130 = 130, - Reserved131 = 131, - Reserved132 = 132, - Reserved133 = 133, - Reserved134 = 134, - Reserved135 = 135, - Reserved136 = 136, - Reserved137 = 137, - Reserved138 = 138, - Reserved139 = 139, - Reserved140 = 140, - Reserved141 = 141, - Reserved142 = 142, - Reserved143 = 143, - Reserved144 = 144, - Reserved145 = 145, - Reserved146 = 146, - Reserved147 = 147, - Reserved148 = 148, - Reserved149 = 149, - Reserved150 = 150, - Reserved151 = 151, - Reserved152 = 152, - Reserved153 = 153, - Reserved154 = 154, - Reserved155 = 155, - Reserved156 = 156, - Reserved157 = 157, - Reserved158 = 158, - Reserved159 = 159, - Reserved160 = 160, - Reserved161 = 161, - Reserved162 = 162, - Reserved163 = 163, - Reserved164 = 164, - Reserved165 = 165, - Reserved166 = 166, - Reserved167 = 167, - Reserved168 = 168, - Reserved169 = 169, - Reserved170 = 170, - Reserved171 = 171, - Reserved172 = 172, - Reserved173 = 173, - Reserved174 = 174, - Reserved175 = 175, - Reserved176 = 176, - Reserved177 = 177, - Reserved178 = 178, - Reserved179 = 179, - Reserved180 = 180, - Reserved181 = 181, - Reserved182 = 182, - Reserved183 = 183, - Reserved184 = 184, - Reserved185 = 185, - Reserved186 = 186, - Reserved187 = 187, - Reserved188 = 188, - Reserved189 = 189, - Reserved190 = 190, - Reserved191 = 191, - Reserved192 = 192, - Reserved193 = 193, - Reserved194 = 194, - Reserved195 = 195, - Reserved196 = 196, - Reserved197 = 197, - Reserved198 = 198, - Reserved199 = 199, - Reserved200 = 200, - Reserved201 = 201, - Reserved202 = 202, - Reserved203 = 203, - Reserved204 = 204, - Reserved205 = 205, - Reserved206 = 206, - Reserved207 = 207, - Reserved208 = 208, - Reserved209 = 209, - Reserved210 = 210, - Reserved211 = 211, - Reserved212 = 212, - Reserved213 = 213, - Reserved214 = 214, - Reserved215 = 215, - Reserved216 = 216, - Reserved217 = 217, - Reserved218 = 218, - Reserved219 = 219, - Reserved220 = 220, - Reserved221 = 221, - Reserved222 = 222, - Reserved223 = 223, - Reserved224 = 224, - Reserved225 = 225, - Reserved226 = 226, - Reserved227 = 227, - Reserved228 = 228, - Reserved229 = 229, - Reserved230 = 230, - Reserved231 = 231, - Reserved232 = 232, - Reserved233 = 233, - Reserved234 = 234, - Reserved235 = 235, - Reserved236 = 236, - Reserved237 = 237, - Reserved238 = 238, - Reserved239 = 239, - Reserved240 = 240, - Reserved241 = 241, - Reserved242 = 242, - Reserved243 = 243, - Reserved244 = 244, - Reserved245 = 245, - Reserved246 = 246, - Reserved247 = 247, - Reserved248 = 248, - Reserved249 = 249, - Reserved250 = 250, - Reserved251 = 251, - Reserved252 = 252, - Reserved253 = 253, - Reserved254 = 254, - Reserved255 = 255, - } - impl KvErrorE { - #[inline(always)] - pub fn success(&self) -> bool { - *self == Self::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> bool { - *self == Self::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> bool { - *self == Self::KvWriteFail - } - } - impl TryFrom for KvErrorE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 0x100 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: KvErrorE) -> Self { - val as u32 - } - } - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum PvErrorE { - Success = 0, - PvReadFail = 1, - PvWriteFail = 2, - Reserved3 = 3, - Reserved4 = 4, - Reserved5 = 5, - Reserved6 = 6, - Reserved7 = 7, - Reserved8 = 8, - Reserved9 = 9, - Reserved10 = 10, - Reserved11 = 11, - Reserved12 = 12, - Reserved13 = 13, - Reserved14 = 14, - Reserved15 = 15, - Reserved16 = 16, - Reserved17 = 17, - Reserved18 = 18, - Reserved19 = 19, - Reserved20 = 20, - Reserved21 = 21, - Reserved22 = 22, - Reserved23 = 23, - Reserved24 = 24, - Reserved25 = 25, - Reserved26 = 26, - Reserved27 = 27, - Reserved28 = 28, - Reserved29 = 29, - Reserved30 = 30, - Reserved31 = 31, - Reserved32 = 32, - Reserved33 = 33, - Reserved34 = 34, - Reserved35 = 35, - Reserved36 = 36, - Reserved37 = 37, - Reserved38 = 38, - Reserved39 = 39, - Reserved40 = 40, - Reserved41 = 41, - Reserved42 = 42, - Reserved43 = 43, - Reserved44 = 44, - Reserved45 = 45, - Reserved46 = 46, - Reserved47 = 47, - Reserved48 = 48, - Reserved49 = 49, - Reserved50 = 50, - Reserved51 = 51, - Reserved52 = 52, - Reserved53 = 53, - Reserved54 = 54, - Reserved55 = 55, - Reserved56 = 56, - Reserved57 = 57, - Reserved58 = 58, - Reserved59 = 59, - Reserved60 = 60, - Reserved61 = 61, - Reserved62 = 62, - Reserved63 = 63, - Reserved64 = 64, - Reserved65 = 65, - Reserved66 = 66, - Reserved67 = 67, - Reserved68 = 68, - Reserved69 = 69, - Reserved70 = 70, - Reserved71 = 71, - Reserved72 = 72, - Reserved73 = 73, - Reserved74 = 74, - Reserved75 = 75, - Reserved76 = 76, - Reserved77 = 77, - Reserved78 = 78, - Reserved79 = 79, - Reserved80 = 80, - Reserved81 = 81, - Reserved82 = 82, - Reserved83 = 83, - Reserved84 = 84, - Reserved85 = 85, - Reserved86 = 86, - Reserved87 = 87, - Reserved88 = 88, - Reserved89 = 89, - Reserved90 = 90, - Reserved91 = 91, - Reserved92 = 92, - Reserved93 = 93, - Reserved94 = 94, - Reserved95 = 95, - Reserved96 = 96, - Reserved97 = 97, - Reserved98 = 98, - Reserved99 = 99, - Reserved100 = 100, - Reserved101 = 101, - Reserved102 = 102, - Reserved103 = 103, - Reserved104 = 104, - Reserved105 = 105, - Reserved106 = 106, - Reserved107 = 107, - Reserved108 = 108, - Reserved109 = 109, - Reserved110 = 110, - Reserved111 = 111, - Reserved112 = 112, - Reserved113 = 113, - Reserved114 = 114, - Reserved115 = 115, - Reserved116 = 116, - Reserved117 = 117, - Reserved118 = 118, - Reserved119 = 119, - Reserved120 = 120, - Reserved121 = 121, - Reserved122 = 122, - Reserved123 = 123, - Reserved124 = 124, - Reserved125 = 125, - Reserved126 = 126, - Reserved127 = 127, - Reserved128 = 128, - Reserved129 = 129, - Reserved130 = 130, - Reserved131 = 131, - Reserved132 = 132, - Reserved133 = 133, - Reserved134 = 134, - Reserved135 = 135, - Reserved136 = 136, - Reserved137 = 137, - Reserved138 = 138, - Reserved139 = 139, - Reserved140 = 140, - Reserved141 = 141, - Reserved142 = 142, - Reserved143 = 143, - Reserved144 = 144, - Reserved145 = 145, - Reserved146 = 146, - Reserved147 = 147, - Reserved148 = 148, - Reserved149 = 149, - Reserved150 = 150, - Reserved151 = 151, - Reserved152 = 152, - Reserved153 = 153, - Reserved154 = 154, - Reserved155 = 155, - Reserved156 = 156, - Reserved157 = 157, - Reserved158 = 158, - Reserved159 = 159, - Reserved160 = 160, - Reserved161 = 161, - Reserved162 = 162, - Reserved163 = 163, - Reserved164 = 164, - Reserved165 = 165, - Reserved166 = 166, - Reserved167 = 167, - Reserved168 = 168, - Reserved169 = 169, - Reserved170 = 170, - Reserved171 = 171, - Reserved172 = 172, - Reserved173 = 173, - Reserved174 = 174, - Reserved175 = 175, - Reserved176 = 176, - Reserved177 = 177, - Reserved178 = 178, - Reserved179 = 179, - Reserved180 = 180, - Reserved181 = 181, - Reserved182 = 182, - Reserved183 = 183, - Reserved184 = 184, - Reserved185 = 185, - Reserved186 = 186, - Reserved187 = 187, - Reserved188 = 188, - Reserved189 = 189, - Reserved190 = 190, - Reserved191 = 191, - Reserved192 = 192, - Reserved193 = 193, - Reserved194 = 194, - Reserved195 = 195, - Reserved196 = 196, - Reserved197 = 197, - Reserved198 = 198, - Reserved199 = 199, - Reserved200 = 200, - Reserved201 = 201, - Reserved202 = 202, - Reserved203 = 203, - Reserved204 = 204, - Reserved205 = 205, - Reserved206 = 206, - Reserved207 = 207, - Reserved208 = 208, - Reserved209 = 209, - Reserved210 = 210, - Reserved211 = 211, - Reserved212 = 212, - Reserved213 = 213, - Reserved214 = 214, - Reserved215 = 215, - Reserved216 = 216, - Reserved217 = 217, - Reserved218 = 218, - Reserved219 = 219, - Reserved220 = 220, - Reserved221 = 221, - Reserved222 = 222, - Reserved223 = 223, - Reserved224 = 224, - Reserved225 = 225, - Reserved226 = 226, - Reserved227 = 227, - Reserved228 = 228, - Reserved229 = 229, - Reserved230 = 230, - Reserved231 = 231, - Reserved232 = 232, - Reserved233 = 233, - Reserved234 = 234, - Reserved235 = 235, - Reserved236 = 236, - Reserved237 = 237, - Reserved238 = 238, - Reserved239 = 239, - Reserved240 = 240, - Reserved241 = 241, - Reserved242 = 242, - Reserved243 = 243, - Reserved244 = 244, - Reserved245 = 245, - Reserved246 = 246, - Reserved247 = 247, - Reserved248 = 248, - Reserved249 = 249, - Reserved250 = 250, - Reserved251 = 251, - Reserved252 = 252, - Reserved253 = 253, - Reserved254 = 254, - Reserved255 = 255, - } - impl PvErrorE { - #[inline(always)] - pub fn success(&self) -> bool { - *self == Self::Success - } - #[inline(always)] - pub fn pv_read_fail(&self) -> bool { - *self == Self::PvReadFail - } - #[inline(always)] - pub fn pv_write_fail(&self) -> bool { - *self == Self::PvWriteFail - } - } - impl TryFrom for PvErrorE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 0x100 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: PvErrorE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct KvErrorESelector(); - impl KvErrorESelector { - #[inline(always)] - pub fn success(&self) -> super::KvErrorE { - super::KvErrorE::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvWriteFail - } - } - pub struct PvErrorESelector(); - impl PvErrorESelector { - #[inline(always)] - pub fn success(&self) -> super::PvErrorE { - super::PvErrorE::Success - } - #[inline(always)] - pub fn pv_read_fail(&self) -> super::PvErrorE { - super::PvErrorE::PvReadFail - } - #[inline(always)] - pub fn pv_write_fail(&self) -> super::PvErrorE { - super::PvErrorE::PvWriteFail - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. -} -pub mod csrng; -pub mod doe; -pub mod dv; -pub mod ecc; -pub mod el2_pic_ctrl; -pub mod entropy_src; -pub mod hmac; -pub mod kv; -pub mod mbox; -pub mod pv; -pub mod sha256; -pub mod sha512; -pub mod sha512_acc; -pub mod soc_ifc; -pub mod soc_ifc_trng; -pub mod spi_host; -pub mod uart; diff --git a/hw/1.0/registers/src/mbox.rs b/hw/1.0/registers/src/mbox.rs deleted file mode 100644 index 991380df35..0000000000 --- a/hw/1.0/registers/src/mbox.rs +++ /dev/null @@ -1,615 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct MboxCsr { - _priv: (), -} -impl MboxCsr { - pub const PTR: *mut u32 = 0x30020000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Mailbox lock register for mailbox access, reading 0 will set the lock - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`mbox::regs::LockReadVal`]; Write value: [`mbox::regs::LockWriteVal`] - #[inline(always)] - pub fn lock(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Stores the user that locked the mailbox - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn user(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Command requested for data in mailbox - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cmd(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Data length for mailbox access in bytes - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn dlen(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Data in register, write the next data to mailbox - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn datain(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Data out register, read the next data from mailbox - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn dataout(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Mailbox execute register indicates to receiver that the sender is done - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`mbox::regs::ExecuteReadVal`]; Write value: [`mbox::regs::ExecuteWriteVal`] - #[inline(always)] - pub fn execute(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Status of the mailbox command - /// - /// Read value: [`mbox::regs::StatusReadVal`]; Write value: [`mbox::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Capability for uC only to force unlock the mailbox. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`mbox::regs::UnlockReadVal`]; Write value: [`mbox::regs::UnlockWriteVal`] - #[inline(always)] - pub fn unlock(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct ExecuteReadVal(u32); - impl ExecuteReadVal { - /// - #[inline(always)] - pub fn execute(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ExecuteWriteVal { - ExecuteWriteVal(self.0) - } - } - impl From for ExecuteReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExecuteReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExecuteWriteVal(u32); - impl ExecuteWriteVal { - /// - #[inline(always)] - pub fn execute(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for ExecuteWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExecuteWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct LockReadVal(u32); - impl LockReadVal { - /// - #[inline(always)] - pub fn lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for LockReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: LockReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Indicates the status of mailbox command - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn status(&self) -> super::enums::MboxStatusE { - super::enums::MboxStatusE::try_from((self.0 >> 0) & 0xf).unwrap() - } - /// Indicates a correctable ECC single-bit error was - /// detected and corrected while reading dataout. - /// Auto-clears when mbox_execute field is cleared. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn ecc_single_error(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Indicates an uncorrectable ECC double-bit error - /// was detected while reading dataout. - /// Firmware developers are advised to set the command - /// status to CMD_FAILURE in response. - /// Auto-clears when mbox_execute field is cleared. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn ecc_double_error(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Indicates the present state of the mailbox FSM - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn mbox_fsm_ps(&self) -> super::enums::MboxFsmE { - super::enums::MboxFsmE::try_from((self.0 >> 6) & 7).unwrap() - } - /// Indicates that the current lock was acquired by the SoC - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn soc_has_lock(&self) -> bool { - ((self.0 >> 9) & 1) != 0 - } - /// Returns the current read pointer for the mailbox - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn mbox_rdptr(&self) -> u32 { - (self.0 >> 10) & 0x7fff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> StatusWriteVal { - StatusWriteVal(self.0) - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusWriteVal(u32); - impl StatusWriteVal { - /// Indicates the status of mailbox command - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RO - #[inline(always)] - pub fn status( - self, - f: impl FnOnce(super::enums::selector::MboxStatusESelector) -> super::enums::MboxStatusE, - ) -> Self { - Self( - (self.0 & !(0xf << 0)) - | (u32::from(f(super::enums::selector::MboxStatusESelector())) << 0), - ) - } - } - impl From for StatusWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct UnlockReadVal(u32); - impl UnlockReadVal { - /// - #[inline(always)] - pub fn unlock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> UnlockWriteVal { - UnlockWriteVal(self.0) - } - } - impl From for UnlockReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: UnlockReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct UnlockWriteVal(u32); - impl UnlockWriteVal { - /// - #[inline(always)] - pub fn unlock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for UnlockWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: UnlockWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum MboxFsmE { - MboxIdle = 0, - MboxRdyForCmd = 1, - MboxRdyForData = 2, - MboxRdyForDlen = 3, - MboxExecuteSoc = 4, - Reserved5 = 5, - MboxExecuteUc = 6, - MboxError = 7, - } - impl MboxFsmE { - #[inline(always)] - pub fn mbox_idle(&self) -> bool { - *self == Self::MboxIdle - } - #[inline(always)] - pub fn mbox_rdy_for_cmd(&self) -> bool { - *self == Self::MboxRdyForCmd - } - #[inline(always)] - pub fn mbox_rdy_for_data(&self) -> bool { - *self == Self::MboxRdyForData - } - #[inline(always)] - pub fn mbox_rdy_for_dlen(&self) -> bool { - *self == Self::MboxRdyForDlen - } - #[inline(always)] - pub fn mbox_execute_soc(&self) -> bool { - *self == Self::MboxExecuteSoc - } - #[inline(always)] - pub fn mbox_execute_uc(&self) -> bool { - *self == Self::MboxExecuteUc - } - #[inline(always)] - pub fn mbox_error(&self) -> bool { - *self == Self::MboxError - } - } - impl TryFrom for MboxFsmE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 8 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: MboxFsmE) -> Self { - val as u32 - } - } - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum MboxStatusE { - CmdBusy = 0, - DataReady = 1, - CmdComplete = 2, - CmdFailure = 3, - Reserved4 = 4, - Reserved5 = 5, - Reserved6 = 6, - Reserved7 = 7, - Reserved8 = 8, - Reserved9 = 9, - Reserved10 = 10, - Reserved11 = 11, - Reserved12 = 12, - Reserved13 = 13, - Reserved14 = 14, - Reserved15 = 15, - } - impl MboxStatusE { - #[inline(always)] - pub fn cmd_busy(&self) -> bool { - *self == Self::CmdBusy - } - #[inline(always)] - pub fn data_ready(&self) -> bool { - *self == Self::DataReady - } - #[inline(always)] - pub fn cmd_complete(&self) -> bool { - *self == Self::CmdComplete - } - #[inline(always)] - pub fn cmd_failure(&self) -> bool { - *self == Self::CmdFailure - } - } - impl TryFrom for MboxStatusE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 0x10 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: MboxStatusE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct MboxFsmESelector(); - impl MboxFsmESelector { - #[inline(always)] - pub fn mbox_idle(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxIdle - } - #[inline(always)] - pub fn mbox_rdy_for_cmd(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxRdyForCmd - } - #[inline(always)] - pub fn mbox_rdy_for_dlen(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxRdyForDlen - } - #[inline(always)] - pub fn mbox_rdy_for_data(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxRdyForData - } - #[inline(always)] - pub fn mbox_execute_uc(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxExecuteUc - } - #[inline(always)] - pub fn mbox_execute_soc(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxExecuteSoc - } - #[inline(always)] - pub fn mbox_error(&self) -> super::MboxFsmE { - super::MboxFsmE::MboxError - } - } - pub struct MboxStatusESelector(); - impl MboxStatusESelector { - #[inline(always)] - pub fn cmd_busy(&self) -> super::MboxStatusE { - super::MboxStatusE::CmdBusy - } - #[inline(always)] - pub fn data_ready(&self) -> super::MboxStatusE { - super::MboxStatusE::DataReady - } - #[inline(always)] - pub fn cmd_complete(&self) -> super::MboxStatusE { - super::MboxStatusE::CmdComplete - } - #[inline(always)] - pub fn cmd_failure(&self) -> super::MboxStatusE { - super::MboxStatusE::CmdFailure - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Lock = ureg::ReadOnlyReg32; - pub type User = ureg::ReadOnlyReg32; - pub type Cmd = ureg::ReadWriteReg32<0, u32, u32>; - pub type Dlen = ureg::ReadWriteReg32<0, u32, u32>; - pub type Datain = ureg::ReadWriteReg32<0, u32, u32>; - pub type Dataout = ureg::ReadWriteReg32<0, u32, u32>; - pub type Execute = ureg::ReadWriteReg32< - 0, - crate::mbox::regs::ExecuteReadVal, - crate::mbox::regs::ExecuteWriteVal, - >; - pub type Status = ureg::ReadWriteReg32< - 0, - crate::mbox::regs::StatusReadVal, - crate::mbox::regs::StatusWriteVal, - >; - pub type Unlock = ureg::ReadWriteReg32< - 0, - crate::mbox::regs::UnlockReadVal, - crate::mbox::regs::UnlockWriteVal, - >; -} diff --git a/hw/1.0/registers/src/pv.rs b/hw/1.0/registers/src/pv.rs deleted file mode 100644 index 632b8db91d..0000000000 --- a/hw/1.0/registers/src/pv.rs +++ /dev/null @@ -1,191 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct PvReg { - _priv: (), -} -impl PvReg { - pub const PTR: *mut u32 = 0x1001a000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Controls for each pcr entry - /// - /// Read value: [`pv::regs::PvctrlReadVal`]; Write value: [`pv::regs::PvctrlWriteVal`] - #[inline(always)] - pub fn pcr_ctrl(&self) -> ureg::Array<32, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Pcr Entries are read only - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn pcr_entry( - &self, - ) -> ureg::Array<32, ureg::Array<12, ureg::RegRef>> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x600 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct PvctrlReadVal(u32); - impl PvctrlReadVal { - /// Lock the PCR from being cleared - #[inline(always)] - pub fn lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Clear the data stored in this entry. Lock will prevent this clear. - #[inline(always)] - pub fn clear(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Reserved - #[inline(always)] - pub fn rsvd0(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Reserved - #[inline(always)] - pub fn rsvd1(&self) -> u32 { - (self.0 >> 3) & 0x1f - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> PvctrlWriteVal { - PvctrlWriteVal(self.0) - } - } - impl From for PvctrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: PvctrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct PvctrlWriteVal(u32); - impl PvctrlWriteVal { - /// Lock the PCR from being cleared - #[inline(always)] - pub fn lock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Clear the data stored in this entry. Lock will prevent this clear. - #[inline(always)] - pub fn clear(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Reserved - #[inline(always)] - pub fn rsvd0(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Reserved - #[inline(always)] - pub fn rsvd1(self, val: u32) -> Self { - Self((self.0 & !(0x1f << 3)) | ((val & 0x1f) << 3)) - } - } - impl From for PvctrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: PvctrlWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type PcrCtrl = - ureg::ReadWriteReg32<0, crate::pv::regs::PvctrlReadVal, crate::pv::regs::PvctrlWriteVal>; - pub type PcrEntry = ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/sha256.rs b/hw/1.0/registers/src/sha256.rs deleted file mode 100644 index 6e2cb6cbef..0000000000 --- a/hw/1.0/registers/src/sha256.rs +++ /dev/null @@ -1,1164 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct Sha256Reg { - _priv: (), -} -impl Sha256Reg { - pub const PTR: *mut u32 = 0x10028000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Two 32-bit read-only registers repereseting of the name - /// of SHA256 component. These registers are located at - /// SHA256_base_address + 0x0000_0000 and 0x0000_0004 addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn name(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Two 32-bit read-only registers repereseting of the version - /// of SHA256 component. These registers are located at - /// SHA256_base_address + 0x0000_0008 and 0x0000_000C addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn version(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 4-bit register including the following flags: - /// bit #0: INIT : Trigs the SHA256 core to start the - /// processing for the first padded message block. - /// bit #1: NEXT: ​Trigs the SHA256 core to start the - /// processing for the remining padded message block. - /// bit #2: MODE : Indicates the SHA256 core to set dynamically - /// the type of hashing algorithm. This can be: - /// 0 for SHA256/224 - /// 1 for SHA256 - /// bit #3: Zeroize all internal registers after SHA process, to avoid SCA leakage. - /// This register is located at SHA256_base_address + 0x0000_0010 - /// After each software write, hardware will erase the register. - /// - /// Read value: [`sha256::regs::CtrlReadVal`]; Write value: [`sha256::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 2-bit register including the following flags: - /// bit #0: READY : ​Indicates if the core is ready to take - /// a control command and process the block. - /// bit #1: Valid: ​Indicates if the process is done and the - /// hash value stored in DIGEST registers is valid. - /// This register is located at SHA256_base_address + 0x0000_0018. - /// - /// Read value: [`sha256::regs::StatusReadVal`]; Write value: [`sha256::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 16 32-bit registers storing the 512-bit padded input. - /// These registers are located at SHA256_base_address + - /// 0x0000_0080 to 0x0000_00BC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn block(&self) -> ureg::Array<16, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x80 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 8 32-bit registers storing the 256-bit digest output. - /// These registers are located at SHA256_base_address + - /// 0x0000_0100 to 0x0000_011C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn digest(&self) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrEnTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::NotifIntrEnTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error0_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error1_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error2_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error3_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error0_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error1_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error2_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error3_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x210 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// Control init command bit - #[inline(always)] - pub fn init(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Control next command bit - #[inline(always)] - pub fn next(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Control mode command bits - #[inline(always)] - pub fn mode(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Zeroize all internal registers - #[inline(always)] - pub fn zeroize(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Status ready bit - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Status valid bit - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTReadVal(u32); - impl GlobalIntrEnTReadVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> GlobalIntrEnTWriteVal { - GlobalIntrEnTWriteVal(self.0) - } - } - impl From for GlobalIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTWriteVal(u32); - impl GlobalIntrEnTWriteVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for GlobalIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrTReadVal(u32); - impl GlobalIntrTReadVal { - /// Interrupt Event Aggregation status bit - #[inline(always)] - pub fn agg_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for GlobalIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntrCountIncrTReadVal(u32); - impl IntrCountIncrTReadVal { - /// Pulse mirrors interrupt event occurrence - #[inline(always)] - pub fn pulse(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for IntrCountIncrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntrCountIncrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Name = ureg::ReadOnlyReg32; - pub type Version = ureg::ReadOnlyReg32; - pub type Ctrl = ureg::WriteOnlyReg32<4, crate::sha256::regs::CtrlWriteVal>; - pub type Status = ureg::ReadOnlyReg32; - pub type Block = ureg::WriteOnlyReg32<0, u32>; - pub type Digest = ureg::ReadOnlyReg32; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrEnTReadVal, - crate::sha512_acc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrEnTReadVal, - crate::sha512_acc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTReadVal, - crate::sha512_acc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTReadVal, - crate::sha512_acc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTrigTReadVal, - crate::sha512_acc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTrigTReadVal, - crate::sha512_acc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfError0IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError1IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError2IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError3IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdDoneIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError0IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError1IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError2IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError3IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdDoneIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/sha512.rs b/hw/1.0/registers/src/sha512.rs deleted file mode 100644 index 92d9f50c5b..0000000000 --- a/hw/1.0/registers/src/sha512.rs +++ /dev/null @@ -1,1617 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct Sha512Reg { - _priv: (), -} -impl Sha512Reg { - pub const PTR: *mut u32 = 0x10020000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Two 32-bit read-only registers repereseting of the name - /// of SHA512 component. These registers are located at - /// SHA512_base_address + 0x0000_0000 and 0x0000_0004 addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn name(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Two 32-bit read-only registers repereseting of the version - /// of SHA512 component. These registers are located at - /// SHA512_base_address + 0x0000_0008 and 0x0000_000C addresses. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn version(&self) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 5-bit register including the following flags: - /// bit #0: INIT : Trigs the SHA512 core to start the - /// processing for the first padded message block. - /// bit #1: NEXT: ​Trigs the SHA512 core to start the - /// processing for the remining padded message block. - /// bit #3-2: MODE : Indicates the SHA512 core to set dynamically - /// the type of hashing algorithm. This can be: - /// 00 for SHA512/224 - /// 01 for SHA512/256 - /// 10 for SHA384 - /// 11 for SHA512 - /// bit #4: Zeroize all internal registers after SHA process, to avoid SCA leakage. - /// This register is located at SHA512_base_address + 0x0000_0010 - /// After each software write, hardware will erase the register. - /// - /// Read value: [`sha512::regs::CtrlReadVal`]; Write value: [`sha512::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// One 2-bit register including the following flags: - /// bit #0: READY : ​Indicates if the core is ready to take - /// a control command and process the block. - /// bit #1: Valid: ​Indicates if the process is done and the - /// hash value stored in DIGEST registers is valid. - /// This register is located at SHA512_base_address + 0x0000_0018. - /// - /// Read value: [`sha512::regs::StatusReadVal`]; Write value: [`sha512::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 32 32-bit registers storing the 1024-bit padded input. - /// These registers are located at SHA512_base_address + - /// 0x0000_0080 to 0x0000_00FC in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn block(&self) -> ureg::Array<32, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x80 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 16 32-bit registers storing the 512-bit digest output. - /// These registers are located at SHA512_base_address + - /// 0x0000_0100 to 0x0000_013C in big-endian representation. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn digest(&self) -> ureg::Array<16, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault read access for this engine - /// - /// Read value: [`regs::KvReadCtrlRegReadVal`]; Write value: [`regs::KvReadCtrlRegWriteVal`] - #[inline(always)] - pub fn vault_rd_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x600 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn vault_rd_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x604 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Controls the Key Vault write access for this engine - /// - /// Read value: [`regs::KvWriteCtrlRegReadVal`]; Write value: [`regs::KvWriteCtrlRegWriteVal`] - #[inline(always)] - pub fn kv_wr_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x608 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the Key Vault flow status for this engine - /// - /// Read value: [`regs::KvStatusRegReadVal`]; Write value: [`regs::KvStatusRegWriteVal`] - #[inline(always)] - pub fn kv_wr_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x60c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Nonce for PCR Gen Hash Function - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn gen_pcr_hash_nonce( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x610 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Control register for PCR Gen Hash Function - /// - /// Read value: [`sha512::regs::GenPcrHashCtrlReadVal`]; Write value: [`sha512::regs::GenPcrHashCtrlWriteVal`] - #[inline(always)] - pub fn gen_pcr_hash_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x630 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Status register for PCR Gen Hash Function - /// - /// Read value: [`sha512::regs::StatusReadVal`]; Write value: [`sha512::regs::StatusWriteVal`] - #[inline(always)] - pub fn gen_pcr_hash_status( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x634 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 12 32-bit registers storing the 384-bit digest output. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn gen_pcr_hash_digest( - &self, - ) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x638 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrEnTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::NotifIntrEnTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error0_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error1_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error2_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error3_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error0_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error1_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error2_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error3_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x210 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// Control init command bit - #[inline(always)] - pub fn init(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Control next command bit - #[inline(always)] - pub fn next(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Control mode command bits - #[inline(always)] - pub fn mode(self, val: u32) -> Self { - Self((self.0 & !(3 << 2)) | ((val & 3) << 2)) - } - /// Zeroize all internal registers - #[inline(always)] - pub fn zeroize(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Indicates last iteration for keyvault or hash extend function. - /// Result of this INIT or NEXT cycle will be written back to the appropriate vault - #[inline(always)] - pub fn last(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GenPcrHashCtrlWriteVal(u32); - impl GenPcrHashCtrlWriteVal { - /// Command to start hash function - #[inline(always)] - pub fn start(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for GenPcrHashCtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GenPcrHashCtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Status ready bit - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Status valid bit - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTReadVal(u32); - impl GlobalIntrEnTReadVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> GlobalIntrEnTWriteVal { - GlobalIntrEnTWriteVal(self.0) - } - } - impl From for GlobalIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTWriteVal(u32); - impl GlobalIntrEnTWriteVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for GlobalIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrTReadVal(u32); - impl GlobalIntrTReadVal { - /// Interrupt Event Aggregation status bit - #[inline(always)] - pub fn agg_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for GlobalIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntrCountIncrTReadVal(u32); - impl IntrCountIncrTReadVal { - /// Pulse mirrors interrupt event occurrence - #[inline(always)] - pub fn pulse(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for IntrCountIncrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntrCountIncrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum KvErrorE { - Success = 0, - KvReadFail = 1, - KvWriteFail = 2, - Reserved3 = 3, - Reserved4 = 4, - Reserved5 = 5, - Reserved6 = 6, - Reserved7 = 7, - Reserved8 = 8, - Reserved9 = 9, - Reserved10 = 10, - Reserved11 = 11, - Reserved12 = 12, - Reserved13 = 13, - Reserved14 = 14, - Reserved15 = 15, - Reserved16 = 16, - Reserved17 = 17, - Reserved18 = 18, - Reserved19 = 19, - Reserved20 = 20, - Reserved21 = 21, - Reserved22 = 22, - Reserved23 = 23, - Reserved24 = 24, - Reserved25 = 25, - Reserved26 = 26, - Reserved27 = 27, - Reserved28 = 28, - Reserved29 = 29, - Reserved30 = 30, - Reserved31 = 31, - Reserved32 = 32, - Reserved33 = 33, - Reserved34 = 34, - Reserved35 = 35, - Reserved36 = 36, - Reserved37 = 37, - Reserved38 = 38, - Reserved39 = 39, - Reserved40 = 40, - Reserved41 = 41, - Reserved42 = 42, - Reserved43 = 43, - Reserved44 = 44, - Reserved45 = 45, - Reserved46 = 46, - Reserved47 = 47, - Reserved48 = 48, - Reserved49 = 49, - Reserved50 = 50, - Reserved51 = 51, - Reserved52 = 52, - Reserved53 = 53, - Reserved54 = 54, - Reserved55 = 55, - Reserved56 = 56, - Reserved57 = 57, - Reserved58 = 58, - Reserved59 = 59, - Reserved60 = 60, - Reserved61 = 61, - Reserved62 = 62, - Reserved63 = 63, - Reserved64 = 64, - Reserved65 = 65, - Reserved66 = 66, - Reserved67 = 67, - Reserved68 = 68, - Reserved69 = 69, - Reserved70 = 70, - Reserved71 = 71, - Reserved72 = 72, - Reserved73 = 73, - Reserved74 = 74, - Reserved75 = 75, - Reserved76 = 76, - Reserved77 = 77, - Reserved78 = 78, - Reserved79 = 79, - Reserved80 = 80, - Reserved81 = 81, - Reserved82 = 82, - Reserved83 = 83, - Reserved84 = 84, - Reserved85 = 85, - Reserved86 = 86, - Reserved87 = 87, - Reserved88 = 88, - Reserved89 = 89, - Reserved90 = 90, - Reserved91 = 91, - Reserved92 = 92, - Reserved93 = 93, - Reserved94 = 94, - Reserved95 = 95, - Reserved96 = 96, - Reserved97 = 97, - Reserved98 = 98, - Reserved99 = 99, - Reserved100 = 100, - Reserved101 = 101, - Reserved102 = 102, - Reserved103 = 103, - Reserved104 = 104, - Reserved105 = 105, - Reserved106 = 106, - Reserved107 = 107, - Reserved108 = 108, - Reserved109 = 109, - Reserved110 = 110, - Reserved111 = 111, - Reserved112 = 112, - Reserved113 = 113, - Reserved114 = 114, - Reserved115 = 115, - Reserved116 = 116, - Reserved117 = 117, - Reserved118 = 118, - Reserved119 = 119, - Reserved120 = 120, - Reserved121 = 121, - Reserved122 = 122, - Reserved123 = 123, - Reserved124 = 124, - Reserved125 = 125, - Reserved126 = 126, - Reserved127 = 127, - Reserved128 = 128, - Reserved129 = 129, - Reserved130 = 130, - Reserved131 = 131, - Reserved132 = 132, - Reserved133 = 133, - Reserved134 = 134, - Reserved135 = 135, - Reserved136 = 136, - Reserved137 = 137, - Reserved138 = 138, - Reserved139 = 139, - Reserved140 = 140, - Reserved141 = 141, - Reserved142 = 142, - Reserved143 = 143, - Reserved144 = 144, - Reserved145 = 145, - Reserved146 = 146, - Reserved147 = 147, - Reserved148 = 148, - Reserved149 = 149, - Reserved150 = 150, - Reserved151 = 151, - Reserved152 = 152, - Reserved153 = 153, - Reserved154 = 154, - Reserved155 = 155, - Reserved156 = 156, - Reserved157 = 157, - Reserved158 = 158, - Reserved159 = 159, - Reserved160 = 160, - Reserved161 = 161, - Reserved162 = 162, - Reserved163 = 163, - Reserved164 = 164, - Reserved165 = 165, - Reserved166 = 166, - Reserved167 = 167, - Reserved168 = 168, - Reserved169 = 169, - Reserved170 = 170, - Reserved171 = 171, - Reserved172 = 172, - Reserved173 = 173, - Reserved174 = 174, - Reserved175 = 175, - Reserved176 = 176, - Reserved177 = 177, - Reserved178 = 178, - Reserved179 = 179, - Reserved180 = 180, - Reserved181 = 181, - Reserved182 = 182, - Reserved183 = 183, - Reserved184 = 184, - Reserved185 = 185, - Reserved186 = 186, - Reserved187 = 187, - Reserved188 = 188, - Reserved189 = 189, - Reserved190 = 190, - Reserved191 = 191, - Reserved192 = 192, - Reserved193 = 193, - Reserved194 = 194, - Reserved195 = 195, - Reserved196 = 196, - Reserved197 = 197, - Reserved198 = 198, - Reserved199 = 199, - Reserved200 = 200, - Reserved201 = 201, - Reserved202 = 202, - Reserved203 = 203, - Reserved204 = 204, - Reserved205 = 205, - Reserved206 = 206, - Reserved207 = 207, - Reserved208 = 208, - Reserved209 = 209, - Reserved210 = 210, - Reserved211 = 211, - Reserved212 = 212, - Reserved213 = 213, - Reserved214 = 214, - Reserved215 = 215, - Reserved216 = 216, - Reserved217 = 217, - Reserved218 = 218, - Reserved219 = 219, - Reserved220 = 220, - Reserved221 = 221, - Reserved222 = 222, - Reserved223 = 223, - Reserved224 = 224, - Reserved225 = 225, - Reserved226 = 226, - Reserved227 = 227, - Reserved228 = 228, - Reserved229 = 229, - Reserved230 = 230, - Reserved231 = 231, - Reserved232 = 232, - Reserved233 = 233, - Reserved234 = 234, - Reserved235 = 235, - Reserved236 = 236, - Reserved237 = 237, - Reserved238 = 238, - Reserved239 = 239, - Reserved240 = 240, - Reserved241 = 241, - Reserved242 = 242, - Reserved243 = 243, - Reserved244 = 244, - Reserved245 = 245, - Reserved246 = 246, - Reserved247 = 247, - Reserved248 = 248, - Reserved249 = 249, - Reserved250 = 250, - Reserved251 = 251, - Reserved252 = 252, - Reserved253 = 253, - Reserved254 = 254, - Reserved255 = 255, - } - impl KvErrorE { - #[inline(always)] - pub fn success(&self) -> bool { - *self == Self::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> bool { - *self == Self::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> bool { - *self == Self::KvWriteFail - } - } - impl TryFrom for KvErrorE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 0x100 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: KvErrorE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct KvErrorESelector(); - impl KvErrorESelector { - #[inline(always)] - pub fn success(&self) -> super::KvErrorE { - super::KvErrorE::Success - } - #[inline(always)] - pub fn kv_read_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvReadFail - } - #[inline(always)] - pub fn kv_write_fail(&self) -> super::KvErrorE { - super::KvErrorE::KvWriteFail - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Name = ureg::ReadOnlyReg32; - pub type Version = ureg::ReadOnlyReg32; - pub type Ctrl = ureg::WriteOnlyReg32<8, crate::sha512::regs::CtrlWriteVal>; - pub type Status = ureg::ReadOnlyReg32; - pub type Block = ureg::WriteOnlyReg32<0, u32>; - pub type Digest = ureg::ReadOnlyReg32; - pub type VaultRdCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvReadCtrlRegReadVal, - crate::regs::KvReadCtrlRegWriteVal, - >; - pub type VaultRdStatus = ureg::ReadOnlyReg32; - pub type KvWrCtrl = ureg::ReadWriteReg32< - 0, - crate::regs::KvWriteCtrlRegReadVal, - crate::regs::KvWriteCtrlRegWriteVal, - >; - pub type KvWrStatus = ureg::ReadOnlyReg32; - pub type GenPcrHashNonce = ureg::WriteOnlyReg32<0, u32>; - pub type GenPcrHashCtrl = ureg::WriteOnlyReg32<0, crate::sha512::regs::GenPcrHashCtrlWriteVal>; - pub type GenPcrHashStatus = ureg::ReadOnlyReg32; - pub type GenPcrHashDigest = ureg::ReadOnlyReg32; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrEnTReadVal, - crate::sha512_acc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrEnTReadVal, - crate::sha512_acc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTReadVal, - crate::sha512_acc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTReadVal, - crate::sha512_acc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTrigTReadVal, - crate::sha512_acc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTrigTReadVal, - crate::sha512_acc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfError0IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError1IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError2IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError3IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdDoneIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError0IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError1IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError2IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError3IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdDoneIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/sha512_acc.rs b/hw/1.0/registers/src/sha512_acc.rs deleted file mode 100644 index 28d0c6deec..0000000000 --- a/hw/1.0/registers/src/sha512_acc.rs +++ /dev/null @@ -1,1475 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct Sha512AccCsr { - _priv: (), -} -impl Sha512AccCsr { - pub const PTR: *mut u32 = 0x30021000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// SHA lock register for SHA access, reading 0 will set the lock, Write 1 to clear the lock - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`sha512_acc::regs::LockReadVal`]; Write value: [`sha512_acc::regs::LockWriteVal`] - #[inline(always)] - pub fn lock(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Stores the user that locked the SHA - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn user(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Stores the requested mode for the SHA to execute. - /// SHA Supports both SHA384 and SHA512 modes of operation. - /// SHA Supports streaming mode - SHA is computed on a stream of incoming data to datain register. - /// mailbox mode - SHA is computed on LENGTH bytes of data stored in the mailbox from START_ADDRESS. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`sha512_acc::regs::ModeReadVal`]; Write value: [`sha512_acc::regs::ModeWriteVal`] - #[inline(always)] - pub fn mode(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// The start address for FW controlled SHA performed on data stored in the mailbox. - /// Start Address must be dword aligned. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn start_address(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// The length of data to be processed in bytes. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn dlen(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Data in register for SHA Streaming function - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn datain(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// For Streaming Function, indicates that the initiator is done streaming. - /// For the Mailbox SHA Function, indicates that the SHA can begin execution. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`sha512_acc::regs::ExecuteReadVal`]; Write value: [`sha512_acc::regs::ExecuteWriteVal`] - #[inline(always)] - pub fn execute(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Status register indicating when the requested function is complete - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`sha512_acc::regs::StatusReadVal`]; Write value: [`sha512_acc::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 16 32-bit registers storing the 512-bit digest output in - /// big-endian representation. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn digest(&self) -> ureg::Array<16, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// SHA Accelerator control flows. - /// [br]Zeroize the SHA engine internal registers. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`sha512_acc::regs::ControlReadVal`]; Write value: [`sha512_acc::regs::ControlWriteVal`] - #[inline(always)] - pub fn control(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x60 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrEnTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::NotifIntrEnTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::ErrorIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`sha512_acc::regs::NotifIntrTrigTReadVal`]; Write value: [`sha512_acc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error0_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error1_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error2_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error3_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error0_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error1_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error2_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error3_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_done_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x210 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct ControlReadVal(u32); - impl ControlReadVal { - /// Zeroize all internal registers - #[inline(always)] - pub fn zeroize(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ControlWriteVal { - ControlWriteVal(self.0) - } - } - impl From for ControlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ControlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ControlWriteVal(u32); - impl ControlWriteVal { - /// Zeroize all internal registers - #[inline(always)] - pub fn zeroize(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for ControlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ControlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExecuteReadVal(u32); - impl ExecuteReadVal { - /// - #[inline(always)] - pub fn execute(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ExecuteWriteVal { - ExecuteWriteVal(self.0) - } - } - impl From for ExecuteReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExecuteReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ExecuteWriteVal(u32); - impl ExecuteWriteVal { - /// - #[inline(always)] - pub fn execute(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for ExecuteWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ExecuteWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct LockReadVal(u32); - impl LockReadVal { - /// - #[inline(always)] - pub fn lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> LockWriteVal { - LockWriteVal(self.0) - } - } - impl From for LockReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: LockReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct LockWriteVal(u32); - impl LockWriteVal { - /// - #[inline(always)] - pub fn lock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for LockWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: LockWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ModeReadVal(u32); - impl ModeReadVal { - /// - #[inline(always)] - pub fn mode(&self) -> super::enums::ShaCmdE { - super::enums::ShaCmdE::try_from((self.0 >> 0) & 3).unwrap() - } - /// Default behavior assumes that data in mailbox is little endian, - /// When set to 0, data from mailbox will be swizzled from little to big endian at the byte level. - /// When set to 1, data from the mailbox will be loaded into SHA as-is. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - #[inline(always)] - pub fn endian_toggle(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ModeWriteVal { - ModeWriteVal(self.0) - } - } - impl From for ModeReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ModeReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ModeWriteVal(u32); - impl ModeWriteVal { - /// - #[inline(always)] - pub fn mode( - self, - f: impl FnOnce(super::enums::selector::ShaCmdESelector) -> super::enums::ShaCmdE, - ) -> Self { - Self( - (self.0 & !(3 << 0)) - | (u32::from(f(super::enums::selector::ShaCmdESelector())) << 0), - ) - } - /// Default behavior assumes that data in mailbox is little endian, - /// When set to 0, data from mailbox will be swizzled from little to big endian at the byte level. - /// When set to 1, data from the mailbox will be loaded into SHA as-is. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - #[inline(always)] - pub fn endian_toggle(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - } - impl From for ModeWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ModeWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Valid bit, indicating that the digest is complete - #[inline(always)] - pub fn valid(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Indicates that the current lock was acquired by the SoC - #[inline(always)] - pub fn soc_has_lock(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Event 0 - #[inline(always)] - pub fn error0_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Event 1 - #[inline(always)] - pub fn error1_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Event 2 - #[inline(always)] - pub fn error2_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Event 3 - #[inline(always)] - pub fn error3_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Interrupt Event 0 status bit - #[inline(always)] - pub fn error0_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Event 1 status bit - #[inline(always)] - pub fn error1_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Event 2 status bit - #[inline(always)] - pub fn error2_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Event 3 status bit - #[inline(always)] - pub fn error3_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn error0_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Interrupt Trigger 1 bit - #[inline(always)] - pub fn error1_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Interrupt Trigger 2 bit - #[inline(always)] - pub fn error2_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Interrupt Trigger 3 bit - #[inline(always)] - pub fn error3_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTReadVal(u32); - impl GlobalIntrEnTReadVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> GlobalIntrEnTWriteVal { - GlobalIntrEnTWriteVal(self.0) - } - } - impl From for GlobalIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrEnTWriteVal(u32); - impl GlobalIntrEnTWriteVal { - /// Global enable bit for all events of type 'Error' - #[inline(always)] - pub fn error_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Global enable bit for all events of type 'Notification' - #[inline(always)] - pub fn notif_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for GlobalIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct GlobalIntrTReadVal(u32); - impl GlobalIntrTReadVal { - /// Interrupt Event Aggregation status bit - #[inline(always)] - pub fn agg_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for GlobalIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: GlobalIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct IntrCountIncrTReadVal(u32); - impl IntrCountIncrTReadVal { - /// Pulse mirrors interrupt event occurrence - #[inline(always)] - pub fn pulse(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - } - impl From for IntrCountIncrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: IntrCountIncrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Done Interrupt - #[inline(always)] - pub fn notif_cmd_done_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Done Interrupt status bit - #[inline(always)] - pub fn notif_cmd_done_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Interrupt Trigger 0 bit - #[inline(always)] - pub fn notif_cmd_done_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum ShaCmdE { - ShaStream384 = 0, - ShaStream512 = 1, - ShaMbox384 = 2, - ShaMbox512 = 3, - } - impl ShaCmdE { - #[inline(always)] - pub fn sha_stream_384(&self) -> bool { - *self == Self::ShaStream384 - } - #[inline(always)] - pub fn sha_stream_512(&self) -> bool { - *self == Self::ShaStream512 - } - #[inline(always)] - pub fn sha_mbox_384(&self) -> bool { - *self == Self::ShaMbox384 - } - #[inline(always)] - pub fn sha_mbox_512(&self) -> bool { - *self == Self::ShaMbox512 - } - } - impl TryFrom for ShaCmdE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 4 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: ShaCmdE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct ShaCmdESelector(); - impl ShaCmdESelector { - #[inline(always)] - pub fn sha_stream_384(&self) -> super::ShaCmdE { - super::ShaCmdE::ShaStream384 - } - #[inline(always)] - pub fn sha_stream_512(&self) -> super::ShaCmdE { - super::ShaCmdE::ShaStream512 - } - #[inline(always)] - pub fn sha_mbox_384(&self) -> super::ShaCmdE { - super::ShaCmdE::ShaMbox384 - } - #[inline(always)] - pub fn sha_mbox_512(&self) -> super::ShaCmdE { - super::ShaCmdE::ShaMbox512 - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type Lock = ureg::ReadWriteReg32< - 1, - crate::sha512_acc::regs::LockReadVal, - crate::sha512_acc::regs::LockWriteVal, - >; - pub type User = ureg::ReadOnlyReg32; - pub type Mode = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ModeReadVal, - crate::sha512_acc::regs::ModeWriteVal, - >; - pub type StartAddress = ureg::ReadWriteReg32<0, u32, u32>; - pub type Dlen = ureg::ReadWriteReg32<0, u32, u32>; - pub type Datain = ureg::ReadWriteReg32<0, u32, u32>; - pub type Execute = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ExecuteReadVal, - crate::sha512_acc::regs::ExecuteWriteVal, - >; - pub type Status = ureg::ReadOnlyReg32; - pub type Digest = ureg::ReadOnlyReg32; - pub type Control = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ControlReadVal, - crate::sha512_acc::regs::ControlWriteVal, - >; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrEnTReadVal, - crate::sha512_acc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrEnTReadVal, - crate::sha512_acc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTReadVal, - crate::sha512_acc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTReadVal, - crate::sha512_acc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::ErrorIntrTrigTReadVal, - crate::sha512_acc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::NotifIntrTrigTReadVal, - crate::sha512_acc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfError0IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError1IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError2IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError3IntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdDoneIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfError0IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError1IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError2IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfError3IntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdDoneIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/soc_ifc.rs b/hw/1.0/registers/src/soc_ifc.rs deleted file mode 100644 index 31736904e6..0000000000 --- a/hw/1.0/registers/src/soc_ifc.rs +++ /dev/null @@ -1,4400 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct SocIfcReg { - _priv: (), -} -impl SocIfcReg { - pub const PTR: *mut u32 = 0x30030000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Indicates fatal hardware error. Assertion of any bit in this - /// register results in the assertion of the SoC interrupt pin, - /// cptra_error_fatal, unless that bit is masked using the internal - /// mask register. After the output interrupt is asserted, clearing - /// the bit in this register will not cause the interrupt to deassert. - /// Only a Caliptra reset will clear the fatal error interrupt. - /// [br]Caliptra Access: RW1C - /// [br]SOC Access: RW1C - /// - /// Read value: [`soc_ifc::regs::CptraHwErrorFatalReadVal`]; Write value: [`soc_ifc::regs::CptraHwErrorFatalWriteVal`] - #[inline(always)] - pub fn cptra_hw_error_fatal( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Indicates non-fatal hardware error. Assertion of any bit in this - /// register results in the assertion of the SoC interrupt pin, - /// cptra_error_non_fatal, unless that bit is masked using the internal - /// mask register. After the output interrupt is asserted, any - /// change by firmware that results in all set non-fatal errors - /// being masked will immediately deassert the interrupt output. This means - /// that firmware may cause the cptra_error_non_fatal signal to deassert by - /// writing to any of these registers, if the write results in all error - /// bits being cleared or masked: - /// [br][list] - /// [br] [*] CPTRA_HW_ERROR_NON_FATAL - /// [br] [*] CPTRA_FW_ERROR_NON_FATAL - /// [br] [*] internal_hw_error_non_fatal_mask - /// [br] [*] internal_fw_error_non_fatal_mask - /// [/list] - /// [br]Caliptra Access: RW1C - /// [br]SOC Access: RW1C - /// - /// Read value: [`soc_ifc::regs::CptraHwErrorNonFatalReadVal`]; Write value: [`soc_ifc::regs::CptraHwErrorNonFatalWriteVal`] - #[inline(always)] - pub fn cptra_hw_error_non_fatal( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Indicates fatal firmware error. Assertion of any bit in this - /// register results in the assertion of the SoC interrupt pin, - /// cptra_error_fatal, unless that bit is masked using the internal - /// mask register. After the output interrupt is asserted, clearing - /// the bit in this register will not cause the interrupt to deassert. - /// Only a Caliptra reset will clear the fatal error interrupt. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_fw_error_fatal( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Indicates non-fatal firmware error. Assertion of any bit in this - /// register results in the assertion of the SoC interrupt pin, - /// cptra_error_non_fatal, unless that bit is masked using the internal - /// mask register. After the output interrupt is asserted, any - /// change by firmware that results in all set non-fatal errors - /// being masked will immediately deassert the interrupt output. This means - /// that firmware may cause the cptra_error_non_fatal signal to deassert by - /// writing to any of these registers, if the write results in all error - /// bits being cleared or masked: - /// [br][list] - /// [br] [*] CPTRA_HW_ERROR_NON_FATAL - /// [br] [*] CPTRA_FW_ERROR_NON_FATAL - /// [br] [*] internal_hw_error_non_fatal_mask - /// [br] [*] internal_fw_error_non_fatal_mask - /// [/list] - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_fw_error_non_fatal( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Encoded error value for hardware errors. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_hw_error_enc( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Encoded error value for firmware errors. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_fw_error_enc( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Firmware Extended Error information for firmware errors. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_fw_extended_error_info( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the boot status. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// [br]TAP Access [in debug/manuf mode]: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_boot_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x38 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Reports the status of the firmware flows. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraFlowStatusReadVal`]; Write value: [`soc_ifc::regs::CptraFlowStatusWriteVal`] - #[inline(always)] - pub fn cptra_flow_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x3c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Indicates to ROM the originating cause for the PC to be reset to 0. - /// Only reset during cold-boot (sticky). - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraResetReasonReadVal`]; Write value: [`soc_ifc::regs::CptraResetReasonWriteVal`] - #[inline(always)] - pub fn cptra_reset_reason( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x40 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Indicates current hardware security state. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraSecurityStateReadVal`]; Write value: [`soc_ifc::regs::CptraSecurityStateWriteVal`] - #[inline(always)] - pub fn cptra_security_state( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x44 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Valid PAUSER attributes for requests from SoC APB Interface. Only valid once LOCK is set. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// Read-Only once locked by PAUSER_LOCK. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_mbox_valid_pauser( - &self, - ) -> ureg::Array<5, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x48 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Valid PAUSER attributes for requests from SoC APB Interface. - /// [br]Each bit corresponds to locking the associated MBOX_VALID_PAUSER register. - /// [br]Associated MBOX_VALID_PAUSER register is only valid once locked by this bit. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]Read-Only once locked. - /// - /// Read value: [`soc_ifc::regs::CptraXxxxPauserLockReadVal`]; Write value: [`soc_ifc::regs::CptraXxxxPauserLockWriteVal`] - #[inline(always)] - pub fn cptra_mbox_pauser_lock( - &self, - ) -> ureg::Array<5, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x5c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Valid PAUSER attributes for TRNG on SoC APB Interface. Only valid once LOCK is set. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]Read-Only once locked by TRNG_PAUSER_LOCK. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_trng_valid_pauser( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x70 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Valid PAUSER attributes for requests from SoC APB Interface. - /// [br]Each bit corresponds to locking the associated TRNG_VALID_PAUSER register. - /// [br]Associated TRNG_VALID_PAUSER register is only valid once locked by this bit. - /// [br]Caliptra FW RW access for survivability but cannot unlock once locked - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]Read-Only once locked. - /// - /// Read value: [`soc_ifc::regs::CptraXxxxPauserLockReadVal`]; Write value: [`soc_ifc::regs::CptraXxxxPauserLockWriteVal`] - #[inline(always)] - pub fn cptra_trng_pauser_lock( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x74 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// TRNG Control register to clear data registers - /// - /// Read value: [`soc_ifc::regs::CptraTrngCtrlReadVal`]; Write value: [`soc_ifc::regs::CptraTrngCtrlWriteVal`] - #[inline(always)] - pub fn cptra_trng_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xa8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Writes to fuse registers are completed. After the done bit is set, any subsequent writes to a fuse register will be dropped unless there is a power cycle or a warm reset or caliptra FW allows a write (negotiated through a mailbox command). - /// [br]Caliptra Access: RO - /// [br]SOC Access: RW1-S - /// - /// Read value: [`soc_ifc::regs::CptraFuseWrDoneReadVal`]; Write value: [`soc_ifc::regs::CptraFuseWrDoneWriteVal`] - #[inline(always)] - pub fn cptra_fuse_wr_done( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xb0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides the clock period of the system clock. - /// Used to standardize the RISC-V Standard MTIME count register. - /// Clock Period is indicated as an integer number of picoseconds. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_timer_config( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xb4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Indicates that the BootFSM can continue to execute to bring the uController out of reset - /// [br]Caliptra Access: RO - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RW - /// - /// Read value: [`soc_ifc::regs::CptraBootfsmGoReadVal`]; Write value: [`soc_ifc::regs::CptraBootfsmGoWriteVal`] - #[inline(always)] - pub fn cptra_bootfsm_go(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xb8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// JTAG in debug/manuf mode or SOC can write to this register for ROM/FW defined skips or services; ROM/FW maintains the defintion of these bits. - /// [br] - /// [br]Field decode: - /// [br] [lb]0[rb] MFG_FLAG_GEN_IDEV_CSR: Enable bit for Caliptra to generate an IDEV CSR - /// [br] [lb]1[rb] MFG_FLAG_RNG_UNAVAIL: Random Number Generator Unavailable - /// [br] [lb]15:2[rb] MFG_FLAG_RSVD - /// [br] [lb]30:16[rb] FAKE_ROM_RSVD - /// [br] [lb]31[rb] FAKE_ROM_IMAGE_VERIFY_EN: Enable bit to perform image verification within the fake-rom feature - /// [br] - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]TAP Access [in debug/manuf mode]: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_dbg_manuf_service_reg( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xbc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Control register to enable or disable all of the caliptra clk gating. Default is 0 (disabled). - /// [br]Caliptra Access: RO - /// [br]SOC Access: RW - /// - /// Read value: [`soc_ifc::regs::CptraClkGatingEnReadVal`]; Write value: [`soc_ifc::regs::CptraClkGatingEnWriteVal`] - #[inline(always)] - pub fn cptra_clk_gating_en( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Generic input wires connected to SoC interface. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_generic_input_wires( - &self, - ) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0xc4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Generic output wires connected to SoC interface. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_generic_output_wires( - &self, - ) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0xcc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra HW revision ID that matches the official final release milestone - /// SoC stepping ID is repopulated with the value in the fuse register on every warm reset - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraHwRevIdReadVal`]; Write value: [`soc_ifc::regs::CptraHwRevIdWriteVal`] - #[inline(always)] - pub fn cptra_hw_rev_id(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xd4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra FW revision ID - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_fw_rev_id( - &self, - ) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0xd8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra HW Configuration - /// [br]Caliptra Access: RO - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraHwConfigReadVal`]; Write value: [`soc_ifc::regs::CptraHwConfigWriteVal`] - #[inline(always)] - pub fn cptra_hw_config(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xe0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer1 enable register - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraWdtTimer1EnReadVal`]; Write value: [`soc_ifc::regs::CptraWdtTimer1EnWriteVal`] - #[inline(always)] - pub fn cptra_wdt_timer1_en( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xe4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer1 control register - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraWdtTimer1CtrlReadVal`]; Write value: [`soc_ifc::regs::CptraWdtTimer1CtrlWriteVal`] - #[inline(always)] - pub fn cptra_wdt_timer1_ctrl( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xe8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer1 timeout register - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_wdt_timer1_timeout_period( - &self, - ) -> ureg::Array<2, ureg::RegRef> - { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0xec / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer2 enable register. Note: Setting this to 1 will disable the default cascaded mode and will have both timers count independently. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraWdtTimer2EnReadVal`]; Write value: [`soc_ifc::regs::CptraWdtTimer2EnWriteVal`] - #[inline(always)] - pub fn cptra_wdt_timer2_en( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xf4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer2 control register - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraWdtTimer2CtrlReadVal`]; Write value: [`soc_ifc::regs::CptraWdtTimer2CtrlWriteVal`] - #[inline(always)] - pub fn cptra_wdt_timer2_ctrl( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xf8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer2 timeout register - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_wdt_timer2_timeout_period( - &self, - ) -> ureg::Array<2, ureg::RegRef> - { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0xfc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra watchdog timer status register - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::CptraWdtStatusReadVal`]; Write value: [`soc_ifc::regs::CptraWdtStatusWriteVal`] - #[inline(always)] - pub fn cptra_wdt_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Valid PAUSER attributes for FUSE on SoC APB Interface. Only valid once LOCK is set. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]Read-Only once locked by FUSE_PAUSER_LOCK. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_fuse_valid_pauser( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Valid PAUSER attributes for requests from SoC APB Interface. - /// [br]Each bit corresponds to locking the associated FUSE_VALID_PAUSER register. - /// [br]Associated FUSE_VALID_PAUSER register is only valid once locked by this bit. - /// [br]Caliptra FW RW access for survivability but cannot unlock once locked - /// [br]Caliptra Access: RW - /// [br]SOC Access: RW - /// [br]Read-Only once locked. - /// - /// Read value: [`soc_ifc::regs::CptraXxxxPauserLockReadVal`]; Write value: [`soc_ifc::regs::CptraXxxxPauserLockWriteVal`] - #[inline(always)] - pub fn cptra_fuse_pauser_lock( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// SOC provided count in cycles for WDT1 timeout. - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_wdt_cfg( - &self, - ) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x110 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Adaptive threshold values for entropy source health tests. - /// - /// Read value: [`soc_ifc::regs::CptraItrngEntropyConfig0ReadVal`]; Write value: [`soc_ifc::regs::CptraItrngEntropyConfig0WriteVal`] - #[inline(always)] - pub fn cptra_i_trng_entropy_config_0( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x118 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Repetition count value for entropy source health tests. - /// - /// Read value: [`soc_ifc::regs::CptraItrngEntropyConfig1ReadVal`]; Write value: [`soc_ifc::regs::CptraItrngEntropyConfig1WriteVal`] - #[inline(always)] - pub fn cptra_i_trng_entropy_config_1( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x11c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Set of reserved registers for survivability - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_rsvd_reg( - &self, - ) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x120 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Obfuscated UDS. - /// [br]Caliptra Access: - - /// [br]SOC Access: WL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_uds_seed( - &self, - ) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Obfuscated Field Entropy. - /// [br]Caliptra Access: - - /// [br]SOC Access: WL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_field_entropy( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x230 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Key Manifest PK hash Fuse. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_key_manifest_pk_hash( - &self, - ) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x250 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Key Manifest Mask Fuse. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`soc_ifc::regs::FuseKeyManifestPkHashMaskReadVal`]; Write value: [`soc_ifc::regs::FuseKeyManifestPkHashMaskWriteVal`] - #[inline(always)] - pub fn fuse_key_manifest_pk_hash_mask( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x280 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Owner PK hash Fuse. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_owner_pk_hash( - &self, - ) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x284 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// FMC Security Version Number. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_fmc_key_manifest_svn( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x2b4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Runtime SVN Fuse. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_runtime_svn( - &self, - ) -> ureg::Array<4, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x2b8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Anti Rollback Disable Fuse. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`soc_ifc::regs::FuseAntiRollbackDisableReadVal`]; Write value: [`soc_ifc::regs::FuseAntiRollbackDisableWriteVal`] - #[inline(always)] - pub fn fuse_anti_rollback_disable( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x2c8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Manufacturer IEEE IDevID Certificate Gen Attributes. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_idevid_cert_attr( - &self, - ) -> ureg::Array<24, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x2cc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Manufacturer IDEVID Manufacturer’s HSM identifier (this is used to find the certificate chain from the boot media) - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_idevid_manuf_hsm_id( - &self, - ) -> ureg::Array<4, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x32c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Caliptra Boot Media Integrated mode usage only. SOCs that build with a Boot Media Independent profile don’t have to account for these fuses. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`soc_ifc::regs::FuseLifeCycleReadVal`]; Write value: [`soc_ifc::regs::FuseLifeCycleWriteVal`] - #[inline(always)] - pub fn fuse_life_cycle(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x33c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 0 - Verify Caliptra firmware images with ECDSA-only; 1 - Verify Caliptra firmware images with both ECDSA and LMS - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`soc_ifc::regs::FuseLmsVerifyReadVal`]; Write value: [`soc_ifc::regs::FuseLmsVerifyWriteVal`] - #[inline(always)] - pub fn fuse_lms_verify(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x340 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Bits for revoking LMS public keys in the key manifest - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn fuse_lms_revocation( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x344 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// SOC stepping ID - /// [br]Caliptra Access: RO - /// [br]SOC Access: RWL-S - /// - /// Read value: [`soc_ifc::regs::FuseSocSteppingIdReadVal`]; Write value: [`soc_ifc::regs::FuseSocSteppingIdWriteVal`] - #[inline(always)] - pub fn fuse_soc_stepping_id( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x348 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Stored De-Obfuscation key, not accessible by software. - /// [br]Caliptra Access: - - /// [br]SOC Access: - - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_obf_key( - &self, - ) -> ureg::Array<8, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x600 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Lock feature gates writes to the ICCM. When lock is set to - /// 1, writes are blocked. When cleared to 0, writes allowed. - /// Write-once, meaning only a reset can clear it once set to 1. - /// [br]Caliptra Access: RW1 - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::InternalIccmLockReadVal`]; Write value: [`soc_ifc::regs::InternalIccmLockWriteVal`] - #[inline(always)] - pub fn internal_iccm_lock( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x620 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Control register to assert FW update reset. When cleared to - /// 0, no reset is triggered. When set to 1, uc-only reset is asserted. - /// Field automatically clears 1 cycle after being set. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::InternalFwUpdateResetReadVal`]; Write value: [`soc_ifc::regs::InternalFwUpdateResetWriteVal`] - #[inline(always)] - pub fn internal_fw_update_reset( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x624 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Control register to set the number of cycles for which FW update reset must be asserted. Default is 5. Max value is 255 (8 bit). - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::InternalFwUpdateResetWaitCyclesReadVal`]; Write value: [`soc_ifc::regs::InternalFwUpdateResetWaitCyclesWriteVal`] - #[inline(always)] - pub fn internal_fw_update_reset_wait_cycles( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x628 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// 32-bit register providing the jump vector for RISC-V to transition for NMI handling code. - /// Default is the base address of ROM, but may be updated for enhanced handling by runtime images. - /// Bit [0] is ignored to enforce half-word alignment of address. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_nmi_vector( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x62c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Bit mask for the register CPTRA_HW_ERROR_FATAL to determine - /// which bits are disabled for interrupt generation on the - /// cptra_error_fatal output signal. - /// [br]A value of 1 in a field of this register means the corresponding bit - /// position in CPTRA_HW_ERROR_FATAL will not produce an interrupt - /// output assertion. If a hardware error bit is set and was previously - /// masked, and firmware performs a write to clear the corresponding mask - /// bit in this register, the interrupt output will not be asserted. Only - /// the same error condition reoccurring while it is unmasked will cause - /// a new assertion of the interrupt output. - /// [br]Firmware can not cause the interrupt output to deassert by setting - /// mask bits for fatal error conditions that have already triggered the - /// interrupt. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::InternalHwErrorFatalMaskReadVal`]; Write value: [`soc_ifc::regs::InternalHwErrorFatalMaskWriteVal`] - #[inline(always)] - pub fn internal_hw_error_fatal_mask( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x630 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Bit mask for the register CPTRA_HW_ERROR_NON_FATAL to determine - /// which bits are disabled for interrupt generation on the - /// cptra_error_non_fatal output signal. - /// [br]A value of 1 in a field of this register means the corresponding bit - /// position in CPTRA_HW_ERROR_NON_FATAL will not produce an interrupt - /// output assertion. If a hardware error bit is set that was previously - /// masked, and firmware performs a write to clear the corresponding mask - /// bit in this register, the interrupt output will not be asserted. Only - /// the same error condition reoccurring while it is unmasked will cause - /// a new assertion of the interrupt output. - /// [br]Any change by firmware that results in all set non-fatal errors - /// being masked will immediately deassert the interrupt output. This means - /// that firmware may cause the cptra_error_non_fatal signal to deassert by - /// writing to any of these registers, if the write results in all error - /// bits being cleared or masked: - /// [br][list] - /// [br] [*] CPTRA_HW_ERROR_NON_FATAL - /// [br] [*] CPTRA_FW_ERROR_NON_FATAL - /// [br] [*] internal_hw_error_non_fatal_mask - /// [br] [*] internal_fw_error_non_fatal_mask - /// [/list] - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`soc_ifc::regs::InternalHwErrorNonFatalMaskReadVal`]; Write value: [`soc_ifc::regs::InternalHwErrorNonFatalMaskWriteVal`] - #[inline(always)] - pub fn internal_hw_error_non_fatal_mask( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x634 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Bit mask for the register CPTRA_FW_ERROR_FATAL to determine - /// which bits are disabled for interrupt generation on the - /// cptra_error_fatal output signal. - /// [br]A value of 1 in a field of this register means the corresponding bit - /// position in CPTRA_FW_ERROR_FATAL will not produce an interrupt - /// output assertion. If a firmware error bit is set and was previously - /// masked, and firmware performs a write to clear the corresponding mask - /// bit in this register, the interrupt output will not be asserted. Only - /// the same error bit being cleared then set again while it is unmasked will cause - /// a new assertion of the interrupt output. - /// [br]Firmware can not cause the interrupt output to deassert by setting - /// mask bits for fatal error conditions that have already triggered the - /// interrupt. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_fw_error_fatal_mask( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x638 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Bit mask for the register CPTRA_FW_ERROR_NON_FATAL to determine - /// which bits are disabled for interrupt generation on the - /// cptra_error_non_fatal output signal. - /// [br]A value of 1 in a field of this register means the corresponding bit - /// position in CPTRA_FW_ERROR_NON_FATAL will not produce an interrupt - /// output assertion. If a firmware error bit is set that was previously - /// masked, and firmware performs a write to clear the corresponding mask - /// bit in this register, the interrupt output will not be asserted. Only - /// the same error bit being cleared then set again while it is unmasked will cause - /// a new assertion of the interrupt output. - /// [br]Any change by firmware that results in all set non-fatal errors - /// being masked will immediately deassert the interrupt output. This means - /// that firmware may cause the cptra_error_non_fatal signal to deassert by - /// writing to any of these registers, if the write results in all error - /// bits being cleared or masked: - /// [br][list] - /// [br] [*] CPTRA_HW_ERROR_NON_FATAL - /// [br] [*] CPTRA_FW_ERROR_NON_FATAL - /// [br] [*] internal_hw_error_non_fatal_mask - /// [br] [*] internal_fw_error_non_fatal_mask - /// [/list] - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_fw_error_non_fatal_mask( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x63c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// RISC-V Standard Machine-mode Time Counter, lower 32-bits. - /// [br]Frequency of counter is indicated in CPTRA_TIMER_CONFIG.clk_period. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_rv_mtime_l( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x640 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// RISC-V Standard Machine-mode Time Counter, upper 32-bits. - /// [br]Frequency of counter is indicated in CPTRA_TIMER_CONFIG.clk_period. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_rv_mtime_h( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x644 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// RISC-V Standard Machine-mode Time Counter Compare Value, lower 32-bits. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_rv_mtimecmp_l( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x648 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// RISC-V Standard Machine-mode Time Counter Compare Value, upper 32-bits. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn internal_rv_mtimecmp_h( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x64c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - #[inline(always)] - pub fn intr_block_rf(&self) -> IntrBlockRfBlock<&TMmio> { - IntrBlockRfBlock { - ptr: unsafe { self.ptr.add(0x800 / core::mem::size_of::()) }, - mmio: core::borrow::Borrow::borrow(&self.mmio), - } - } -} -#[derive(Clone, Copy)] -pub struct IntrBlockRfBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl IntrBlockRfBlock { - /// Dedicated register with one bit for each event type that may produce an interrupt. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrEnTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrEnTWriteVal`] - #[inline(always)] - pub fn global_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`soc_ifc::regs::ErrorIntrEnTReadVal`]; Write value: [`soc_ifc::regs::ErrorIntrEnTWriteVal`] - #[inline(always)] - pub fn error_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Dedicated register with one bit for each event that may produce an interrupt. - /// - /// Read value: [`soc_ifc::regs::NotifIntrEnTReadVal`]; Write value: [`soc_ifc::regs::NotifIntrEnTWriteVal`] - #[inline(always)] - pub fn notif_intr_en_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn error_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of any interrupt event - /// of a given type. E.g. Notifications and Errors may drive - /// to two separate interrupt registers. There may be - /// multiple sources of Notifications or Errors that are - /// aggregated into a single interrupt pin for that - /// respective type. That pin feeds through this register - /// in order to apply a global enablement of that interrupt - /// event type. - /// Nonsticky assertion. - /// - /// Read value: [`sha512_acc::regs::GlobalIntrTReadVal`]; Write value: [`sha512_acc::regs::GlobalIntrTWriteVal`] - #[inline(always)] - pub fn notif_global_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`soc_ifc::regs::ErrorIntrTReadVal`]; Write value: [`soc_ifc::regs::ErrorIntrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit indicating occurrence of each interrupt event. - /// Sticky, level assertion, write-1-to-clear. - /// - /// Read value: [`soc_ifc::regs::NotifIntrTReadVal`]; Write value: [`soc_ifc::regs::NotifIntrTWriteVal`] - #[inline(always)] - pub fn notif_internal_intr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`soc_ifc::regs::ErrorIntrTrigTReadVal`]; Write value: [`soc_ifc::regs::ErrorIntrTrigTWriteVal`] - #[inline(always)] - pub fn error_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Single bit for each interrupt event allows SW to manually - /// trigger occurrence of that event. Upon SW write, the trigger bit - /// will pulse for 1 cycle then clear to 0. The pulse on the - /// trigger register bit results in the corresponding interrupt - /// status bit being set to 1. - /// - /// Read value: [`soc_ifc::regs::NotifIntrTrigTReadVal`]; Write value: [`soc_ifc::regs::NotifIntrTrigTWriteVal`] - #[inline(always)] - pub fn notif_intr_trig_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_internal_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x100 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_inv_dev_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x104 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_cmd_fail_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x108 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_bad_fuse_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_iccm_blocked_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x110 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_mbox_ecc_unc_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x114 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_wdt_timer1_timeout_intr_count_r( - &self, - ) -> ureg::RegRef - { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x118 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn error_wdt_timer2_timeout_intr_count_r( - &self, - ) -> ureg::RegRef - { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x11c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_cmd_avail_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x180 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_mbox_ecc_cor_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x184 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_debug_locked_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x188 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_scan_mode_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_soc_req_lock_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x190 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Provides statistics about the number of events that have - /// occurred. - /// Will not overflow ('incrsaturate'). - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn notif_gen_in_toggle_intr_count_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x194 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_internal_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x200 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_inv_dev_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x204 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_cmd_fail_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x208 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_bad_fuse_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_iccm_blocked_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x210 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_mbox_ecc_unc_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x214 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_wdt_timer1_timeout_intr_count_incr_r( - &self, - ) -> ureg::RegRef - { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x218 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn error_wdt_timer2_timeout_intr_count_incr_r( - &self, - ) -> ureg::RegRef - { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x21c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_cmd_avail_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x220 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_mbox_ecc_cor_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x224 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_debug_locked_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x228 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_scan_mode_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x22c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_soc_req_lock_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x230 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Trigger the event counter to increment based on observing - /// the rising edge of an interrupt event input from the - /// Hardware. The same input signal that causes an interrupt - /// event to be set (sticky) also causes this signal to pulse - /// for 1 clock cycle, resulting in the event counter - /// incrementing by 1 for every interrupt event. - /// This is implemented as a down-counter (1-bit) that will - /// decrement immediately on being set - resulting in a pulse - /// - /// Read value: [`sha512_acc::regs::IntrCountIncrTReadVal`]; Write value: [`sha512_acc::regs::IntrCountIncrTWriteVal`] - #[inline(always)] - pub fn notif_gen_in_toggle_intr_count_incr_r( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x234 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct IntrBlockRf { - _priv: (), -} -impl IntrBlockRf { - pub const PTR: *mut u32 = 0x800 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CptraBootfsmGoReadVal(u32); - impl CptraBootfsmGoReadVal { - /// - #[inline(always)] - pub fn go(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraBootfsmGoWriteVal { - CptraBootfsmGoWriteVal(self.0) - } - } - impl From for CptraBootfsmGoReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraBootfsmGoReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraBootfsmGoWriteVal(u32); - impl CptraBootfsmGoWriteVal { - /// - #[inline(always)] - pub fn go(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraBootfsmGoWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraBootfsmGoWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraClkGatingEnReadVal(u32); - impl CptraClkGatingEnReadVal { - /// Clk gating enable - #[inline(always)] - pub fn clk_gating_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraClkGatingEnWriteVal { - CptraClkGatingEnWriteVal(self.0) - } - } - impl From for CptraClkGatingEnReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraClkGatingEnReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraClkGatingEnWriteVal(u32); - impl CptraClkGatingEnWriteVal { - /// Clk gating enable - #[inline(always)] - pub fn clk_gating_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraClkGatingEnWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraClkGatingEnWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraFlowStatusReadVal(u32); - impl CptraFlowStatusReadVal { - /// - #[inline(always)] - pub fn status(&self) -> u32 { - (self.0 >> 0) & 0xffffff - } - /// DEV ID CSR ready - #[inline(always)] - pub fn idevid_csr_ready(&self) -> bool { - ((self.0 >> 24) & 1) != 0 - } - /// Boot FSM State - #[inline(always)] - pub fn boot_fsm_ps(&self) -> u32 { - (self.0 >> 25) & 7 - } - /// Indicates Caliptra is ready for Firmware Download - #[inline(always)] - pub fn ready_for_fw(&self) -> bool { - ((self.0 >> 28) & 1) != 0 - } - /// Indicates Caliptra is ready for RT flows - #[inline(always)] - pub fn ready_for_runtime(&self) -> bool { - ((self.0 >> 29) & 1) != 0 - } - /// Indicates Caliptra is ready for Fuses to be programmed. - /// Read-only to both Caliptra and SOC. - #[inline(always)] - pub fn ready_for_fuses(&self) -> bool { - ((self.0 >> 30) & 1) != 0 - } - /// Indicates Caliptra is has completed Mailbox Flow. - #[inline(always)] - pub fn mailbox_flow_done(&self) -> bool { - ((self.0 >> 31) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraFlowStatusWriteVal { - CptraFlowStatusWriteVal(self.0) - } - } - impl From for CptraFlowStatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraFlowStatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraFlowStatusWriteVal(u32); - impl CptraFlowStatusWriteVal { - /// - #[inline(always)] - pub fn status(self, val: u32) -> Self { - Self((self.0 & !(0xffffff << 0)) | ((val & 0xffffff) << 0)) - } - /// DEV ID CSR ready - #[inline(always)] - pub fn idevid_csr_ready(self, val: bool) -> Self { - Self((self.0 & !(1 << 24)) | (u32::from(val) << 24)) - } - /// Indicates Caliptra is ready for Firmware Download - #[inline(always)] - pub fn ready_for_fw(self, val: bool) -> Self { - Self((self.0 & !(1 << 28)) | (u32::from(val) << 28)) - } - /// Indicates Caliptra is ready for RT flows - #[inline(always)] - pub fn ready_for_runtime(self, val: bool) -> Self { - Self((self.0 & !(1 << 29)) | (u32::from(val) << 29)) - } - /// Indicates Caliptra is has completed Mailbox Flow. - #[inline(always)] - pub fn mailbox_flow_done(self, val: bool) -> Self { - Self((self.0 & !(1 << 31)) | (u32::from(val) << 31)) - } - } - impl From for CptraFlowStatusWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraFlowStatusWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraFuseWrDoneReadVal(u32); - impl CptraFuseWrDoneReadVal { - /// - #[inline(always)] - pub fn done(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraFuseWrDoneWriteVal { - CptraFuseWrDoneWriteVal(self.0) - } - } - impl From for CptraFuseWrDoneReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraFuseWrDoneReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraFuseWrDoneWriteVal(u32); - impl CptraFuseWrDoneWriteVal { - /// - #[inline(always)] - pub fn done(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraFuseWrDoneWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraFuseWrDoneWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraHwConfigReadVal(u32); - impl CptraHwConfigReadVal { - /// - #[inline(always)] - pub fn i_trng_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// - #[inline(always)] - pub fn qspi_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// - #[inline(always)] - pub fn i3_c_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// - #[inline(always)] - pub fn uart_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - } - impl From for CptraHwConfigReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraHwConfigReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraHwErrorFatalReadVal(u32); - impl CptraHwErrorFatalReadVal { - /// - #[inline(always)] - pub fn iccm_ecc_unc(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// - #[inline(always)] - pub fn dccm_ecc_unc(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// - #[inline(always)] - pub fn nmi_pin(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraHwErrorFatalWriteVal { - CptraHwErrorFatalWriteVal(self.0) - } - } - impl From for CptraHwErrorFatalReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraHwErrorFatalReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraHwErrorFatalWriteVal(u32); - impl CptraHwErrorFatalWriteVal { - /// - #[inline(always)] - pub fn iccm_ecc_unc(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// - #[inline(always)] - pub fn dccm_ecc_unc(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// - #[inline(always)] - pub fn nmi_pin(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - } - impl From for CptraHwErrorFatalWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraHwErrorFatalWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraHwErrorNonFatalReadVal(u32); - impl CptraHwErrorNonFatalReadVal { - /// - #[inline(always)] - pub fn mbox_prot_no_lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// - #[inline(always)] - pub fn mbox_prot_ooo(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// - #[inline(always)] - pub fn mbox_ecc_unc(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraHwErrorNonFatalWriteVal { - CptraHwErrorNonFatalWriteVal(self.0) - } - } - impl From for CptraHwErrorNonFatalReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraHwErrorNonFatalReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraHwErrorNonFatalWriteVal(u32); - impl CptraHwErrorNonFatalWriteVal { - /// - #[inline(always)] - pub fn mbox_prot_no_lock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// - #[inline(always)] - pub fn mbox_prot_ooo(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// - #[inline(always)] - pub fn mbox_ecc_unc(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - } - impl From for CptraHwErrorNonFatalWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraHwErrorNonFatalWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraHwRevIdReadVal(u32); - impl CptraHwRevIdReadVal { - /// - #[inline(always)] - pub fn cptra_generation(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// - #[inline(always)] - pub fn soc_stepping_id(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - } - impl From for CptraHwRevIdReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraHwRevIdReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraResetReasonReadVal(u32); - impl CptraResetReasonReadVal { - /// FW update reset has been executed - #[inline(always)] - pub fn fw_upd_reset(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// warm reset has been executed - #[inline(always)] - pub fn warm_reset(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - } - impl From for CptraResetReasonReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraResetReasonReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraSecurityStateReadVal(u32); - impl CptraSecurityStateReadVal { - /// Device Lifecycle - #[inline(always)] - pub fn device_lifecycle(&self) -> super::enums::DeviceLifecycleE { - super::enums::DeviceLifecycleE::try_from((self.0 >> 0) & 3).unwrap() - } - /// Debug Locked - #[inline(always)] - pub fn debug_locked(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// scan mode signal observed at caliptra interface - only for debug mode as its used to flush assets - - /// when truly in scan mode, everything will be BROKEN for functional reads! - #[inline(always)] - pub fn scan_mode(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Reserved field - #[inline(always)] - pub fn rsvd(&self) -> u32 { - (self.0 >> 4) & 0xfffffff - } - } - impl From for CptraSecurityStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraSecurityStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraTrngCtrlReadVal(u32); - impl CptraTrngCtrlReadVal { - /// Indicates that TRNG Data can be cleared - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - #[inline(always)] - pub fn clear(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraTrngCtrlWriteVal { - CptraTrngCtrlWriteVal(self.0) - } - } - impl From for CptraTrngCtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraTrngCtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraTrngCtrlWriteVal(u32); - impl CptraTrngCtrlWriteVal { - /// Indicates that TRNG Data can be cleared - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - #[inline(always)] - pub fn clear(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraTrngCtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraTrngCtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtStatusReadVal(u32); - impl CptraWdtStatusReadVal { - /// Timer1 timed out, timer2 enabled - #[inline(always)] - pub fn t1_timeout(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Timer2 timed out - #[inline(always)] - pub fn t2_timeout(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraWdtStatusWriteVal { - CptraWdtStatusWriteVal(self.0) - } - } - impl From for CptraWdtStatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtStatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtStatusWriteVal(u32); - impl CptraWdtStatusWriteVal { - /// Timer1 timed out, timer2 enabled - #[inline(always)] - pub fn t1_timeout(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Timer2 timed out - #[inline(always)] - pub fn t2_timeout(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for CptraWdtStatusWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtStatusWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer1CtrlReadVal(u32); - impl CptraWdtTimer1CtrlReadVal { - /// WDT timer1 restart - #[inline(always)] - pub fn timer1_restart(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraWdtTimer1CtrlWriteVal { - CptraWdtTimer1CtrlWriteVal(self.0) - } - } - impl From for CptraWdtTimer1CtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer1CtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer1CtrlWriteVal(u32); - impl CptraWdtTimer1CtrlWriteVal { - /// WDT timer1 restart - #[inline(always)] - pub fn timer1_restart(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraWdtTimer1CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer1CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer1EnReadVal(u32); - impl CptraWdtTimer1EnReadVal { - /// WDT timer1 enable - #[inline(always)] - pub fn timer1_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraWdtTimer1EnWriteVal { - CptraWdtTimer1EnWriteVal(self.0) - } - } - impl From for CptraWdtTimer1EnReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer1EnReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer1EnWriteVal(u32); - impl CptraWdtTimer1EnWriteVal { - /// WDT timer1 enable - #[inline(always)] - pub fn timer1_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraWdtTimer1EnWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer1EnWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer2CtrlReadVal(u32); - impl CptraWdtTimer2CtrlReadVal { - /// WDT timer2 restart - #[inline(always)] - pub fn timer2_restart(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraWdtTimer2CtrlWriteVal { - CptraWdtTimer2CtrlWriteVal(self.0) - } - } - impl From for CptraWdtTimer2CtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer2CtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer2CtrlWriteVal(u32); - impl CptraWdtTimer2CtrlWriteVal { - /// WDT timer2 restart - #[inline(always)] - pub fn timer2_restart(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraWdtTimer2CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer2CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer2EnReadVal(u32); - impl CptraWdtTimer2EnReadVal { - /// WDT timer2 enable - #[inline(always)] - pub fn timer2_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraWdtTimer2EnWriteVal { - CptraWdtTimer2EnWriteVal(self.0) - } - } - impl From for CptraWdtTimer2EnReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer2EnReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraWdtTimer2EnWriteVal(u32); - impl CptraWdtTimer2EnWriteVal { - /// WDT timer2 enable - #[inline(always)] - pub fn timer2_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraWdtTimer2EnWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraWdtTimer2EnWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraXxxxPauserLockReadVal(u32); - impl CptraXxxxPauserLockReadVal { - /// - #[inline(always)] - pub fn lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraXxxxPauserLockWriteVal { - CptraXxxxPauserLockWriteVal(self.0) - } - } - impl From for CptraXxxxPauserLockReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraXxxxPauserLockReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraXxxxPauserLockWriteVal(u32); - impl CptraXxxxPauserLockWriteVal { - /// - #[inline(always)] - pub fn lock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for CptraXxxxPauserLockWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraXxxxPauserLockWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraItrngEntropyConfig0ReadVal(u32); - impl CptraItrngEntropyConfig0ReadVal { - /// - #[inline(always)] - pub fn low_threshold(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// - #[inline(always)] - pub fn high_threshold(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraItrngEntropyConfig0WriteVal { - CptraItrngEntropyConfig0WriteVal(self.0) - } - } - impl From for CptraItrngEntropyConfig0ReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraItrngEntropyConfig0ReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraItrngEntropyConfig0WriteVal(u32); - impl CptraItrngEntropyConfig0WriteVal { - /// - #[inline(always)] - pub fn low_threshold(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// - #[inline(always)] - pub fn high_threshold(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for CptraItrngEntropyConfig0WriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraItrngEntropyConfig0WriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraItrngEntropyConfig1ReadVal(u32); - impl CptraItrngEntropyConfig1ReadVal { - /// - #[inline(always)] - pub fn repetition_count(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// - #[inline(always)] - pub fn rsvd(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraItrngEntropyConfig1WriteVal { - CptraItrngEntropyConfig1WriteVal(self.0) - } - } - impl From for CptraItrngEntropyConfig1ReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraItrngEntropyConfig1ReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraItrngEntropyConfig1WriteVal(u32); - impl CptraItrngEntropyConfig1WriteVal { - /// - #[inline(always)] - pub fn repetition_count(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// - #[inline(always)] - pub fn rsvd(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for CptraItrngEntropyConfig1WriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraItrngEntropyConfig1WriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTReadVal(u32); - impl ErrorIntrEnTReadVal { - /// Enable bit for Internal Errors - #[inline(always)] - pub fn error_internal_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Invalid Device in Pauser field - #[inline(always)] - pub fn error_inv_dev_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Failed Commands (invalid protocol or FW Fail Status) - #[inline(always)] - pub fn error_cmd_fail_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Bad Fuse received from SoC - #[inline(always)] - pub fn error_bad_fuse_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Enable bit for ICCM access blocked by lock - #[inline(always)] - pub fn error_iccm_blocked_en(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Enable bit for Mailbox ECC Double-bit Error (uncorrectable) - #[inline(always)] - pub fn error_mbox_ecc_unc_en(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Enable bit for WDT Timer1 timeout - #[inline(always)] - pub fn error_wdt_timer1_timeout_en(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// Enable bit for WDT Timer2 timeout, applicable if timer2 is enabled as an independent timer - #[inline(always)] - pub fn error_wdt_timer2_timeout_en(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrEnTWriteVal { - ErrorIntrEnTWriteVal(self.0) - } - } - impl From for ErrorIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrEnTWriteVal(u32); - impl ErrorIntrEnTWriteVal { - /// Enable bit for Internal Errors - #[inline(always)] - pub fn error_internal_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Invalid Device in Pauser field - #[inline(always)] - pub fn error_inv_dev_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Failed Commands (invalid protocol or FW Fail Status) - #[inline(always)] - pub fn error_cmd_fail_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Bad Fuse received from SoC - #[inline(always)] - pub fn error_bad_fuse_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Enable bit for ICCM access blocked by lock - #[inline(always)] - pub fn error_iccm_blocked_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Enable bit for Mailbox ECC Double-bit Error (uncorrectable) - #[inline(always)] - pub fn error_mbox_ecc_unc_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// Enable bit for WDT Timer1 timeout - #[inline(always)] - pub fn error_wdt_timer1_timeout_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// Enable bit for WDT Timer2 timeout, applicable if timer2 is enabled as an independent timer - #[inline(always)] - pub fn error_wdt_timer2_timeout_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - } - impl From for ErrorIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTReadVal(u32); - impl ErrorIntrTReadVal { - /// Internal Errors status bit - #[inline(always)] - pub fn error_internal_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Invalid Device in Pauser field status bit - #[inline(always)] - pub fn error_inv_dev_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Failed Commands status bit (invalid protocol or FW Fail Status) - #[inline(always)] - pub fn error_cmd_fail_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Bad Fuse received from SoC status bit - #[inline(always)] - pub fn error_bad_fuse_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// ICCM access blocked by lock status bit - #[inline(always)] - pub fn error_iccm_blocked_sts(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Mailbox ECC Double-bit Error (uncorrectable) status bit - #[inline(always)] - pub fn error_mbox_ecc_unc_sts(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// WDT Timer1 timeout status bit - #[inline(always)] - pub fn error_wdt_timer1_timeout_sts(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// WDT Timer2 timeout status bit - #[inline(always)] - pub fn error_wdt_timer2_timeout_sts(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTWriteVal { - ErrorIntrTWriteVal(self.0) - } - } - impl From for ErrorIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTWriteVal(u32); - impl ErrorIntrTWriteVal { - /// Internal Errors status bit - #[inline(always)] - pub fn error_internal_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Invalid Device in Pauser field status bit - #[inline(always)] - pub fn error_inv_dev_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Failed Commands status bit (invalid protocol or FW Fail Status) - #[inline(always)] - pub fn error_cmd_fail_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Bad Fuse received from SoC status bit - #[inline(always)] - pub fn error_bad_fuse_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// ICCM access blocked by lock status bit - #[inline(always)] - pub fn error_iccm_blocked_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Mailbox ECC Double-bit Error (uncorrectable) status bit - #[inline(always)] - pub fn error_mbox_ecc_unc_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// WDT Timer1 timeout status bit - #[inline(always)] - pub fn error_wdt_timer1_timeout_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// WDT Timer2 timeout status bit - #[inline(always)] - pub fn error_wdt_timer2_timeout_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - } - impl From for ErrorIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTReadVal(u32); - impl ErrorIntrTrigTReadVal { - /// Internal Errors trigger bit - #[inline(always)] - pub fn error_internal_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Invalid Device in Pauser field trigger bit - #[inline(always)] - pub fn error_inv_dev_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Failed Commands trigger bit - #[inline(always)] - pub fn error_cmd_fail_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Bad Fuse received from SoC trigger bit - #[inline(always)] - pub fn error_bad_fuse_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// ICCM access blocked by lock trigger bit - #[inline(always)] - pub fn error_iccm_blocked_trig(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Mailbox ECC Double-bit Error (uncorrectable) trigger bit - #[inline(always)] - pub fn error_mbox_ecc_unc_trig(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// WDT Timer1 timeout trigger bit - #[inline(always)] - pub fn error_wdt_timer1_timeout_trig(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// WDT Timer2 timeout trigger bit - #[inline(always)] - pub fn error_wdt_timer2_timeout_trig(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorIntrTrigTWriteVal { - ErrorIntrTrigTWriteVal(self.0) - } - } - impl From for ErrorIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorIntrTrigTWriteVal(u32); - impl ErrorIntrTrigTWriteVal { - /// Internal Errors trigger bit - #[inline(always)] - pub fn error_internal_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Invalid Device in Pauser field trigger bit - #[inline(always)] - pub fn error_inv_dev_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Failed Commands trigger bit - #[inline(always)] - pub fn error_cmd_fail_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Bad Fuse received from SoC trigger bit - #[inline(always)] - pub fn error_bad_fuse_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// ICCM access blocked by lock trigger bit - #[inline(always)] - pub fn error_iccm_blocked_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Mailbox ECC Double-bit Error (uncorrectable) trigger bit - #[inline(always)] - pub fn error_mbox_ecc_unc_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// WDT Timer1 timeout trigger bit - #[inline(always)] - pub fn error_wdt_timer1_timeout_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// WDT Timer2 timeout trigger bit - #[inline(always)] - pub fn error_wdt_timer2_timeout_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - } - impl From for ErrorIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorIntrTrigTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseAntiRollbackDisableReadVal(u32); - impl FuseAntiRollbackDisableReadVal { - /// - #[inline(always)] - pub fn dis(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FuseAntiRollbackDisableWriteVal { - FuseAntiRollbackDisableWriteVal(self.0) - } - } - impl From for FuseAntiRollbackDisableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseAntiRollbackDisableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseAntiRollbackDisableWriteVal(u32); - impl FuseAntiRollbackDisableWriteVal { - /// - #[inline(always)] - pub fn dis(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for FuseAntiRollbackDisableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseAntiRollbackDisableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseKeyManifestPkHashMaskReadVal(u32); - impl FuseKeyManifestPkHashMaskReadVal { - /// - #[inline(always)] - pub fn mask(&self) -> u32 { - (self.0 >> 0) & 0xf - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FuseKeyManifestPkHashMaskWriteVal { - FuseKeyManifestPkHashMaskWriteVal(self.0) - } - } - impl From for FuseKeyManifestPkHashMaskReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseKeyManifestPkHashMaskReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseKeyManifestPkHashMaskWriteVal(u32); - impl FuseKeyManifestPkHashMaskWriteVal { - /// - #[inline(always)] - pub fn mask(self, val: u32) -> Self { - Self((self.0 & !(0xf << 0)) | ((val & 0xf) << 0)) - } - } - impl From for FuseKeyManifestPkHashMaskWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseKeyManifestPkHashMaskWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseLifeCycleReadVal(u32); - impl FuseLifeCycleReadVal { - /// - #[inline(always)] - pub fn life_cycle(&self) -> u32 { - (self.0 >> 0) & 3 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FuseLifeCycleWriteVal { - FuseLifeCycleWriteVal(self.0) - } - } - impl From for FuseLifeCycleReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseLifeCycleReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseLifeCycleWriteVal(u32); - impl FuseLifeCycleWriteVal { - /// - #[inline(always)] - pub fn life_cycle(self, val: u32) -> Self { - Self((self.0 & !(3 << 0)) | ((val & 3) << 0)) - } - } - impl From for FuseLifeCycleWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseLifeCycleWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseLmsVerifyReadVal(u32); - impl FuseLmsVerifyReadVal { - /// - #[inline(always)] - pub fn lms_verify(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FuseLmsVerifyWriteVal { - FuseLmsVerifyWriteVal(self.0) - } - } - impl From for FuseLmsVerifyReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseLmsVerifyReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseLmsVerifyWriteVal(u32); - impl FuseLmsVerifyWriteVal { - /// - #[inline(always)] - pub fn lms_verify(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for FuseLmsVerifyWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseLmsVerifyWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseSocSteppingIdReadVal(u32); - impl FuseSocSteppingIdReadVal { - /// - #[inline(always)] - pub fn soc_stepping_id(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FuseSocSteppingIdWriteVal { - FuseSocSteppingIdWriteVal(self.0) - } - } - impl From for FuseSocSteppingIdReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseSocSteppingIdReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FuseSocSteppingIdWriteVal(u32); - impl FuseSocSteppingIdWriteVal { - /// - #[inline(always)] - pub fn soc_stepping_id(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - } - impl From for FuseSocSteppingIdWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FuseSocSteppingIdWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalFwUpdateResetReadVal(u32); - impl InternalFwUpdateResetReadVal { - /// FW Update reset to reset core - #[inline(always)] - pub fn core_rst(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InternalFwUpdateResetWriteVal { - InternalFwUpdateResetWriteVal(self.0) - } - } - impl From for InternalFwUpdateResetReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalFwUpdateResetReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalFwUpdateResetWriteVal(u32); - impl InternalFwUpdateResetWriteVal { - /// FW Update reset to reset core - #[inline(always)] - pub fn core_rst(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for InternalFwUpdateResetWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalFwUpdateResetWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalFwUpdateResetWaitCyclesReadVal(u32); - impl InternalFwUpdateResetWaitCyclesReadVal { - /// FW Update reset wait cycles - #[inline(always)] - pub fn wait_cycles(&self) -> u32 { - (self.0 >> 0) & 0xff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InternalFwUpdateResetWaitCyclesWriteVal { - InternalFwUpdateResetWaitCyclesWriteVal(self.0) - } - } - impl From for InternalFwUpdateResetWaitCyclesReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalFwUpdateResetWaitCyclesReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalFwUpdateResetWaitCyclesWriteVal(u32); - impl InternalFwUpdateResetWaitCyclesWriteVal { - /// FW Update reset wait cycles - #[inline(always)] - pub fn wait_cycles(self, val: u32) -> Self { - Self((self.0 & !(0xff << 0)) | ((val & 0xff) << 0)) - } - } - impl From for InternalFwUpdateResetWaitCyclesWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalFwUpdateResetWaitCyclesWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalHwErrorFatalMaskReadVal(u32); - impl InternalHwErrorFatalMaskReadVal { - /// - #[inline(always)] - pub fn mask_iccm_ecc_unc(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// - #[inline(always)] - pub fn mask_dccm_ecc_unc(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// - #[inline(always)] - pub fn mask_nmi_pin(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InternalHwErrorFatalMaskWriteVal { - InternalHwErrorFatalMaskWriteVal(self.0) - } - } - impl From for InternalHwErrorFatalMaskReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalHwErrorFatalMaskReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalHwErrorFatalMaskWriteVal(u32); - impl InternalHwErrorFatalMaskWriteVal { - /// - #[inline(always)] - pub fn mask_iccm_ecc_unc(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// - #[inline(always)] - pub fn mask_dccm_ecc_unc(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// - #[inline(always)] - pub fn mask_nmi_pin(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - } - impl From for InternalHwErrorFatalMaskWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalHwErrorFatalMaskWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalHwErrorNonFatalMaskReadVal(u32); - impl InternalHwErrorNonFatalMaskReadVal { - /// - #[inline(always)] - pub fn mask_mbox_prot_no_lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// - #[inline(always)] - pub fn mask_mbox_prot_ooo(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// - #[inline(always)] - pub fn mask_mbox_ecc_unc(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InternalHwErrorNonFatalMaskWriteVal { - InternalHwErrorNonFatalMaskWriteVal(self.0) - } - } - impl From for InternalHwErrorNonFatalMaskReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalHwErrorNonFatalMaskReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalHwErrorNonFatalMaskWriteVal(u32); - impl InternalHwErrorNonFatalMaskWriteVal { - /// - #[inline(always)] - pub fn mask_mbox_prot_no_lock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// - #[inline(always)] - pub fn mask_mbox_prot_ooo(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// - #[inline(always)] - pub fn mask_mbox_ecc_unc(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - } - impl From for InternalHwErrorNonFatalMaskWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalHwErrorNonFatalMaskWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalIccmLockReadVal(u32); - impl InternalIccmLockReadVal { - /// Lock bit gates writes to ICCM. Write 1 to set - cannot be cleared by SW. - #[inline(always)] - pub fn lock(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InternalIccmLockWriteVal { - InternalIccmLockWriteVal(self.0) - } - } - impl From for InternalIccmLockReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalIccmLockReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InternalIccmLockWriteVal(u32); - impl InternalIccmLockWriteVal { - /// Lock bit gates writes to ICCM. Write 1 to set - cannot be cleared by SW. - #[inline(always)] - pub fn lock(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for InternalIccmLockWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InternalIccmLockWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTReadVal(u32); - impl NotifIntrEnTReadVal { - /// Enable bit for Command Available - #[inline(always)] - pub fn notif_cmd_avail_en(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable bit for Mailbox ECC Single-bit Error (correctable) - #[inline(always)] - pub fn notif_mbox_ecc_cor_en(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable bit for Security State, Debug Locked transition - #[inline(always)] - pub fn notif_debug_locked_en(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable bit for Scan mode - #[inline(always)] - pub fn notif_scan_mode_en(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Enable bit for SoC requested the mailbox while locked - #[inline(always)] - pub fn notif_soc_req_lock_en(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Enable bit for Generic Input Wires Toggle - #[inline(always)] - pub fn notif_gen_in_toggle_en(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrEnTWriteVal { - NotifIntrEnTWriteVal(self.0) - } - } - impl From for NotifIntrEnTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrEnTWriteVal(u32); - impl NotifIntrEnTWriteVal { - /// Enable bit for Command Available - #[inline(always)] - pub fn notif_cmd_avail_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable bit for Mailbox ECC Single-bit Error (correctable) - #[inline(always)] - pub fn notif_mbox_ecc_cor_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable bit for Security State, Debug Locked transition - #[inline(always)] - pub fn notif_debug_locked_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable bit for Scan mode - #[inline(always)] - pub fn notif_scan_mode_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Enable bit for SoC requested the mailbox while locked - #[inline(always)] - pub fn notif_soc_req_lock_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Enable bit for Generic Input Wires Toggle - #[inline(always)] - pub fn notif_gen_in_toggle_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - } - impl From for NotifIntrEnTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrEnTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTReadVal(u32); - impl NotifIntrTReadVal { - /// Command Available status bit - #[inline(always)] - pub fn notif_cmd_avail_sts(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Mailbox ECC Single-bit Error (correctable) status bit - #[inline(always)] - pub fn notif_mbox_ecc_cor_sts(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Security State, Debug Locked transition status bit - #[inline(always)] - pub fn notif_debug_locked_sts(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Scan mode status bit - #[inline(always)] - pub fn notif_scan_mode_sts(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// SoC requested the mailbox while locked status bit - #[inline(always)] - pub fn notif_soc_req_lock_sts(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Generic Input Wires Toggle status bit - #[inline(always)] - pub fn notif_gen_in_toggle_sts(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTWriteVal { - NotifIntrTWriteVal(self.0) - } - } - impl From for NotifIntrTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTWriteVal(u32); - impl NotifIntrTWriteVal { - /// Command Available status bit - #[inline(always)] - pub fn notif_cmd_avail_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Mailbox ECC Single-bit Error (correctable) status bit - #[inline(always)] - pub fn notif_mbox_ecc_cor_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Security State, Debug Locked transition status bit - #[inline(always)] - pub fn notif_debug_locked_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Scan mode status bit - #[inline(always)] - pub fn notif_scan_mode_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// SoC requested the mailbox while locked status bit - #[inline(always)] - pub fn notif_soc_req_lock_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Generic Input Wires Toggle status bit - #[inline(always)] - pub fn notif_gen_in_toggle_sts(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - } - impl From for NotifIntrTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTReadVal(u32); - impl NotifIntrTrigTReadVal { - /// Command Available trigger bit - #[inline(always)] - pub fn notif_cmd_avail_trig(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Mailbox ECC Single-bit Error (correctable) trigger bit - #[inline(always)] - pub fn notif_mbox_ecc_cor_trig(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Security State, Debug Locked transition trigger bit - #[inline(always)] - pub fn notif_debug_locked_trig(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Scan mode trigger bit - #[inline(always)] - pub fn notif_scan_mode_trig(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// SoC requested the mailbox while locked trigger bit - #[inline(always)] - pub fn notif_soc_req_lock_trig(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Generic Input Wires Toggle trigger bit - #[inline(always)] - pub fn notif_gen_in_toggle_trig(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> NotifIntrTrigTWriteVal { - NotifIntrTrigTWriteVal(self.0) - } - } - impl From for NotifIntrTrigTReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct NotifIntrTrigTWriteVal(u32); - impl NotifIntrTrigTWriteVal { - /// Command Available trigger bit - #[inline(always)] - pub fn notif_cmd_avail_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Mailbox ECC Single-bit Error (correctable) trigger bit - #[inline(always)] - pub fn notif_mbox_ecc_cor_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Security State, Debug Locked transition trigger bit - #[inline(always)] - pub fn notif_debug_locked_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Scan mode trigger bit - #[inline(always)] - pub fn notif_scan_mode_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// SoC requested the mailbox while locked trigger bit - #[inline(always)] - pub fn notif_soc_req_lock_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Generic Input Wires Toggle trigger bit - #[inline(always)] - pub fn notif_gen_in_toggle_trig(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - } - impl From for NotifIntrTrigTWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: NotifIntrTrigTWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - #[derive(Clone, Copy, Eq, PartialEq)] - #[repr(u32)] - pub enum DeviceLifecycleE { - Unprovisioned = 0, - Manufacturing = 1, - Reserved2 = 2, - Production = 3, - } - impl DeviceLifecycleE { - #[inline(always)] - pub fn unprovisioned(&self) -> bool { - *self == Self::Unprovisioned - } - #[inline(always)] - pub fn manufacturing(&self) -> bool { - *self == Self::Manufacturing - } - #[inline(always)] - pub fn production(&self) -> bool { - *self == Self::Production - } - } - impl TryFrom for DeviceLifecycleE { - type Error = (); - #[inline(always)] - fn try_from(val: u32) -> Result { - if val < 4 { - Ok(unsafe { core::mem::transmute(val) }) - } else { - Err(()) - } - } - } - impl From for u32 { - fn from(val: DeviceLifecycleE) -> Self { - val as u32 - } - } - pub mod selector { - pub struct DeviceLifecycleESelector(); - impl DeviceLifecycleESelector { - #[inline(always)] - pub fn unprovisioned(&self) -> super::DeviceLifecycleE { - super::DeviceLifecycleE::Unprovisioned - } - #[inline(always)] - pub fn manufacturing(&self) -> super::DeviceLifecycleE { - super::DeviceLifecycleE::Manufacturing - } - #[inline(always)] - pub fn production(&self) -> super::DeviceLifecycleE { - super::DeviceLifecycleE::Production - } - } - } -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type CptraHwErrorFatal = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraHwErrorFatalReadVal, - crate::soc_ifc::regs::CptraHwErrorFatalWriteVal, - >; - pub type CptraHwErrorNonFatal = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraHwErrorNonFatalReadVal, - crate::soc_ifc::regs::CptraHwErrorNonFatalWriteVal, - >; - pub type CptraFwErrorFatal = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraFwErrorNonFatal = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraHwErrorEnc = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraFwErrorEnc = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraFwExtendedErrorInfo = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraBootStatus = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraFlowStatus = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraFlowStatusReadVal, - crate::soc_ifc::regs::CptraFlowStatusWriteVal, - >; - pub type CptraResetReason = ureg::ReadOnlyReg32; - pub type CptraSecurityState = - ureg::ReadOnlyReg32; - pub type CptraMboxValidPauser = ureg::ReadWriteReg32<0xffffffff, u32, u32>; - pub type CptraMboxPauserLock = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraXxxxPauserLockReadVal, - crate::soc_ifc::regs::CptraXxxxPauserLockWriteVal, - >; - pub type CptraTrngValidPauser = ureg::ReadWriteReg32<0xffffffff, u32, u32>; - pub type CptraTrngPauserLock = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraXxxxPauserLockReadVal, - crate::soc_ifc::regs::CptraXxxxPauserLockWriteVal, - >; - pub type CptraTrngCtrl = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraTrngCtrlReadVal, - crate::soc_ifc::regs::CptraTrngCtrlWriteVal, - >; - pub type CptraFuseWrDone = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraFuseWrDoneReadVal, - crate::soc_ifc::regs::CptraFuseWrDoneWriteVal, - >; - pub type CptraTimerConfig = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraBootfsmGo = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraBootfsmGoReadVal, - crate::soc_ifc::regs::CptraBootfsmGoWriteVal, - >; - pub type CptraDbgManufServiceReg = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraClkGatingEn = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraClkGatingEnReadVal, - crate::soc_ifc::regs::CptraClkGatingEnWriteVal, - >; - pub type CptraGenericInputWires = ureg::ReadOnlyReg32; - pub type CptraGenericOutputWires = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraHwRevId = ureg::ReadOnlyReg32; - pub type CptraFwRevId = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraHwConfig = ureg::ReadOnlyReg32; - pub type CptraWdtTimer1En = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraWdtTimer1EnReadVal, - crate::soc_ifc::regs::CptraWdtTimer1EnWriteVal, - >; - pub type CptraWdtTimer1Ctrl = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraWdtTimer1CtrlReadVal, - crate::soc_ifc::regs::CptraWdtTimer1CtrlWriteVal, - >; - pub type CptraWdtTimer1TimeoutPeriod = ureg::ReadWriteReg32<0xffffffff, u32, u32>; - pub type CptraWdtTimer2En = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraWdtTimer2EnReadVal, - crate::soc_ifc::regs::CptraWdtTimer2EnWriteVal, - >; - pub type CptraWdtTimer2Ctrl = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraWdtTimer2CtrlReadVal, - crate::soc_ifc::regs::CptraWdtTimer2CtrlWriteVal, - >; - pub type CptraWdtTimer2TimeoutPeriod = ureg::ReadWriteReg32<0xffffffff, u32, u32>; - pub type CptraWdtStatus = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraWdtStatusReadVal, - crate::soc_ifc::regs::CptraWdtStatusWriteVal, - >; - pub type CptraFuseValidPauser = ureg::ReadWriteReg32<0xffffffff, u32, u32>; - pub type CptraFusePauserLock = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraXxxxPauserLockReadVal, - crate::soc_ifc::regs::CptraXxxxPauserLockWriteVal, - >; - pub type CptraWdtCfg = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraItrngEntropyConfig0 = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraItrngEntropyConfig0ReadVal, - crate::soc_ifc::regs::CptraItrngEntropyConfig0WriteVal, - >; - pub type CptraItrngEntropyConfig1 = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::CptraItrngEntropyConfig1ReadVal, - crate::soc_ifc::regs::CptraItrngEntropyConfig1WriteVal, - >; - pub type CptraRsvdReg = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseUdsSeed = ureg::WriteOnlyReg32<0, u32>; - pub type FuseFieldEntropy = ureg::WriteOnlyReg32<0, u32>; - pub type FuseKeyManifestPkHash = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseKeyManifestPkHashMask = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::FuseKeyManifestPkHashMaskReadVal, - crate::soc_ifc::regs::FuseKeyManifestPkHashMaskWriteVal, - >; - pub type FuseOwnerPkHash = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseFmcKeyManifestSvn = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseRuntimeSvn = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseAntiRollbackDisable = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::FuseAntiRollbackDisableReadVal, - crate::soc_ifc::regs::FuseAntiRollbackDisableWriteVal, - >; - pub type FuseIdevidCertAttr = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseIdevidManufHsmId = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseLifeCycle = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::FuseLifeCycleReadVal, - crate::soc_ifc::regs::FuseLifeCycleWriteVal, - >; - pub type FuseLmsVerify = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::FuseLmsVerifyReadVal, - crate::soc_ifc::regs::FuseLmsVerifyWriteVal, - >; - pub type FuseLmsRevocation = ureg::ReadWriteReg32<0, u32, u32>; - pub type FuseSocSteppingId = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::FuseSocSteppingIdReadVal, - crate::soc_ifc::regs::FuseSocSteppingIdWriteVal, - >; - pub type InternalObfKey = ureg::WriteOnlyReg32<0, u32>; - pub type InternalIccmLock = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::InternalIccmLockReadVal, - crate::soc_ifc::regs::InternalIccmLockWriteVal, - >; - pub type InternalFwUpdateReset = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::InternalFwUpdateResetReadVal, - crate::soc_ifc::regs::InternalFwUpdateResetWriteVal, - >; - pub type InternalFwUpdateResetWaitCycles = ureg::ReadWriteReg32< - 5, - crate::soc_ifc::regs::InternalFwUpdateResetWaitCyclesReadVal, - crate::soc_ifc::regs::InternalFwUpdateResetWaitCyclesWriteVal, - >; - pub type InternalNmiVector = ureg::ReadWriteReg32<0, u32, u32>; - pub type InternalHwErrorFatalMask = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::InternalHwErrorFatalMaskReadVal, - crate::soc_ifc::regs::InternalHwErrorFatalMaskWriteVal, - >; - pub type InternalHwErrorNonFatalMask = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::InternalHwErrorNonFatalMaskReadVal, - crate::soc_ifc::regs::InternalHwErrorNonFatalMaskWriteVal, - >; - pub type InternalFwErrorFatalMask = ureg::ReadWriteReg32<0, u32, u32>; - pub type InternalFwErrorNonFatalMask = ureg::ReadWriteReg32<0, u32, u32>; - pub type InternalRvMtimeL = ureg::ReadWriteReg32<0, u32, u32>; - pub type InternalRvMtimeH = ureg::ReadWriteReg32<0, u32, u32>; - pub type InternalRvMtimecmpL = ureg::ReadWriteReg32<0, u32, u32>; - pub type InternalRvMtimecmpH = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfGlobalIntrEnR = ureg::ReadWriteReg32< - 0, - crate::sha512_acc::regs::GlobalIntrEnTReadVal, - crate::sha512_acc::regs::GlobalIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorIntrEnR = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::ErrorIntrEnTReadVal, - crate::soc_ifc::regs::ErrorIntrEnTWriteVal, - >; - pub type IntrBlockRfNotifIntrEnR = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::NotifIntrEnTReadVal, - crate::soc_ifc::regs::NotifIntrEnTWriteVal, - >; - pub type IntrBlockRfErrorGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGlobalIntrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::ErrorIntrTReadVal, - crate::soc_ifc::regs::ErrorIntrTWriteVal, - >; - pub type IntrBlockRfNotifInternalIntrR = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::NotifIntrTReadVal, - crate::soc_ifc::regs::NotifIntrTWriteVal, - >; - pub type IntrBlockRfErrorIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::ErrorIntrTrigTReadVal, - crate::soc_ifc::regs::ErrorIntrTrigTWriteVal, - >; - pub type IntrBlockRfNotifIntrTrigR = ureg::ReadWriteReg32< - 0, - crate::soc_ifc::regs::NotifIntrTrigTReadVal, - crate::soc_ifc::regs::NotifIntrTrigTWriteVal, - >; - pub type IntrBlockRfErrorInternalIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorInvDevIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorCmdFailIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorBadFuseIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorIccmBlockedIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorMboxEccUncIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorWdtTimer1TimeoutIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorWdtTimer2TimeoutIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifCmdAvailIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifMboxEccCorIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifDebugLockedIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifScanModeIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifSocReqLockIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfNotifGenInToggleIntrCountR = ureg::ReadWriteReg32<0, u32, u32>; - pub type IntrBlockRfErrorInternalIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorInvDevIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorCmdFailIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorBadFuseIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorIccmBlockedIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorMboxEccUncIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorWdtTimer1TimeoutIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfErrorWdtTimer2TimeoutIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifCmdAvailIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifMboxEccCorIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifDebugLockedIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifScanModeIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifSocReqLockIntrCountIncrR = - ureg::ReadOnlyReg32; - pub type IntrBlockRfNotifGenInToggleIntrCountIncrR = - ureg::ReadOnlyReg32; -} diff --git a/hw/1.0/registers/src/soc_ifc_trng.rs b/hw/1.0/registers/src/soc_ifc_trng.rs deleted file mode 100644 index dba99e1dff..0000000000 --- a/hw/1.0/registers/src/soc_ifc_trng.rs +++ /dev/null @@ -1,188 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct SocIfcTrngReg { - _priv: (), -} -impl SocIfcTrngReg { - pub const PTR: *mut u32 = 0x30030000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Storage for the requested TRNG Data. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RW - /// - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn cptra_trng_data( - &self, - ) -> ureg::Array<12, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x78 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// TRNG Status register to indicate request and done - /// - /// Read value: [`soc_ifc_trng::regs::CptraTrngStatusReadVal`]; Write value: [`soc_ifc_trng::regs::CptraTrngStatusWriteVal`] - #[inline(always)] - pub fn cptra_trng_status( - &self, - ) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xac / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct CptraTrngStatusReadVal(u32); - impl CptraTrngStatusReadVal { - /// Indicates that there is a request for TRNG Data. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - #[inline(always)] - pub fn data_req(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Indicates that the requests TRNG Data is done and stored in the TRNG Data register. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RW - /// [br]When DATA_REQ is 0 DATA_WR_DONE will also be 0 - #[inline(always)] - pub fn data_wr_done(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CptraTrngStatusWriteVal { - CptraTrngStatusWriteVal(self.0) - } - } - impl From for CptraTrngStatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraTrngStatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CptraTrngStatusWriteVal(u32); - impl CptraTrngStatusWriteVal { - /// Indicates that there is a request for TRNG Data. - /// [br]Caliptra Access: RW - /// [br]SOC Access: RO - #[inline(always)] - pub fn data_req(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Indicates that the requests TRNG Data is done and stored in the TRNG Data register. - /// [br]Caliptra Access: RO - /// [br]SOC Access: RW - /// [br]When DATA_REQ is 0 DATA_WR_DONE will also be 0 - #[inline(always)] - pub fn data_wr_done(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for CptraTrngStatusWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CptraTrngStatusWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type CptraTrngData = ureg::ReadWriteReg32<0, u32, u32>; - pub type CptraTrngStatus = ureg::ReadWriteReg32< - 0, - crate::soc_ifc_trng::regs::CptraTrngStatusReadVal, - crate::soc_ifc_trng::regs::CptraTrngStatusWriteVal, - >; -} diff --git a/hw/1.0/registers/src/spi_host.rs b/hw/1.0/registers/src/spi_host.rs deleted file mode 100644 index df7c477afe..0000000000 --- a/hw/1.0/registers/src/spi_host.rs +++ /dev/null @@ -1,1189 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct SpiHostReg { - _priv: (), -} -impl SpiHostReg { - pub const PTR: *mut u32 = 0x20000000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Read value: [`spi_host::regs::InterruptStateReadVal`]; Write value: [`spi_host::regs::InterruptStateWriteVal`] - #[inline(always)] - pub fn interrupt_state(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::InterruptEnableReadVal`]; Write value: [`spi_host::regs::InterruptEnableWriteVal`] - #[inline(always)] - pub fn interrupt_enable(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::InterruptTestReadVal`]; Write value: [`spi_host::regs::InterruptTestWriteVal`] - #[inline(always)] - pub fn interrupt_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::AlertTestReadVal`]; Write value: [`spi_host::regs::AlertTestWriteVal`] - #[inline(always)] - pub fn alert_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::ControlReadVal`]; Write value: [`spi_host::regs::ControlWriteVal`] - #[inline(always)] - pub fn control(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::StatusReadVal`]; Write value: [`spi_host::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::ConfigoptsReadVal`]; Write value: [`spi_host::regs::ConfigoptsWriteVal`] - #[inline(always)] - pub fn configopts( - &self, - ) -> ureg::Array<2, ureg::RegRef> { - unsafe { - ureg::Array::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn csid(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::CommandReadVal`]; Write value: [`spi_host::regs::CommandWriteVal`] - #[inline(always)] - pub fn command(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x24 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn rxdata(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x28 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`u32`]; Write value: [`u32`] - #[inline(always)] - pub fn txdata(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x2c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::ErrorEnableReadVal`]; Write value: [`spi_host::regs::ErrorEnableWriteVal`] - #[inline(always)] - pub fn error_enable(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x30 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::ErrorStatusReadVal`]; Write value: [`spi_host::regs::ErrorStatusWriteVal`] - #[inline(always)] - pub fn error_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x34 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`spi_host::regs::EventEnableReadVal`]; Write value: [`spi_host::regs::EventEnableWriteVal`] - #[inline(always)] - pub fn event_enable(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x38 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct AlertTestWriteVal(u32); - impl AlertTestWriteVal { - /// Write 1 to trigger one alert event of this kind. - #[inline(always)] - pub fn fatal_fault(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for AlertTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CommandWriteVal(u32); - impl CommandWriteVal { - /// Segment Length. - /// - /// For read or write segments, this field controls the - /// number of 1-byte bursts to transmit and or receive in - /// this command segment. The number of cyles required - /// to send or received a byte will depend on !!COMMAND.SPEED. - /// For dummy segments, (!!COMMAND.DIRECTION == 0), this register - /// controls the number of dummy cycles to issue. - /// The number of bytes (or dummy cycles) in the segment will be - /// equal to !!COMMAND.LEN + 1. - #[inline(always)] - pub fn len(self, val: u32) -> Self { - Self((self.0 & !(0x1ff << 0)) | ((val & 0x1ff) << 0)) - } - /// Chip select active after transaction. If CSAAT = 0, the - /// chip select line is raised immediately at the end of the - /// command segment. If !!COMMAND.CSAAT = 1, the chip select - /// line is left low at the end of the current transaction - /// segment. This allows the creation longer, more - /// complete SPI transactions, consisting of several separate - /// segments for issuing instructions, pausing for dummy cycles, - /// and transmitting or receiving data from the device. - #[inline(always)] - pub fn csaat(self, val: bool) -> Self { - Self((self.0 & !(1 << 9)) | (u32::from(val) << 9)) - } - /// The speed for this command segment: "0" = Standard SPI. "1" = Dual SPI. - /// "2"=Quad SPI, "3": RESERVED. - #[inline(always)] - pub fn speed(self, val: u32) -> Self { - Self((self.0 & !(3 << 10)) | ((val & 3) << 10)) - } - /// The direction for the following command: "0" = Dummy cycles - /// (no TX/RX). "1" = Rx only, "2" = Tx only, "3" = Bidirectional - /// Tx/Rx (Standard SPI mode only). - #[inline(always)] - pub fn direction(self, val: u32) -> Self { - Self((self.0 & !(3 << 12)) | ((val & 3) << 12)) - } - } - impl From for CommandWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CommandWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ConfigoptsReadVal(u32); - impl ConfigoptsReadVal { - /// Core clock divider. Slows down subsequent SPI transactions by a - /// factor of (CLKDIV+1) relative to the core clock frequency. The - /// period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)` - #[inline(always)] - pub fn clkdiv(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - /// Minimum idle time between commands. Indicates the minimum - /// number of sck half-cycles to hold cs_n high between commands. - /// Setting this register to zero creates a minimally-wide CS_N-high - /// pulse of one-half sck cycle. - #[inline(always)] - pub fn csnidle(&self) -> u32 { - (self.0 >> 16) & 0xf - } - /// CS_N Trailing Time. Indicates the number of half sck cycles, - /// CSNTRAIL+1, to leave between last edge of sck and the rising - /// edge of cs_n. Setting this register to zero corresponds - /// to the minimum delay of one-half sck cycle. - #[inline(always)] - pub fn csntrail(&self) -> u32 { - (self.0 >> 20) & 0xf - } - /// CS_N Leading Time. Indicates the number of half sck cycles, - /// CSNLEAD+1, to leave between the falling edge of cs_n and - /// the first edge of sck. Setting this register to zero - /// corresponds to the minimum delay of one-half sck cycle - #[inline(always)] - pub fn csnlead(&self) -> u32 { - (self.0 >> 24) & 0xf - } - /// Full cycle. Modifies the CPHA sampling behaviour to allow - /// for longer device logic setup times. Rather than sampling the SD - /// bus a half cycle after shifting out data, the data is sampled - /// a full cycle after shifting data out. This means that if - /// CPHA = 0, data is shifted out on the trailing edge, and - /// sampled a full cycle later. If CPHA = 1, data is shifted and - /// sampled with the trailing edge, also separated by a - /// full cycle. - #[inline(always)] - pub fn fullcyc(&self) -> bool { - ((self.0 >> 29) & 1) != 0 - } - /// The phase of the sck clock signal relative to the data. When - /// CPHA = 0, the data changes on the trailing edge of sck - /// and is typically sampled on the leading edge. Conversely - /// if CPHA = 1 high, data lines change on the leading edge of - /// sck and are typically sampled on the trailing edge. - /// CPHA should be chosen to match the phase of the selected - /// device. The sampling behavior is modified by the - /// !!CONFIGOPTS.FULLCYC bit. - #[inline(always)] - pub fn cpha(&self) -> bool { - ((self.0 >> 30) & 1) != 0 - } - /// The polarity of the sck clock signal. When CPOL is 0, - /// sck is low when idle, and emits high pulses. When CPOL - /// is low, sck is high when idle, and emits a series of low - /// pulses. - #[inline(always)] - pub fn cpol(&self) -> bool { - ((self.0 >> 31) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ConfigoptsWriteVal { - ConfigoptsWriteVal(self.0) - } - } - impl From for ConfigoptsReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ConfigoptsReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ConfigoptsWriteVal(u32); - impl ConfigoptsWriteVal { - /// Core clock divider. Slows down subsequent SPI transactions by a - /// factor of (CLKDIV+1) relative to the core clock frequency. The - /// period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)` - #[inline(always)] - pub fn clkdiv(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 0)) | ((val & 0xffff) << 0)) - } - /// Minimum idle time between commands. Indicates the minimum - /// number of sck half-cycles to hold cs_n high between commands. - /// Setting this register to zero creates a minimally-wide CS_N-high - /// pulse of one-half sck cycle. - #[inline(always)] - pub fn csnidle(self, val: u32) -> Self { - Self((self.0 & !(0xf << 16)) | ((val & 0xf) << 16)) - } - /// CS_N Trailing Time. Indicates the number of half sck cycles, - /// CSNTRAIL+1, to leave between last edge of sck and the rising - /// edge of cs_n. Setting this register to zero corresponds - /// to the minimum delay of one-half sck cycle. - #[inline(always)] - pub fn csntrail(self, val: u32) -> Self { - Self((self.0 & !(0xf << 20)) | ((val & 0xf) << 20)) - } - /// CS_N Leading Time. Indicates the number of half sck cycles, - /// CSNLEAD+1, to leave between the falling edge of cs_n and - /// the first edge of sck. Setting this register to zero - /// corresponds to the minimum delay of one-half sck cycle - #[inline(always)] - pub fn csnlead(self, val: u32) -> Self { - Self((self.0 & !(0xf << 24)) | ((val & 0xf) << 24)) - } - /// Full cycle. Modifies the CPHA sampling behaviour to allow - /// for longer device logic setup times. Rather than sampling the SD - /// bus a half cycle after shifting out data, the data is sampled - /// a full cycle after shifting data out. This means that if - /// CPHA = 0, data is shifted out on the trailing edge, and - /// sampled a full cycle later. If CPHA = 1, data is shifted and - /// sampled with the trailing edge, also separated by a - /// full cycle. - #[inline(always)] - pub fn fullcyc(self, val: bool) -> Self { - Self((self.0 & !(1 << 29)) | (u32::from(val) << 29)) - } - /// The phase of the sck clock signal relative to the data. When - /// CPHA = 0, the data changes on the trailing edge of sck - /// and is typically sampled on the leading edge. Conversely - /// if CPHA = 1 high, data lines change on the leading edge of - /// sck and are typically sampled on the trailing edge. - /// CPHA should be chosen to match the phase of the selected - /// device. The sampling behavior is modified by the - /// !!CONFIGOPTS.FULLCYC bit. - #[inline(always)] - pub fn cpha(self, val: bool) -> Self { - Self((self.0 & !(1 << 30)) | (u32::from(val) << 30)) - } - /// The polarity of the sck clock signal. When CPOL is 0, - /// sck is low when idle, and emits high pulses. When CPOL - /// is low, sck is high when idle, and emits a series of low - /// pulses. - #[inline(always)] - pub fn cpol(self, val: bool) -> Self { - Self((self.0 & !(1 << 31)) | (u32::from(val) << 31)) - } - } - impl From for ConfigoptsWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ConfigoptsWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ControlReadVal(u32); - impl ControlReadVal { - /// If !!EVENT_ENABLE.RXWM is set, the IP will send - /// an interrupt when the depth of the RX FIFO reaches - /// RX_WATERMARK words (32b each). - #[inline(always)] - pub fn rx_watermark(&self) -> u32 { - (self.0 >> 0) & 0xff - } - /// If !!EVENT_ENABLE.TXWM is set, the IP will send - /// an interrupt when the depth of the TX FIFO drops below - /// TX_WATERMARK words (32b each). - #[inline(always)] - pub fn tx_watermark(&self) -> u32 { - (self.0 >> 8) & 0xff - } - /// Enable the SPI host output buffers for the sck, csb, and sd lines. This allows - /// the SPI_HOST IP to connect to the same bus as other SPI controllers without - /// interference. - #[inline(always)] - pub fn output_en(&self) -> bool { - ((self.0 >> 29) & 1) != 0 - } - /// Clears the entire IP to the reset state when set to 1, including - /// the FIFOs, the CDC's, the core state machine and the shift register. - /// In the current implementation, the CDC FIFOs are drained not reset. - /// Therefore software must confirm that both FIFO's empty before releasing - /// the IP from reset. - #[inline(always)] - pub fn sw_rst(&self) -> bool { - ((self.0 >> 30) & 1) != 0 - } - /// Enables the SPI host. On reset, this field is 0, meaning - /// that no transactions can proceed. - #[inline(always)] - pub fn spien(&self) -> bool { - ((self.0 >> 31) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ControlWriteVal { - ControlWriteVal(self.0) - } - } - impl From for ControlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ControlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ControlWriteVal(u32); - impl ControlWriteVal { - /// If !!EVENT_ENABLE.RXWM is set, the IP will send - /// an interrupt when the depth of the RX FIFO reaches - /// RX_WATERMARK words (32b each). - #[inline(always)] - pub fn rx_watermark(self, val: u32) -> Self { - Self((self.0 & !(0xff << 0)) | ((val & 0xff) << 0)) - } - /// If !!EVENT_ENABLE.TXWM is set, the IP will send - /// an interrupt when the depth of the TX FIFO drops below - /// TX_WATERMARK words (32b each). - #[inline(always)] - pub fn tx_watermark(self, val: u32) -> Self { - Self((self.0 & !(0xff << 8)) | ((val & 0xff) << 8)) - } - /// Enable the SPI host output buffers for the sck, csb, and sd lines. This allows - /// the SPI_HOST IP to connect to the same bus as other SPI controllers without - /// interference. - #[inline(always)] - pub fn output_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 29)) | (u32::from(val) << 29)) - } - /// Clears the entire IP to the reset state when set to 1, including - /// the FIFOs, the CDC's, the core state machine and the shift register. - /// In the current implementation, the CDC FIFOs are drained not reset. - /// Therefore software must confirm that both FIFO's empty before releasing - /// the IP from reset. - #[inline(always)] - pub fn sw_rst(self, val: bool) -> Self { - Self((self.0 & !(1 << 30)) | (u32::from(val) << 30)) - } - /// Enables the SPI host. On reset, this field is 0, meaning - /// that no transactions can proceed. - #[inline(always)] - pub fn spien(self, val: bool) -> Self { - Self((self.0 & !(1 << 31)) | (u32::from(val) << 31)) - } - } - impl From for ControlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ControlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorEnableReadVal(u32); - impl ErrorEnableReadVal { - /// Command Error: If this bit is set, the block sends an error - /// interrupt whenever a command is issued while busy (i.e. a 1 is - /// when !!STATUS.READY is not asserted.) - #[inline(always)] - pub fn cmdbusy(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Overflow Errors: If this bit is set, the block sends an - /// error interrupt whenever the TX FIFO overflows. - #[inline(always)] - pub fn overflow(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Underflow Errors: If this bit is set, the block sends an - /// error interrupt whenever there is a read from !!RXDATA - /// but the RX FIFO is empty. - #[inline(always)] - pub fn underflow(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Invalid Command Errors: If this bit is set, the block sends an - /// error interrupt whenever a command is sent with invalid values for - /// !!COMMAND.SPEED or !!COMMAND.DIRECTION. - #[inline(always)] - pub fn cmdinval(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Invalid CSID: If this bit is set, the block sends an error interrupt whenever - /// a command is submitted, but CSID exceeds NumCS. - #[inline(always)] - pub fn csidinval(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorEnableWriteVal { - ErrorEnableWriteVal(self.0) - } - } - impl From for ErrorEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorEnableWriteVal(u32); - impl ErrorEnableWriteVal { - /// Command Error: If this bit is set, the block sends an error - /// interrupt whenever a command is issued while busy (i.e. a 1 is - /// when !!STATUS.READY is not asserted.) - #[inline(always)] - pub fn cmdbusy(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Overflow Errors: If this bit is set, the block sends an - /// error interrupt whenever the TX FIFO overflows. - #[inline(always)] - pub fn overflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Underflow Errors: If this bit is set, the block sends an - /// error interrupt whenever there is a read from !!RXDATA - /// but the RX FIFO is empty. - #[inline(always)] - pub fn underflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Invalid Command Errors: If this bit is set, the block sends an - /// error interrupt whenever a command is sent with invalid values for - /// !!COMMAND.SPEED or !!COMMAND.DIRECTION. - #[inline(always)] - pub fn cmdinval(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Invalid CSID: If this bit is set, the block sends an error interrupt whenever - /// a command is submitted, but CSID exceeds NumCS. - #[inline(always)] - pub fn csidinval(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - } - impl From for ErrorEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorStatusReadVal(u32); - impl ErrorStatusReadVal { - /// Indicates a write to !!COMMAND when !!STATUS.READY = 0. - #[inline(always)] - pub fn cmdbusy(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Indicates that firmware has overflowed the TX FIFO - #[inline(always)] - pub fn overflow(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Indicates that firmware has attempted to read from - /// !!RXDATA when the RX FIFO is empty. - #[inline(always)] - pub fn underflow(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Indicates an invalid command segment, meaning either an invalid value of - /// !!COMMAND.SPEED or a request for bidirectional data transfer at dual or quad - /// speed - #[inline(always)] - pub fn cmdinval(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Indicates a command was attempted with an invalid value for !!CSID. - #[inline(always)] - pub fn csidinval(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Indicates that TLUL attempted to write to TXDATA with no bytes enabled. Such - /// 'zero byte' writes are not supported. - #[inline(always)] - pub fn accessinval(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> ErrorStatusWriteVal { - ErrorStatusWriteVal(self.0) - } - } - impl From for ErrorStatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorStatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ErrorStatusWriteVal(u32); - impl ErrorStatusWriteVal { - /// Indicates a write to !!COMMAND when !!STATUS.READY = 0. - #[inline(always)] - pub fn cmdbusy(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Indicates that firmware has overflowed the TX FIFO - #[inline(always)] - pub fn overflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Indicates that firmware has attempted to read from - /// !!RXDATA when the RX FIFO is empty. - #[inline(always)] - pub fn underflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Indicates an invalid command segment, meaning either an invalid value of - /// !!COMMAND.SPEED or a request for bidirectional data transfer at dual or quad - /// speed - #[inline(always)] - pub fn cmdinval(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Indicates a command was attempted with an invalid value for !!CSID. - #[inline(always)] - pub fn csidinval(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Indicates that TLUL attempted to write to TXDATA with no bytes enabled. Such - /// 'zero byte' writes are not supported. - #[inline(always)] - pub fn accessinval(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - } - impl From for ErrorStatusWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ErrorStatusWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct EventEnableReadVal(u32); - impl EventEnableReadVal { - /// Assert to send a spi_event interrupt whenever !!STATUS.RXFULL - /// goes high - #[inline(always)] - pub fn rxfull(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Assert to send a spi_event interrupt whenever !!STATUS.TXEMPTY - /// goes high - #[inline(always)] - pub fn txempty(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Assert to send a spi_event interrupt whenever the number of 32-bit words in - /// the RX FIFO is greater than !!CONTROL.RX_WATERMARK. To prevent the - /// reassertion of this interrupt, read more data from the RX FIFO, or - /// increase !!CONTROL.RX_WATERMARK. - #[inline(always)] - pub fn rxwm(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Assert to send a spi_event interrupt whenever the number of 32-bit words in - /// the TX FIFO is less than !!CONTROL.TX_WATERMARK. To prevent the - /// reassertion of this interrupt add more data to the TX FIFO, or - /// reduce !!CONTROL.TX_WATERMARK. - #[inline(always)] - pub fn txwm(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Assert to send a spi_event interrupt whenever !!STATUS.READY - /// goes high - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Assert to send a spi_event interrupt whenever !!STATUS.ACTIVE - /// goes low - #[inline(always)] - pub fn idle(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> EventEnableWriteVal { - EventEnableWriteVal(self.0) - } - } - impl From for EventEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: EventEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct EventEnableWriteVal(u32); - impl EventEnableWriteVal { - /// Assert to send a spi_event interrupt whenever !!STATUS.RXFULL - /// goes high - #[inline(always)] - pub fn rxfull(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Assert to send a spi_event interrupt whenever !!STATUS.TXEMPTY - /// goes high - #[inline(always)] - pub fn txempty(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Assert to send a spi_event interrupt whenever the number of 32-bit words in - /// the RX FIFO is greater than !!CONTROL.RX_WATERMARK. To prevent the - /// reassertion of this interrupt, read more data from the RX FIFO, or - /// increase !!CONTROL.RX_WATERMARK. - #[inline(always)] - pub fn rxwm(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Assert to send a spi_event interrupt whenever the number of 32-bit words in - /// the TX FIFO is less than !!CONTROL.TX_WATERMARK. To prevent the - /// reassertion of this interrupt add more data to the TX FIFO, or - /// reduce !!CONTROL.TX_WATERMARK. - #[inline(always)] - pub fn txwm(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Assert to send a spi_event interrupt whenever !!STATUS.READY - /// goes high - #[inline(always)] - pub fn ready(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Assert to send a spi_event interrupt whenever !!STATUS.ACTIVE - /// goes low - #[inline(always)] - pub fn idle(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - } - impl From for EventEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: EventEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableReadVal(u32); - impl InterruptEnableReadVal { - /// Enable interrupt when error is set. - #[inline(always)] - pub fn error(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable interrupt when spi_event is set. - #[inline(always)] - pub fn spi_event(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptEnableWriteVal { - InterruptEnableWriteVal(self.0) - } - } - impl From for InterruptEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableWriteVal(u32); - impl InterruptEnableWriteVal { - /// Enable interrupt when error is set. - #[inline(always)] - pub fn error(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable interrupt when spi_event is set. - #[inline(always)] - pub fn spi_event(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for InterruptEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateReadVal(u32); - impl InterruptStateReadVal { - /// Error-related interrupts, see !!ERROR_ENABLE register for more - /// information. - #[inline(always)] - pub fn error(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Event-related interrupts, see !!EVENT_ENABLE register for more - /// information. - #[inline(always)] - pub fn spi_event(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptStateWriteVal { - InterruptStateWriteVal(self.0) - } - } - impl From for InterruptStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateWriteVal(u32); - impl InterruptStateWriteVal { - /// Error-related interrupts, see !!ERROR_ENABLE register for more - /// information. - #[inline(always)] - pub fn error(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Event-related interrupts, see !!EVENT_ENABLE register for more - /// information. - #[inline(always)] - pub fn spi_event(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for InterruptStateWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptTestWriteVal(u32); - impl InterruptTestWriteVal { - /// Write 1 to force error to 1. - #[inline(always)] - pub fn error(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write 1 to force spi_event to 1. - #[inline(always)] - pub fn spi_event(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for InterruptTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// Transmit queue depth. Indicates how many unsent 32-bit words - /// are currently in the TX FIFO. When active, this result may - /// be an overestimate due to synchronization delays, - #[inline(always)] - pub fn txqd(&self) -> u32 { - (self.0 >> 0) & 0xff - } - /// Receive queue depth. Indicates how many unread 32-bit words are - /// currently in the RX FIFO. When active, this result may an - /// underestimate due to synchronization delays. - #[inline(always)] - pub fn rxqd(&self) -> u32 { - (self.0 >> 8) & 0xff - } - /// Command queue depth. Indicates how many unread 32-bit words are - /// currently in the command segment queue. - #[inline(always)] - pub fn cmdqd(&self) -> u32 { - (self.0 >> 16) & 0xf - } - /// If high, the number of 32-bits in the RX FIFO now exceeds the - /// !!CONTROL.RX_WATERMARK entries (32b each). - #[inline(always)] - pub fn rxwm(&self) -> bool { - ((self.0 >> 20) & 1) != 0 - } - /// The value of the ByteOrder parameter, provided so that firmware - /// can confirm proper IP configuration. - #[inline(always)] - pub fn byteorder(&self) -> bool { - ((self.0 >> 22) & 1) != 0 - } - /// If high, signifies that an ongoing transaction has stalled - /// due to lack of available space in the RX FIFO - #[inline(always)] - pub fn rxstall(&self) -> bool { - ((self.0 >> 23) & 1) != 0 - } - /// When high, indicates that the receive fifo is empty. - /// Any reads from RX FIFO will cause an error interrupt. - #[inline(always)] - pub fn rxempty(&self) -> bool { - ((self.0 >> 24) & 1) != 0 - } - /// When high, indicates that the receive fifo is full. Any - /// ongoing transactions will stall until firmware reads some - /// data from !!RXDATA. - #[inline(always)] - pub fn rxfull(&self) -> bool { - ((self.0 >> 25) & 1) != 0 - } - /// If high, the amount of data in the TX FIFO has fallen below the - /// level of !!CONTROL.TX_WATERMARK words (32b each). - #[inline(always)] - pub fn txwm(&self) -> bool { - ((self.0 >> 26) & 1) != 0 - } - /// If high, signifies that an ongoing transaction has stalled - /// due to lack of data in the TX FIFO - #[inline(always)] - pub fn txstall(&self) -> bool { - ((self.0 >> 27) & 1) != 0 - } - /// When high, indicates that the transmit data fifo is empty. - #[inline(always)] - pub fn txempty(&self) -> bool { - ((self.0 >> 28) & 1) != 0 - } - /// When high, indicates that the transmit data fifo is full. - /// Any further writes to !!RXDATA will create an error interrupt. - #[inline(always)] - pub fn txfull(&self) -> bool { - ((self.0 >> 29) & 1) != 0 - } - /// When high, indicates the SPI host is processing a previously - /// issued command. - #[inline(always)] - pub fn active(&self) -> bool { - ((self.0 >> 30) & 1) != 0 - } - /// When high, indicates the SPI host is ready to receive - /// commands. Writing to COMMAND when READY is low is - /// an error, and will trigger an interrupt. - #[inline(always)] - pub fn ready(&self) -> bool { - ((self.0 >> 31) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type InterruptState = ureg::ReadWriteReg32< - 0, - crate::spi_host::regs::InterruptStateReadVal, - crate::spi_host::regs::InterruptStateWriteVal, - >; - pub type InterruptEnable = ureg::ReadWriteReg32< - 0, - crate::spi_host::regs::InterruptEnableReadVal, - crate::spi_host::regs::InterruptEnableWriteVal, - >; - pub type InterruptTest = ureg::WriteOnlyReg32<0, crate::spi_host::regs::InterruptTestWriteVal>; - pub type AlertTest = ureg::WriteOnlyReg32<0, crate::spi_host::regs::AlertTestWriteVal>; - pub type Control = ureg::ReadWriteReg32< - 0x7f, - crate::spi_host::regs::ControlReadVal, - crate::spi_host::regs::ControlWriteVal, - >; - pub type Status = ureg::ReadOnlyReg32; - pub type Configopts = ureg::ReadWriteReg32< - 0, - crate::spi_host::regs::ConfigoptsReadVal, - crate::spi_host::regs::ConfigoptsWriteVal, - >; - pub type Csid = ureg::ReadWriteReg32<0, u32, u32>; - pub type Command = ureg::WriteOnlyReg32<0, crate::spi_host::regs::CommandWriteVal>; - pub type Rxdata = ureg::ReadOnlyReg32; - pub type Txdata = ureg::WriteOnlyReg32<0, u32>; - pub type ErrorEnable = ureg::ReadWriteReg32< - 0x1f, - crate::spi_host::regs::ErrorEnableReadVal, - crate::spi_host::regs::ErrorEnableWriteVal, - >; - pub type ErrorStatus = ureg::ReadWriteReg32< - 0, - crate::spi_host::regs::ErrorStatusReadVal, - crate::spi_host::regs::ErrorStatusWriteVal, - >; - pub type EventEnable = ureg::ReadWriteReg32< - 0, - crate::spi_host::regs::EventEnableReadVal, - crate::spi_host::regs::EventEnableWriteVal, - >; -} diff --git a/hw/1.0/registers/src/uart.rs b/hw/1.0/registers/src/uart.rs deleted file mode 100644 index 20ff017590..0000000000 --- a/hw/1.0/registers/src/uart.rs +++ /dev/null @@ -1,1036 +0,0 @@ -// Licensed under the Apache-2.0 license. -// -// generated by caliptra_registers_generator with caliptra-rtl repo at 7c953512251707d6f77d7d9a2f6be186ed013d50 -// -#![allow(clippy::erasing_op)] -#![allow(clippy::identity_op)] -/// A zero-sized type that represents ownership of this -/// peripheral, used to get access to a Register lock. Most -/// programs create one of these in unsafe code near the top of -/// main(), and pass it to the driver responsible for managing -/// all access to the hardware. -pub struct Uart { - _priv: (), -} -impl Uart { - pub const PTR: *mut u32 = 0x20001000 as *mut u32; - /// # Safety - /// - /// Caller must ensure that all concurrent use of this - /// peripheral in the firmware is done so in a compatible - /// way. The simplest way to enforce this is to only call - /// this function once. - #[inline(always)] - pub unsafe fn new() -> Self { - Self { _priv: () } - } - /// Returns a register block that can be used to read - /// registers from this peripheral, but cannot write. - #[inline(always)] - pub fn regs(&self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } - /// Return a register block that can be used to read and - /// write this peripheral's registers. - #[inline(always)] - pub fn regs_mut(&mut self) -> RegisterBlock { - RegisterBlock { - ptr: Self::PTR, - mmio: core::default::Default::default(), - } - } -} -#[derive(Clone, Copy)] -pub struct RegisterBlock> { - ptr: *mut u32, - mmio: TMmio, -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new(ptr: *mut u32) -> Self { - Self { - ptr, - mmio: core::default::Default::default(), - } - } -} -impl RegisterBlock { - /// # Safety - /// - /// The caller is responsible for ensuring that ptr is valid for - /// volatile reads and writes at any of the offsets in this register - /// block. - #[inline(always)] - pub unsafe fn new_with_mmio(ptr: *mut u32, mmio: TMmio) -> Self { - Self { ptr, mmio } - } - /// Read value: [`uart::regs::InterruptStateReadVal`]; Write value: [`uart::regs::InterruptStateWriteVal`] - #[inline(always)] - pub fn interrupt_state(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::InterruptEnableReadVal`]; Write value: [`uart::regs::InterruptEnableWriteVal`] - #[inline(always)] - pub fn interrupt_enable(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(4 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::InterruptTestReadVal`]; Write value: [`uart::regs::InterruptTestWriteVal`] - #[inline(always)] - pub fn interrupt_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(8 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::AlertTestReadVal`]; Write value: [`uart::regs::AlertTestWriteVal`] - #[inline(always)] - pub fn alert_test(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0xc / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::CtrlReadVal`]; Write value: [`uart::regs::CtrlWriteVal`] - #[inline(always)] - pub fn ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x10 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::StatusReadVal`]; Write value: [`uart::regs::StatusWriteVal`] - #[inline(always)] - pub fn status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x14 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::RdataReadVal`]; Write value: [`uart::regs::RdataWriteVal`] - #[inline(always)] - pub fn rdata(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x18 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::WdataReadVal`]; Write value: [`uart::regs::WdataWriteVal`] - #[inline(always)] - pub fn wdata(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x1c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::FifoCtrlReadVal`]; Write value: [`uart::regs::FifoCtrlWriteVal`] - #[inline(always)] - pub fn fifo_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x20 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::FifoStatusReadVal`]; Write value: [`uart::regs::FifoStatusWriteVal`] - #[inline(always)] - pub fn fifo_status(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x24 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::OvrdReadVal`]; Write value: [`uart::regs::OvrdWriteVal`] - #[inline(always)] - pub fn ovrd(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x28 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::ValReadVal`]; Write value: [`uart::regs::ValWriteVal`] - #[inline(always)] - pub fn val(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x2c / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } - /// Read value: [`uart::regs::TimeoutCtrlReadVal`]; Write value: [`uart::regs::TimeoutCtrlWriteVal`] - #[inline(always)] - pub fn timeout_ctrl(&self) -> ureg::RegRef { - unsafe { - ureg::RegRef::new_with_mmio( - self.ptr.wrapping_add(0x30 / core::mem::size_of::()), - core::borrow::Borrow::borrow(&self.mmio), - ) - } - } -} -pub mod regs { - //! Types that represent the values held by registers. - #[derive(Clone, Copy)] - pub struct AlertTestWriteVal(u32); - impl AlertTestWriteVal { - /// Write 1 to trigger one alert event of this kind. - #[inline(always)] - pub fn fatal_fault(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - } - impl From for AlertTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: AlertTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CtrlReadVal(u32); - impl CtrlReadVal { - /// TX enable - #[inline(always)] - pub fn tx(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// RX enable - #[inline(always)] - pub fn rx(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// RX noise filter enable. - /// If the noise filter is enabled, RX line goes through the 3-tap - /// repetition code. It ignores single IP clock period noise. - #[inline(always)] - pub fn nf(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// System loopback enable. - /// - /// If this bit is turned on, any outgoing bits to TX are received through RX. - /// See Block Diagram. Note that the TX line goes 1 if System loopback is enabled. - #[inline(always)] - pub fn slpbk(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Line loopback enable. - /// - /// If this bit is turned on, incoming bits are forwarded to TX for testing purpose. - /// See Block Diagram. Note that the internal design sees RX value as 1 always if line - /// loopback is enabled. - #[inline(always)] - pub fn llpbk(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// If true, parity is enabled in both RX and TX directions. - #[inline(always)] - pub fn parity_en(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even. - #[inline(always)] - pub fn parity_odd(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// Trigger level for RX break detection. Sets the number of character - /// times the line must be low to detect a break. - #[inline(always)] - pub fn rxblvl(&self) -> u32 { - (self.0 >> 8) & 3 - } - /// BAUD clock rate control. - #[inline(always)] - pub fn nco(&self) -> u32 { - (self.0 >> 16) & 0xffff - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> CtrlWriteVal { - CtrlWriteVal(self.0) - } - } - impl From for CtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct CtrlWriteVal(u32); - impl CtrlWriteVal { - /// TX enable - #[inline(always)] - pub fn tx(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// RX enable - #[inline(always)] - pub fn rx(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// RX noise filter enable. - /// If the noise filter is enabled, RX line goes through the 3-tap - /// repetition code. It ignores single IP clock period noise. - #[inline(always)] - pub fn nf(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// System loopback enable. - /// - /// If this bit is turned on, any outgoing bits to TX are received through RX. - /// See Block Diagram. Note that the TX line goes 1 if System loopback is enabled. - #[inline(always)] - pub fn slpbk(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Line loopback enable. - /// - /// If this bit is turned on, incoming bits are forwarded to TX for testing purpose. - /// See Block Diagram. Note that the internal design sees RX value as 1 always if line - /// loopback is enabled. - #[inline(always)] - pub fn llpbk(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// If true, parity is enabled in both RX and TX directions. - #[inline(always)] - pub fn parity_en(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even. - #[inline(always)] - pub fn parity_odd(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - /// Trigger level for RX break detection. Sets the number of character - /// times the line must be low to detect a break. - #[inline(always)] - pub fn rxblvl(self, val: u32) -> Self { - Self((self.0 & !(3 << 8)) | ((val & 3) << 8)) - } - /// BAUD clock rate control. - #[inline(always)] - pub fn nco(self, val: u32) -> Self { - Self((self.0 & !(0xffff << 16)) | ((val & 0xffff) << 16)) - } - } - impl From for CtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: CtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FifoCtrlReadVal(u32); - impl FifoCtrlReadVal { - /// RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0 - #[inline(always)] - pub fn rxrst(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0 - #[inline(always)] - pub fn txrst(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Trigger level for RX interrupts. If the FIFO depth is greater than or equal to - /// the setting, it raises rx_watermark interrupt. - #[inline(always)] - pub fn rxilvl(&self) -> u32 { - (self.0 >> 2) & 7 - } - /// Trigger level for TX interrupts. If the FIFO depth is less than the setting, it - /// raises tx_watermark interrupt. - #[inline(always)] - pub fn txilvl(&self) -> u32 { - (self.0 >> 5) & 3 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> FifoCtrlWriteVal { - FifoCtrlWriteVal(self.0) - } - } - impl From for FifoCtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FifoCtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FifoCtrlWriteVal(u32); - impl FifoCtrlWriteVal { - /// RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0 - #[inline(always)] - pub fn rxrst(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0 - #[inline(always)] - pub fn txrst(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Trigger level for RX interrupts. If the FIFO depth is greater than or equal to - /// the setting, it raises rx_watermark interrupt. - #[inline(always)] - pub fn rxilvl(self, val: u32) -> Self { - Self((self.0 & !(7 << 2)) | ((val & 7) << 2)) - } - /// Trigger level for TX interrupts. If the FIFO depth is less than the setting, it - /// raises tx_watermark interrupt. - #[inline(always)] - pub fn txilvl(self, val: u32) -> Self { - Self((self.0 & !(3 << 5)) | ((val & 3) << 5)) - } - } - impl From for FifoCtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FifoCtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct FifoStatusReadVal(u32); - impl FifoStatusReadVal { - /// Current fill level of TX fifo - #[inline(always)] - pub fn txlvl(&self) -> u32 { - (self.0 >> 0) & 0x3f - } - /// Current fill level of RX fifo - #[inline(always)] - pub fn rxlvl(&self) -> u32 { - (self.0 >> 16) & 0x3f - } - } - impl From for FifoStatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: FifoStatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableReadVal(u32); - impl InterruptEnableReadVal { - /// Enable interrupt when tx_watermark is set. - #[inline(always)] - pub fn tx_watermark(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Enable interrupt when rx_watermark is set. - #[inline(always)] - pub fn rx_watermark(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Enable interrupt when tx_empty is set. - #[inline(always)] - pub fn tx_empty(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// Enable interrupt when rx_overflow is set. - #[inline(always)] - pub fn rx_overflow(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// Enable interrupt when rx_frame_err is set. - #[inline(always)] - pub fn rx_frame_err(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// Enable interrupt when rx_break_err is set. - #[inline(always)] - pub fn rx_break_err(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// Enable interrupt when rx_timeout is set. - #[inline(always)] - pub fn rx_timeout(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// Enable interrupt when rx_parity_err is set. - #[inline(always)] - pub fn rx_parity_err(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptEnableWriteVal { - InterruptEnableWriteVal(self.0) - } - } - impl From for InterruptEnableReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptEnableWriteVal(u32); - impl InterruptEnableWriteVal { - /// Enable interrupt when tx_watermark is set. - #[inline(always)] - pub fn tx_watermark(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Enable interrupt when rx_watermark is set. - #[inline(always)] - pub fn rx_watermark(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Enable interrupt when tx_empty is set. - #[inline(always)] - pub fn tx_empty(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Enable interrupt when rx_overflow is set. - #[inline(always)] - pub fn rx_overflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Enable interrupt when rx_frame_err is set. - #[inline(always)] - pub fn rx_frame_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Enable interrupt when rx_break_err is set. - #[inline(always)] - pub fn rx_break_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// Enable interrupt when rx_timeout is set. - #[inline(always)] - pub fn rx_timeout(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// Enable interrupt when rx_parity_err is set. - #[inline(always)] - pub fn rx_parity_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - } - impl From for InterruptEnableWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptEnableWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateReadVal(u32); - impl InterruptStateReadVal { - /// raised if the transmit FIFO is past the high-water mark. - #[inline(always)] - pub fn tx_watermark(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// raised if the receive FIFO is past the high-water mark. - #[inline(always)] - pub fn rx_watermark(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// raised if the transmit FIFO has emptied and no transmit is ongoing. - #[inline(always)] - pub fn tx_empty(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// raised if the receive FIFO has overflowed. - #[inline(always)] - pub fn rx_overflow(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// raised if a framing error has been detected on receive. - #[inline(always)] - pub fn rx_frame_err(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// raised if break condition has been detected on receive. - #[inline(always)] - pub fn rx_break_err(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - /// raised if RX FIFO has characters remaining in the FIFO without being - /// retrieved for the programmed time period. - #[inline(always)] - pub fn rx_timeout(&self) -> bool { - ((self.0 >> 6) & 1) != 0 - } - /// raised if the receiver has detected a parity error. - #[inline(always)] - pub fn rx_parity_err(&self) -> bool { - ((self.0 >> 7) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> InterruptStateWriteVal { - InterruptStateWriteVal(self.0) - } - } - impl From for InterruptStateReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptStateWriteVal(u32); - impl InterruptStateWriteVal { - /// raised if the transmit FIFO is past the high-water mark. - #[inline(always)] - pub fn tx_watermark(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// raised if the receive FIFO is past the high-water mark. - #[inline(always)] - pub fn rx_watermark(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// raised if the transmit FIFO has emptied and no transmit is ongoing. - #[inline(always)] - pub fn tx_empty(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// raised if the receive FIFO has overflowed. - #[inline(always)] - pub fn rx_overflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// raised if a framing error has been detected on receive. - #[inline(always)] - pub fn rx_frame_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// raised if break condition has been detected on receive. - #[inline(always)] - pub fn rx_break_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// raised if RX FIFO has characters remaining in the FIFO without being - /// retrieved for the programmed time period. - #[inline(always)] - pub fn rx_timeout(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// raised if the receiver has detected a parity error. - #[inline(always)] - pub fn rx_parity_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - } - impl From for InterruptStateWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptStateWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct InterruptTestWriteVal(u32); - impl InterruptTestWriteVal { - /// Write 1 to force tx_watermark to 1. - #[inline(always)] - pub fn tx_watermark(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write 1 to force rx_watermark to 1. - #[inline(always)] - pub fn rx_watermark(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - /// Write 1 to force tx_empty to 1. - #[inline(always)] - pub fn tx_empty(self, val: bool) -> Self { - Self((self.0 & !(1 << 2)) | (u32::from(val) << 2)) - } - /// Write 1 to force rx_overflow to 1. - #[inline(always)] - pub fn rx_overflow(self, val: bool) -> Self { - Self((self.0 & !(1 << 3)) | (u32::from(val) << 3)) - } - /// Write 1 to force rx_frame_err to 1. - #[inline(always)] - pub fn rx_frame_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 4)) | (u32::from(val) << 4)) - } - /// Write 1 to force rx_break_err to 1. - #[inline(always)] - pub fn rx_break_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 5)) | (u32::from(val) << 5)) - } - /// Write 1 to force rx_timeout to 1. - #[inline(always)] - pub fn rx_timeout(self, val: bool) -> Self { - Self((self.0 & !(1 << 6)) | (u32::from(val) << 6)) - } - /// Write 1 to force rx_parity_err to 1. - #[inline(always)] - pub fn rx_parity_err(self, val: bool) -> Self { - Self((self.0 & !(1 << 7)) | (u32::from(val) << 7)) - } - } - impl From for InterruptTestWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: InterruptTestWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct OvrdReadVal(u32); - impl OvrdReadVal { - /// Enable TX pin override control - #[inline(always)] - pub fn txen(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// Write to set the value of the TX pin - #[inline(always)] - pub fn txval(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> OvrdWriteVal { - OvrdWriteVal(self.0) - } - } - impl From for OvrdReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: OvrdReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct OvrdWriteVal(u32); - impl OvrdWriteVal { - /// Enable TX pin override control - #[inline(always)] - pub fn txen(self, val: bool) -> Self { - Self((self.0 & !(1 << 0)) | (u32::from(val) << 0)) - } - /// Write to set the value of the TX pin - #[inline(always)] - pub fn txval(self, val: bool) -> Self { - Self((self.0 & !(1 << 1)) | (u32::from(val) << 1)) - } - } - impl From for OvrdWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: OvrdWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct RdataReadVal(u32); - impl RdataReadVal { - /// UART read data - #[inline(always)] - pub fn rdata(&self) -> u32 { - (self.0 >> 0) & 0xff - } - } - impl From for RdataReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: RdataReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct StatusReadVal(u32); - impl StatusReadVal { - /// TX buffer is full - #[inline(always)] - pub fn txfull(&self) -> bool { - ((self.0 >> 0) & 1) != 0 - } - /// RX buffer is full - #[inline(always)] - pub fn rxfull(&self) -> bool { - ((self.0 >> 1) & 1) != 0 - } - /// TX FIFO is empty - #[inline(always)] - pub fn txempty(&self) -> bool { - ((self.0 >> 2) & 1) != 0 - } - /// TX FIFO is empty and all bits have been transmitted - #[inline(always)] - pub fn txidle(&self) -> bool { - ((self.0 >> 3) & 1) != 0 - } - /// RX is idle - #[inline(always)] - pub fn rxidle(&self) -> bool { - ((self.0 >> 4) & 1) != 0 - } - /// RX FIFO is empty - #[inline(always)] - pub fn rxempty(&self) -> bool { - ((self.0 >> 5) & 1) != 0 - } - } - impl From for StatusReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: StatusReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct TimeoutCtrlReadVal(u32); - impl TimeoutCtrlReadVal { - /// RX timeout value in UART bit times - #[inline(always)] - pub fn val(&self) -> u32 { - (self.0 >> 0) & 0xffffff - } - /// Enable RX timeout feature - #[inline(always)] - pub fn en(&self) -> bool { - ((self.0 >> 31) & 1) != 0 - } - /// Construct a WriteVal that can be used to modify the contents of this register value. - #[inline(always)] - pub fn modify(self) -> TimeoutCtrlWriteVal { - TimeoutCtrlWriteVal(self.0) - } - } - impl From for TimeoutCtrlReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: TimeoutCtrlReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct TimeoutCtrlWriteVal(u32); - impl TimeoutCtrlWriteVal { - /// RX timeout value in UART bit times - #[inline(always)] - pub fn val(self, val: u32) -> Self { - Self((self.0 & !(0xffffff << 0)) | ((val & 0xffffff) << 0)) - } - /// Enable RX timeout feature - #[inline(always)] - pub fn en(self, val: bool) -> Self { - Self((self.0 & !(1 << 31)) | (u32::from(val) << 31)) - } - } - impl From for TimeoutCtrlWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: TimeoutCtrlWriteVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct ValReadVal(u32); - impl ValReadVal { - /// Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15. - #[inline(always)] - pub fn rx(&self) -> u32 { - (self.0 >> 0) & 0xffff - } - } - impl From for ValReadVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: ValReadVal) -> u32 { - val.0 - } - } - #[derive(Clone, Copy)] - pub struct WdataWriteVal(u32); - impl WdataWriteVal { - /// UART write data - #[inline(always)] - pub fn wdata(self, val: u32) -> Self { - Self((self.0 & !(0xff << 0)) | ((val & 0xff) << 0)) - } - } - impl From for WdataWriteVal { - #[inline(always)] - fn from(val: u32) -> Self { - Self(val) - } - } - impl From for u32 { - #[inline(always)] - fn from(val: WdataWriteVal) -> u32 { - val.0 - } - } -} -pub mod enums { - //! Enumerations used by some register fields. - pub mod selector {} -} -pub mod meta { - //! Additional metadata needed by ureg. - pub type InterruptState = ureg::ReadWriteReg32< - 0, - crate::uart::regs::InterruptStateReadVal, - crate::uart::regs::InterruptStateWriteVal, - >; - pub type InterruptEnable = ureg::ReadWriteReg32< - 0, - crate::uart::regs::InterruptEnableReadVal, - crate::uart::regs::InterruptEnableWriteVal, - >; - pub type InterruptTest = ureg::WriteOnlyReg32<0, crate::uart::regs::InterruptTestWriteVal>; - pub type AlertTest = ureg::WriteOnlyReg32<0, crate::uart::regs::AlertTestWriteVal>; - pub type Ctrl = - ureg::ReadWriteReg32<0, crate::uart::regs::CtrlReadVal, crate::uart::regs::CtrlWriteVal>; - pub type Status = ureg::ReadOnlyReg32; - pub type Rdata = ureg::ReadOnlyReg32; - pub type Wdata = ureg::WriteOnlyReg32<0, crate::uart::regs::WdataWriteVal>; - pub type FifoCtrl = ureg::ReadWriteReg32< - 0, - crate::uart::regs::FifoCtrlReadVal, - crate::uart::regs::FifoCtrlWriteVal, - >; - pub type FifoStatus = ureg::ReadOnlyReg32; - pub type Ovrd = - ureg::ReadWriteReg32<0, crate::uart::regs::OvrdReadVal, crate::uart::regs::OvrdWriteVal>; - pub type Val = ureg::ReadOnlyReg32; - pub type TimeoutCtrl = ureg::ReadWriteReg32< - 0, - crate::uart::regs::TimeoutCtrlReadVal, - crate::uart::regs::TimeoutCtrlWriteVal, - >; -} diff --git a/hw/1.0/rtl b/hw/1.0/rtl deleted file mode 160000 index 7c95351225..0000000000 --- a/hw/1.0/rtl +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7c953512251707d6f77d7d9a2f6be186ed013d50 diff --git a/hw/verilated/Makefile b/hw/verilated/Makefile index 501224a55f..5940d056c1 100644 --- a/hw/verilated/Makefile +++ b/hw/verilated/Makefile @@ -15,7 +15,7 @@ VERILATOR = verilator VERILATED_DIR := $(dir $(realpath $(lastword $(MAKEFILE_LIST)))) -CALIPTRA_RTL_DIR := $(realpath $(VERILATED_DIR)../1.0/rtl) +CALIPTRA_RTL_DIR := $(realpath $(VERILATED_DIR)../latest/rtl) CFLAGS := -std=c++11 -fno-exceptions -fPIC VERILATOR_MAKE_FLAGS = OPT_FAST="-Os" @@ -26,7 +26,7 @@ VERILATOR_OBJS = out/verilated_threads.o out/verilated.o out/verilated_vcd_c.o LIB_OBJS = out/caliptra_verilated.o -export CALIPTRA_ROOT = $(realpath ../1.0/rtl) +export CALIPTRA_ROOT = $(realpath ../latest/rtl) suppress = -Wno-WIDTH -Wno-UNOPTFLAT -Wno-LITENDIAN -Wno-CMPCONST -Wno-MULTIDRIVEN -Wno-UNPACKED diff --git a/hw/verilated/build.rs b/hw/verilated/build.rs index ed3e4629f4..365ba0588c 100644 --- a/hw/verilated/build.rs +++ b/hw/verilated/build.rs @@ -46,7 +46,7 @@ fn add_filename(filename: &Path) -> impl FnOnce(std::io::Error) -> std::io::Erro fn sv_files(manifest_dir: &Path) -> Result, std::io::Error> { let mut result = vec![]; - let filename = manifest_dir.join("../1.0/rtl/src/integration/config/caliptra_top_tb.vf"); + let filename = manifest_dir.join("../latest/rtl/src/integration/config/caliptra_top_tb.vf"); for line in BufReader::new(File::open(&filename).map_err(add_filename(&filename))?).lines() { let line = line?; if line.starts_with('+') { diff --git a/kat/Cargo.toml b/kat/Cargo.toml index 78e9c29121..b5d513e5d7 100644 --- a/kat/Cargo.toml +++ b/kat/Cargo.toml @@ -14,6 +14,3 @@ caliptra-drivers.workspace = true caliptra-lms-types.workspace = true zerocopy.workspace = true ufmt.workspace = true - -[features] -"hw-1.0" = ["caliptra-drivers/hw-1.0"] diff --git a/libcaliptra/Makefile b/libcaliptra/Makefile index efdae83e88..7b1d6bd7cf 100644 --- a/libcaliptra/Makefile +++ b/libcaliptra/Makefile @@ -5,7 +5,7 @@ AR=$(CROSS_COMPILE)ar ifneq ($(MAKECMDGOALS),clean) ifndef RTL_SOC_IFC_INCLUDE_PATH -RTL_SOC_IFC_INCLUDE_PATH ?= ../hw/1.0/rtl/src/soc_ifc/rtl +RTL_SOC_IFC_INCLUDE_PATH ?= ../hw/latest/rtl/src/soc_ifc/rtl $(warning RTL_SOC_IFC_INCLUDE_PATH must be defined and point to a location where caliptra_top_reg.h can be found) $(warning Defaulting to $(RTL_SOC_IFC_INCLUDE_PATH)) diff --git a/libcaliptra/examples/generic/main.mk b/libcaliptra/examples/generic/main.mk index 5c71249364..fb0f766145 100644 --- a/libcaliptra/examples/generic/main.mk +++ b/libcaliptra/examples/generic/main.mk @@ -11,7 +11,7 @@ LIBCALIPTRA_INC = $(LIBCALIPTRA_ROOT)/inc OBJS := $(patsubst %.c,%.o, $(filter %.c,$(SOURCE))) # SOC REFERENCE -RTL_SOC_IFC_INCLUDE_PATH = ../../../hw/1.0/rtl/src/soc_ifc/rtl +RTL_SOC_IFC_INCLUDE_PATH = ../../../hw/latest/rtl/src/soc_ifc/rtl # INCLUDES INCLUDES += -I$(RTL_SOC_IFC_INCLUDE_PATH) -I$(LIBCALIPTRA_INC) -I./ diff --git a/registers/Cargo.toml b/registers/Cargo.toml index dee6166a54..b70f5f369a 100644 --- a/registers/Cargo.toml +++ b/registers/Cargo.toml @@ -8,8 +8,4 @@ edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] -caliptra-registers-1_0 = { workspace = true, optional = true } caliptra-registers-latest = { workspace = true } - -[features] -"hw-1.0" = ["dep:caliptra-registers-1_0"] diff --git a/registers/src/lib.rs b/registers/src/lib.rs index 5b00cc39f6..fd7b42e206 100644 --- a/registers/src/lib.rs +++ b/registers/src/lib.rs @@ -2,8 +2,4 @@ // #![no_std] -#[cfg(not(feature = "hw-1.0"))] pub use caliptra_registers_latest::*; - -#[cfg(feature = "hw-1.0")] -pub use caliptra_registers_1_0::*; diff --git a/registers/update.sh b/registers/update.sh index 560daf06a5..37d183c1ec 100755 --- a/registers/update.sh +++ b/registers/update.sh @@ -3,11 +3,10 @@ cd "$(dirname "${BASH_SOURCE[0]}")" -if [[ ! -f "../hw/latest/rtl/.git" || ! -f "../hw/1.0/rtl/.git" ]]; then +if [[ ! -f "../hw/latest/rtl/.git" ]]; then echo "hw/*/rtl submodules are not populated" echo "Please run 'git submodule update --init'" exit 1 fi -cargo run --manifest-path bin/generator/Cargo.toml -- ../hw/1.0/rtl bin/extra-rdl/ ../hw/1.0/registers/src/ cargo run --manifest-path bin/generator/Cargo.toml -- ../hw/latest/rtl bin/extra-rdl/ ../hw/latest/registers/src/ diff --git a/rom/dev/Cargo.toml b/rom/dev/Cargo.toml index 7e1e8f880d..020be0d471 100644 --- a/rom/dev/Cargo.toml +++ b/rom/dev/Cargo.toml @@ -61,7 +61,6 @@ no-fmc = [] fake-rom = [] no-cfi = ["caliptra-image-verify/no-cfi", "caliptra-drivers/no-cfi"] slow_tests = [] -"hw-1.0" = ["caliptra-builder/hw-1.0", "caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0", "caliptra-hw-model/hw-1.0"] fips-test-hooks = ["caliptra-drivers/fips-test-hooks", "caliptra-image-verify/fips-test-hooks"] [[bin]] diff --git a/rom/dev/tests/rom_integration_tests/test_version.rs b/rom/dev/tests/rom_integration_tests/test_version.rs index 662a616d53..94ac52e5f2 100755 --- a/rom/dev/tests/rom_integration_tests/test_version.rs +++ b/rom/dev/tests/rom_integration_tests/test_version.rs @@ -12,7 +12,7 @@ use crate::helpers; // TODO: Find a better way to get this or make it a don't-care for this test // This is not going to work when we start testing against multiple hw revs -const HW_REV_ID: u32 = if cfg!(feature = "hw-1.0") { 0x1 } else { 0x11 }; +const HW_REV_ID: u32 = 0x11; // TODO 2.0 #[test] fn test_version() { diff --git a/rom/dev/tools/test-fmc/Cargo.toml b/rom/dev/tools/test-fmc/Cargo.toml index 0dfda43aa7..4abf6f390f 100644 --- a/rom/dev/tools/test-fmc/Cargo.toml +++ b/rom/dev/tools/test-fmc/Cargo.toml @@ -25,4 +25,3 @@ interactive_test_fmc = [] riscv = ["caliptra-cpu/riscv"] std = ["ufmt/std", "caliptra_common/std"] fake-fmc = [] -"hw-1.0" = ["caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0"] diff --git a/rom/dev/tools/test-rt/Cargo.toml b/rom/dev/tools/test-rt/Cargo.toml index f02210ff12..e2cd798759 100644 --- a/rom/dev/tools/test-rt/Cargo.toml +++ b/rom/dev/tools/test-rt/Cargo.toml @@ -18,4 +18,3 @@ default = ["std"] emu = ["caliptra-drivers/emu"] riscv = ["caliptra-cpu/riscv"] std = ["ufmt/std"] -"hw-1.0" = ["caliptra-drivers/hw-1.0", "caliptra-cpu/hw-1.0"] diff --git a/runtime/Cargo.toml b/runtime/Cargo.toml index 8f5469f5fe..271f24b581 100644 --- a/runtime/Cargo.toml +++ b/runtime/Cargo.toml @@ -62,5 +62,4 @@ verilator = ["caliptra-hw-model/verilator"] fips_self_test=[] no-cfi = ["caliptra-image-verify/no-cfi", "caliptra-drivers/no-cfi"] fpga_realtime = ["caliptra-drivers/fpga_realtime"] -"hw-1.0" = ["caliptra-builder/hw-1.0", "caliptra-drivers/hw-1.0", "caliptra-registers/hw-1.0", "caliptra-kat/hw-1.0","caliptra-cpu/hw-1.0"] fips-test-hooks = ["caliptra-drivers/fips-test-hooks"] diff --git a/runtime/test-fw/Cargo.toml b/runtime/test-fw/Cargo.toml index 6d540d4e68..75acc16088 100644 --- a/runtime/test-fw/Cargo.toml +++ b/runtime/test-fw/Cargo.toml @@ -18,7 +18,6 @@ emu = [ "caliptra-test-harness/emu", ] fpga_realtime = ["caliptra-runtime/fpga_realtime"] -"hw-1.0" = ["caliptra-drivers/hw-1.0"] [[bin]] name = "boot" diff --git a/runtime/tests/runtime_integration_tests/test_fips.rs b/runtime/tests/runtime_integration_tests/test_fips.rs index 16108c4392..9c66477068 100644 --- a/runtime/tests/runtime_integration_tests/test_fips.rs +++ b/runtime/tests/runtime_integration_tests/test_fips.rs @@ -9,7 +9,7 @@ use caliptra_hw_model::HwModel; use caliptra_runtime::FipsVersionCmd; use zerocopy::{AsBytes, FromBytes}; -const HW_REV_ID: u32 = if cfg!(feature = "hw-1.0") { 0x1 } else { 0x11 }; +const HW_REV_ID: u32 = 0x11; // TODO 2.0 #[test] fn test_fips_version() { diff --git a/sw-emulator/lib/periph/Cargo.toml b/sw-emulator/lib/periph/Cargo.toml index 2e76b96140..a0a4808874 100644 --- a/sw-emulator/lib/periph/Cargo.toml +++ b/sw-emulator/lib/periph/Cargo.toml @@ -25,6 +25,3 @@ sha3.workspace = true smlang.workspace = true tock-registers.workspace = true zerocopy.workspace = true - -[features] -"hw-1.0" = [] diff --git a/sw-emulator/lib/periph/src/soc_reg.rs b/sw-emulator/lib/periph/src/soc_reg.rs index 73656051f1..ba88269513 100644 --- a/sw-emulator/lib/periph/src/soc_reg.rs +++ b/sw-emulator/lib/periph/src/soc_reg.rs @@ -812,11 +812,7 @@ impl SocRegistersImpl { cptra_clk_gating_en: ReadOnlyRegister::new(0), cptra_generic_input_wires: Default::default(), cptra_generic_output_wires: Default::default(), - cptra_hw_rev_id: ReadOnlyRegister::new(if cfg!(feature = "hw-1.0") { - 0x1 - } else { - 0x11 - }), + cptra_hw_rev_id: ReadOnlyRegister::new(0x11), // TODO 2.0 cptra_fw_rev_id: Default::default(), cptra_hw_config: 0, fuse_uds_seed: words_from_bytes_be(&Self::UDS), diff --git a/test/Cargo.toml b/test/Cargo.toml index 95f4309e01..be31310b1d 100644 --- a/test/Cargo.toml +++ b/test/Cargo.toml @@ -42,4 +42,3 @@ itrng = ["caliptra-hw-model/itrng"] verilator = ["caliptra-hw-model/verilator"] fips_self_test = ["caliptra-runtime/fips_self_test"] test_env_immutable_rom = [] -"hw-1.0" = ["caliptra-builder/hw-1.0", "caliptra-drivers/hw-1.0", "caliptra-hw-model/hw-1.0"] diff --git a/test/tests/fips_test_suite/jtag_locked.rs b/test/tests/fips_test_suite/jtag_locked.rs index ac8fd08984..bac97fc2c9 100644 --- a/test/tests/fips_test_suite/jtag_locked.rs +++ b/test/tests/fips_test_suite/jtag_locked.rs @@ -48,11 +48,7 @@ fn jtag_locked() { &rom, true, DeviceLifecycle::Manufacturing, - if cfg!(feature = "hw-1.0") { - Ok(()) - } else { - Err(OpenOcdError::VeerNotAccessible) - }, + Err(OpenOcdError::VeerNotAccessible), ); check_jtag_accessible( &rom,