-
Notifications
You must be signed in to change notification settings - Fork 9
/
DE2_115_SOPC.html
1460 lines (1459 loc) · 126 KB
/
DE2_115_SOPC.html
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>Report</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">DE2_115_SOPC</td>
<td class="r">DE2_115_SOPC
<br/>1.0
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2012.11.30.15:06:04</td>
<td class="r">Generation Report</td>
</tr>
</table>
<table class="items">
<tr>
<td class="label">Output Directory</td>
<td class="mono">D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/</td>
</tr>
<tr>
<td class="label">Files</td>
<td class="mono">D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/DE2_115_SOPC.v (766409 bytes VERILOG)
<br/>
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_timer.v (6954 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_sdram.v (23906 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_sdram_test_component.v (9449 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_key.v (4399 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_sma_in.v (1951 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_sma_out.v (2281 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_sw.v (8623 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_ledg.v (2252 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_ledr.v (2255 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_lcd.v (2291 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/TERASIC_SRAM.v (1658 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/SEG7_IF.v (3786 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_jtag_uart.v (24243 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_jtag_uart_input_mutex.dat (3 bytes OTHER)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_jtag_uart_input_stream.dat (10 bytes OTHER)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_jtag_uart_output_stream.dat (0 bytes OTHER)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_pll.v (11687 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_timer_stamp.v (7028 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/VGA_NIOS_CTRL.v (7387 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/VGA_OSD_RAM.v (1703 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/VGA_Controller.v (6394 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/Img_RAM.v (9939 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v (10052 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_avalon_dc_fifo.v (23570 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v (1458 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu.ocp (856 bytes OTHER)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu.sdc (3979 bytes SDC)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu.v (446272 bytes VERILOG_ENCRYPT)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_bht_ram.mif (2392 bytes MIF)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_dc_tag_ram.mif (920 bytes MIF)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_ic_tag_ram.mif (1881 bytes MIF)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_jtag_debug_module_sysclk.v (7125 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_jtag_debug_module_tck.v (8459 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_jtag_debug_module_wrapper.v (10379 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_mult_cell.v (6299 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_ociram_default_contents.mif (5714 bytes MIF)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_oci_test_bench.v (1496 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_rf_ram_a.mif (600 bytes MIF)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_rf_ram_b.mif (600 bytes MIF)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cpu_test_bench.v (31723 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_sysid.v (1451 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/CY7C67200_IF.v (2109 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_master_translator.sv (16802 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_slave_translator.sv (16043 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_slave_agent.sv (19132 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10373 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_master_agent.sv (8686 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_addr_router.sv (6749 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_addr_router_001.sv (8742 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_id_router.sv (6055 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_id_router_002.sv (6067 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_id_router_003.sv (5985 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_addr_router_002.sv (8396 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_id_router_010.sv (5979 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_traffic_limiter.sv (12802 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_burst_adapter.sv (37064 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_reset_controller.v (3595 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cmd_xbar_demux.sv (4766 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cmd_xbar_demux_001.sv (9235 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cmd_xbar_mux.sv (11852 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_rsp_xbar_demux.sv (4121 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_rsp_xbar_demux_003.sv (3495 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_rsp_xbar_mux.sv (12056 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_rsp_xbar_mux_001.sv (17715 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_cmd_xbar_demux_002.sv (8573 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_rsp_xbar_demux_010.sv (3490 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_rsp_xbar_mux_002.sv (16893 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_merlin_width_adapter.sv (35859 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/DE2_115_SOPC_irq_mapper.sv (2169 bytes SYSTEM_VERILOG)
<br/>D:/SVN/DE2_115_CYPRESS/DEV/peli/DE2_115_NIOS_HOST_MOUSE_VGA/DE2_115_SOPC/synthesis/submodules/altera_irq_clock_crosser.sv (1651 bytes SYSTEM_VERILOG)
<br/>
</td>
</tr>
<tr>
<td class="label">Instantiations</td>
<td class="mono">
<table class="grid">
<tr>
<td><b>DE2_115_SOPC</b>
<br/>DE2_115_SOPC v1.0</td>
<td><b>DE2_115_SOPC_timer</b> as timer
<br/><b>DE2_115_SOPC_sdram</b> as sdram
<br/><b>DE2_115_SOPC_key</b> as key
<br/><b>DE2_115_SOPC_sma_in</b> as sma_in
<br/><b>DE2_115_SOPC_sma_out</b> as sma_out
<br/><b>DE2_115_SOPC_sw</b> as sw
<br/><b>DE2_115_SOPC_ledg</b> as ledg
<br/><b>DE2_115_SOPC_ledr</b> as ledr
<br/><b>DE2_115_SOPC_lcd</b> as lcd
<br/><b>TERASIC_SRAM</b> as sram
<br/><b>SEG7_IF</b> as seg7
<br/><b>DE2_115_SOPC_jtag_uart</b> as jtag_uart
<br/><b>DE2_115_SOPC_pll</b> as pll
<br/><b>DE2_115_SOPC_timer_stamp</b> as timer_stamp
<br/><b>VGA_NIOS_CTRL</b> as vpg
<br/><b>altera_avalon_mm_clock_crossing_bridge</b> as clock_crossing_io
<br/><b>DE2_115_SOPC_cpu</b> as cpu
<br/><b>DE2_115_SOPC_sysid</b> as sysid
<br/><b>CY7C67200_IF</b> as CY7C67200_IF_0
<br/><b>altera_merlin_master_translator</b> as cpu_instruction_master_translator, cpu_data_master_translator, clock_crossing_io_m0_translator
<br/><b>altera_merlin_slave_translator</b> as cpu_jtag_debug_module_translator, sdram_s1_translator, sram_avalon_slave_translator, sma_in_s1_translator, sma_out_s1_translator, jtag_uart_avalon_jtag_slave_translator, pll_pll_slave_translator, timer_stamp_s1_translator, timer_s1_translator, clock_crossing_io_s0_translator, sysid_control_slave_translator, key_s1_translator, sw_s1_translator, ledg_s1_translator, ledr_s1_translator, lcd_control_slave_translator, seg7_avalon_slave_translator, vpg_s1_translator, CY7C67200_IF_0_hpi_translator
<br/><b>altera_merlin_slave_agent</b> as sma_out_s1_translator_avalon_universal_slave_0_agent, pll_pll_slave_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, sdram_s1_translator_avalon_universal_slave_0_agent, timer_s1_translator_avalon_universal_slave_0_agent, sma_in_s1_translator_avalon_universal_slave_0_agent, sram_avalon_slave_translator_avalon_universal_slave_0_agent, timer_stamp_s1_translator_avalon_universal_slave_0_agent, clock_crossing_io_s0_translator_avalon_universal_slave_0_agent, CY7C67200_IF_0_hpi_translator_avalon_universal_slave_0_agent, ledr_s1_translator_avalon_universal_slave_0_agent, vpg_s1_translator_avalon_universal_slave_0_agent, sw_s1_translator_avalon_universal_slave_0_agent, seg7_avalon_slave_translator_avalon_universal_slave_0_agent, ledg_s1_translator_avalon_universal_slave_0_agent, key_s1_translator_avalon_universal_slave_0_agent, lcd_control_slave_translator_avalon_universal_slave_0_agent, sysid_control_slave_translator_avalon_universal_slave_0_agent
<br/><b>altera_avalon_sc_fifo</b> as sma_out_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo, sma_in_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sram_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_stamp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, clock_crossing_io_s0_translator_avalon_universal_slave_0_agent_rsp_fifo, CY7C67200_IF_0_hpi_translator_avalon_universal_slave_0_agent_rsp_fifo, ledr_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, vpg_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, vpg_s1_translator_avalon_universal_slave_0_agent_rdata_fifo, sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, seg7_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, ledg_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, lcd_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
<br/><b>altera_merlin_master_agent</b> as cpu_instruction_master_translator_avalon_universal_master_0_agent, cpu_data_master_translator_avalon_universal_master_0_agent, clock_crossing_io_m0_translator_avalon_universal_master_0_agent
<br/><b>DE2_115_SOPC_addr_router</b> as addr_router
<br/><b>DE2_115_SOPC_addr_router_001</b> as addr_router_001
<br/><b>DE2_115_SOPC_id_router</b> as id_router, id_router_001
<br/><b>DE2_115_SOPC_id_router_002</b> as id_router_002
<br/><b>DE2_115_SOPC_id_router_003</b> as id_router_003, id_router_004, id_router_005, id_router_006, id_router_007, id_router_008, id_router_009
<br/><b>DE2_115_SOPC_addr_router_002</b> as addr_router_002
<br/><b>DE2_115_SOPC_id_router_010</b> as id_router_010, id_router_011, id_router_012, id_router_013, id_router_014, id_router_015, id_router_016, id_router_017, id_router_018
<br/><b>altera_merlin_traffic_limiter</b> as limiter, limiter_001, limiter_002
<br/><b>altera_merlin_burst_adapter</b> as burst_adapter
<br/><b>altera_reset_controller</b> as rst_controller, rst_controller_001, rst_controller_002
<br/><b>DE2_115_SOPC_cmd_xbar_demux</b> as cmd_xbar_demux
<br/><b>DE2_115_SOPC_cmd_xbar_demux_001</b> as cmd_xbar_demux_001
<br/><b>DE2_115_SOPC_cmd_xbar_mux</b> as cmd_xbar_mux, cmd_xbar_mux_001, cmd_xbar_mux_002
<br/><b>DE2_115_SOPC_rsp_xbar_demux</b> as rsp_xbar_demux, rsp_xbar_demux_001, rsp_xbar_demux_002
<br/><b>DE2_115_SOPC_rsp_xbar_demux_003</b> as rsp_xbar_demux_003, rsp_xbar_demux_004, rsp_xbar_demux_005, rsp_xbar_demux_006, rsp_xbar_demux_007, rsp_xbar_demux_008, rsp_xbar_demux_009
<br/><b>DE2_115_SOPC_rsp_xbar_mux</b> as rsp_xbar_mux
<br/><b>DE2_115_SOPC_rsp_xbar_mux_001</b> as rsp_xbar_mux_001
<br/><b>DE2_115_SOPC_cmd_xbar_demux_002</b> as cmd_xbar_demux_002
<br/><b>DE2_115_SOPC_rsp_xbar_demux_010</b> as rsp_xbar_demux_010, rsp_xbar_demux_011, rsp_xbar_demux_012, rsp_xbar_demux_013, rsp_xbar_demux_014, rsp_xbar_demux_015, rsp_xbar_demux_016, rsp_xbar_demux_017, rsp_xbar_demux_018
<br/><b>DE2_115_SOPC_rsp_xbar_mux_002</b> as rsp_xbar_mux_002
<br/><b>altera_merlin_width_adapter</b> as width_adapter, width_adapter_001
<br/><b>altera_avalon_st_handshake_clock_crosser</b> as crosser, crosser_001, crosser_002, crosser_003, crosser_004, crosser_005
<br/><b>DE2_115_SOPC_irq_mapper</b> as irq_mapper
<br/><b>altera_irq_clock_crosser</b> as irq_synchronizer, irq_synchronizer_001, irq_synchronizer_002, irq_synchronizer_003
<br/>
</td>
</tr>
<tr>
<td><b>DE2_115_SOPC_timer</b>
<br/>altera_avalon_timer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_sdram</b>
<br/>altera_avalon_new_sdram_controller v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_key</b>
<br/>altera_avalon_pio v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_sma_in</b>
<br/>altera_avalon_pio v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_sma_out</b>
<br/>altera_avalon_pio v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_sw</b>
<br/>altera_avalon_pio v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_ledg</b>
<br/>altera_avalon_pio v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_ledr</b>
<br/>altera_avalon_pio v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_lcd</b>
<br/>altera_avalon_lcd_16207 v11.1</td>
<td></td>
</tr>
<tr>
<td><b>TERASIC_SRAM</b>
<br/>TERASIC_SRAM v1.0</td>
<td></td>
</tr>
<tr>
<td><b>SEG7_IF</b>
<br/>SEG7_IF v1.0</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_jtag_uart</b>
<br/>altera_avalon_jtag_uart v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_pll</b>
<br/>altpll v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_timer_stamp</b>
<br/>altera_avalon_timer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>VGA_NIOS_CTRL</b>
<br/>VGA_NIOS_CTRL v1.0</td>
<td></td>
</tr>
<tr>
<td><b>altera_avalon_mm_clock_crossing_bridge</b>
<br/>altera_avalon_mm_clock_crossing_bridge v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_cpu</b>
<br/>altera_nios2_qsys v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_sysid</b>
<br/>altera_avalon_sysid_qsys v11.1</td>
<td></td>
</tr>
<tr>
<td><b>CY7C67200_IF</b>
<br/>CY7C67200_IF v1.0</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_master_translator</b>
<br/>altera_merlin_master_translator v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_slave_translator</b>
<br/>altera_merlin_slave_translator v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_slave_agent</b>
<br/>altera_merlin_slave_agent v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_avalon_sc_fifo</b>
<br/>altera_avalon_sc_fifo v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_master_agent</b>
<br/>altera_merlin_master_agent v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_addr_router</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_addr_router_001</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_id_router</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_id_router_002</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_id_router_003</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_addr_router_002</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_id_router_010</b>
<br/>altera_merlin_router v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_traffic_limiter</b>
<br/>altera_merlin_traffic_limiter v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_burst_adapter</b>
<br/>altera_merlin_burst_adapter v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_reset_controller</b>
<br/>altera_reset_controller v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_cmd_xbar_demux</b>
<br/>altera_merlin_demultiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_cmd_xbar_demux_001</b>
<br/>altera_merlin_demultiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_cmd_xbar_mux</b>
<br/>altera_merlin_multiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_rsp_xbar_demux</b>
<br/>altera_merlin_demultiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_rsp_xbar_demux_003</b>
<br/>altera_merlin_demultiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_rsp_xbar_mux</b>
<br/>altera_merlin_multiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_rsp_xbar_mux_001</b>
<br/>altera_merlin_multiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_cmd_xbar_demux_002</b>
<br/>altera_merlin_demultiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_rsp_xbar_demux_010</b>
<br/>altera_merlin_demultiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_rsp_xbar_mux_002</b>
<br/>altera_merlin_multiplexer v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_merlin_width_adapter</b>
<br/>altera_merlin_width_adapter v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_avalon_st_handshake_clock_crosser</b>
<br/>altera_avalon_st_handshake_clock_crosser v11.1</td>
<td></td>
</tr>
<tr>
<td><b>DE2_115_SOPC_irq_mapper</b>
<br/>altera_irq_mapper v11.1</td>
<td></td>
</tr>
<tr>
<td><b>altera_irq_clock_crosser</b>
<br/>altera_irq_clock_crosser v11.1</td>
<td></td>
</tr>
</table>
</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Generation Messages</div>
<div style="white-space:pre ; font-family:courier">2012.11.30.14:56:32 [Info] DE2_115_SOPC.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2012.11.30.14:56:32 [Info] DE2_115_SOPC.sma_in: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2012.11.30.14:56:32 [Info] DE2_115_SOPC.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.sram: Timing: QME:1/7.953s
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.seg7: Timing: QME:1/8.500s
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.pll: Timing: VAL:1/0.031s ELA:1/0.000s
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.vpg: Timing: QME:1/8.188s
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.clock_crossing_io: Timing: ELA:1/0.000s
2012.11.30.14:51:29 [Debug] DE2_115_SOPC.altera_nios2_qsys: When a generate simulation callback is defined a synthesis generation callback should also be defined
2012.11.30.14:56:32 [Info] DE2_115_SOPC.cpu: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.cpu: Timing: VAL:1/0.047s ELA:1/0.015s
2012.11.30.14:56:32 [Info] DE2_115_SOPC.sysid: System ID will no longer be automatically assigned.
2012.11.30.14:56:32 [Info] DE2_115_SOPC.sysid: Time stamp will be automatically updated when this component is generated.
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.sysid: Timing: VAL:2/0.000s/0.000s
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.c0: Timing: ELA:1/0.000s
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.c2: Timing: ELA:1/0.000s
2012.11.30.14:51:37 [Warning] DE2_115_SOPC.CY7C67200_IF: TOP_LEVEL_MODULE automatically set to <b>CY7C67200_IF</b>
2012.11.30.14:56:32 [Debug] DE2_115_SOPC.CY7C67200_IF_0: Timing: QME:1/7.922s
2012.11.30.14:56:32 [Info] DE2_115_SOPC: Generating <b>DE2_115_SOPC</b> "<b>DE2_115_SOPC</b>" for QUARTUS_SYNTH
2012.11.30.14:56:32 [Debug] DE2_115_SOPC: queue size: 0 starting:DE2_115_SOPC "DE2_115_SOPC"
2012.11.30.14:56:32 [Debug] Transform: PipelineBridgeSwap
2012.11.30.14:56:32 [Info] pipeline_bridge_swap_transform: After transform: <b>22</b> modules, <b>90</b> connections
2012.11.30.14:56:32 [Debug] Transform: ClockCrossingBridgeSwap
2012.11.30.14:56:32 [Debug] Transform: QsysBetaIPSwap
2012.11.30.14:56:32 [Debug] Transform: CustomInstructionTransform
2012.11.30.14:56:32 [Info] No custom instruction connections, skipping transform
2012.11.30.14:56:32 [Debug] Transform: TristateConduitUpgradeTransform
2012.11.30.14:56:33 [Debug] Transform: TranslatorTransform
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Info] merlin_translator_transform: After transform: <b>44</b> modules, <b>178</b> connections
2012.11.30.14:56:33 [Debug] Transform: DomainTransform
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces sdram_s1_translator.avalon_anti_slave_0 and sdram.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces sram_avalon_slave_translator.avalon_anti_slave_0 and sram.avalon_slave
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces sma_in_s1_translator.avalon_anti_slave_0 and sma_in.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces sma_out_s1_translator.avalon_anti_slave_0 and sma_out.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces pll_pll_slave_translator.avalon_anti_slave_0 and pll.pll_slave
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces timer_stamp_s1_translator.avalon_anti_slave_0 and timer_stamp.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces timer_s1_translator.avalon_anti_slave_0 and timer.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_io_s0_translator.avalon_anti_slave_0 and clock_crossing_io.s0
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_io.m0 and clock_crossing_io_m0_translator.avalon_anti_master_0
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Progress] min: 0
2012.11.30.14:56:33 [Progress] max: 1
2012.11.30.14:56:33 [Progress] current: 1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces key_s1_translator.avalon_anti_slave_0 and key.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces sw_s1_translator.avalon_anti_slave_0 and sw.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces ledg_s1_translator.avalon_anti_slave_0 and ledg.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces ledr_s1_translator.avalon_anti_slave_0 and ledr.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces lcd_control_slave_translator.avalon_anti_slave_0 and lcd.control_slave
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces seg7_avalon_slave_translator.avalon_anti_slave_0 and seg7.avalon_slave
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces vpg_s1_translator.avalon_anti_slave_0 and vpg.s1
2012.11.30.14:56:33 [Debug] Transform merlin_domain_transform not run on matched interfaces CY7C67200_IF_0_hpi_translator.avalon_anti_slave_0 and CY7C67200_IF_0.hpi
2012.11.30.14:56:33 [Info] merlin_domain_transform: After transform: <b>90</b> modules, <b>480</b> connections
2012.11.30.14:56:33 [Debug] Transform: RouterTransform
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Info] merlin_router_transform: After transform: <b>112</b> modules, <b>568</b> connections
2012.11.30.14:56:34 [Debug] Transform: TrafficLimiterTransform
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Info] merlin_traffic_limiter_transform: After transform: <b>115</b> modules, <b>583</b> connections
2012.11.30.14:56:34 [Debug] Transform: BurstTransform
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Info] merlin_burst_transform: After transform: <b>116</b> modules, <b>587</b> connections
2012.11.30.14:56:34 [Debug] Transform: ResetAdaptation
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Info] reset_adaptation_transform: After transform: <b>119</b> modules, <b>462</b> connections
2012.11.30.14:56:34 [Debug] Transform: NetworkToSwitchTransform
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Info] merlin_network_to_switch_transform: After transform: <b>161</b> modules, <b>550</b> connections
2012.11.30.14:56:34 [Debug] Transform: WidthTransform
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1
2012.11.30.14:56:34 [Progress] current: 1
2012.11.30.14:56:34 [Progress] min: 0
2012.11.30.14:56:34 [Progress] max: 1