From 89521f4aad90acaf1e2aecc7e5914c94524d3fcc Mon Sep 17 00:00:00 2001 From: vana Date: Mon, 10 Feb 2020 14:55:38 +0100 Subject: [PATCH] rebased and resolved conflicts --- Justfile | 1 + README.md | 25 + src/periph/gpio/lib.rs | 12 +- svd/src/lib.rs | 199 + svd_files/STM32WBxx_CM4.svd | 36971 ++++++++++++++++++++++++++++++++++ 5 files changed, 37204 insertions(+), 4 deletions(-) create mode 100644 svd_files/STM32WBxx_CM4.svd diff --git a/Justfile b/Justfile index e8f536c..b1fe60d 100644 --- a/Justfile +++ b/Justfile @@ -51,6 +51,7 @@ check-all: DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32l4s7"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}" DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32l4r9"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}" DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32l4s9"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}" + DRONE_RUSTFLAGS='--cfg cortex_m_core="cortex_m4f_r0p1" --cfg stm32_mcu="stm32wbx5"' drone env thumbv7em-none-eabihf -- cargo check --package drone-stm32-map --features "{{features}}" # Generate the docs doc: diff --git a/README.md b/README.md index 4366b2c..5b26e1e 100644 --- a/README.md +++ b/README.md @@ -18,6 +18,7 @@ a drop-in replacement for it. ## Supported Devices +<<<<<<< HEAD | `stm32_mcu` | Core name | Reference manual | Available features | |-------------|-----------------------|--------------------------------------------------------------------------|----------------------------------------------------------| | `stm32f100` | ARM® Cortex®-M3 r1p1 | [RM0041](https://www.st.com/resource/en/reference_manual/cd00246267.pdf) | `dma` `gpio` `spi` `tim` | @@ -50,6 +51,30 @@ a drop-in replacement for it. `stm32_mcu` config flag should be set at the application level according to this table. +======= +| Device name / Cargo feature | Core name | Reference manual | +|-------------|-----------------------|--------------------------------------------------------------------------| +| `stm32f100` | ARM® Cortex®-M3 r1p1 | [RM0041](https://www.st.com/resource/en/reference_manual/cd00246267.pdf) | +| `stm32f101` | ARM® Cortex®-M3 r1p1 | [RM0008](https://www.st.com/resource/en/reference_manual/cd00171190.pdf) | +| `stm32f102` | ARM® Cortex®-M3 r1p1 | [RM0008](https://www.st.com/resource/en/reference_manual/cd00171190.pdf) | +| `stm32f103` | ARM® Cortex®-M3 r1p1 | [RM0008](https://www.st.com/resource/en/reference_manual/cd00171190.pdf) | +| `stm32f107` | ARM® Cortex®-M3 r1p1 | [RM0008](https://www.st.com/resource/en/reference_manual/cd00171190.pdf) | +| `stm32l4x1` | ARM® Cortex®-M4F r0p1 | [RM0394](https://www.st.com/resource/en/reference_manual/dm00151940.pdf) | +| `stm32l4x2` | ARM® Cortex®-M4F r0p1 | [RM0394](https://www.st.com/resource/en/reference_manual/dm00151940.pdf) | +| `stm32l4x3` | ARM® Cortex®-M4F r0p1 | [RM0394](https://www.st.com/resource/en/reference_manual/dm00151940.pdf) | +| `stm32l4x5` | ARM® Cortex®-M4F r0p1 | [RM0351](https://www.st.com/resource/en/reference_manual/dm00083560.pdf) | +| `stm32l4x6` | ARM® Cortex®-M4F r0p1 | [RM0351](https://www.st.com/resource/en/reference_manual/dm00083560.pdf) | +| `stm32l4r5` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | +| `stm32l4s5` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | +| `stm32l4r7` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | +| `stm32l4s7` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | +| `stm32l4r9` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | +| `stm32l4s9` | ARM® Cortex®-M4F r0p1 | [RM0432](https://www.st.com/resource/en/reference_manual/dm00310109.pdf) | +| `stm32wbx5` | ARM® Cortex®-M4F r0p1 | [RM0434](https://www.st.com/resource/en/reference_manual/dm00318631.pdf) | + +**NOTE** Exactly one cargo feature should be selected based on the device +model. +>>>>>>> Initial WB55 support. ## Documentation diff --git a/src/periph/gpio/lib.rs b/src/periph/gpio/lib.rs index 619ab10..ab414ea 100644 --- a/src/periph/gpio/lib.rs +++ b/src/periph/gpio/lib.rs @@ -51,7 +51,8 @@ periph! { stm32_mcu = "stm32l4r9", stm32_mcu = "stm32l4s5", stm32_mcu = "stm32l4s7", - stm32_mcu = "stm32l4s9" + stm32_mcu = "stm32l4s9", + stm32_mcu = "stm32wbx5" ))] BUSSMENR { 0x20 RwRegBitBand Shared; @@ -82,7 +83,8 @@ periph! { stm32_mcu = "stm32l4r9", stm32_mcu = "stm32l4s5", stm32_mcu = "stm32l4s7", - stm32_mcu = "stm32l4s9" + stm32_mcu = "stm32l4s9", + stm32_mcu = "stm32wbx5" ))] AFRL { 0x20 RwReg; @@ -117,7 +119,8 @@ periph! { stm32_mcu = "stm32l4r9", stm32_mcu = "stm32l4s5", stm32_mcu = "stm32l4s7", - stm32_mcu = "stm32l4s9" + stm32_mcu = "stm32l4s9", + stm32_mcu = "stm32wbx5" ))] AFRH { 0x20 RwReg; @@ -132,7 +135,8 @@ periph! { } #[cfg(any( stm32_mcu = "stm32l4x5", - stm32_mcu = "stm32l4x6" + stm32_mcu = "stm32l4x6", + stm32_mcu = "stm32wbx5" ))] ASCR { 0x20 RwReg Option; diff --git a/svd/src/lib.rs b/svd/src/lib.rs index 218c224..5632e26 100644 --- a/svd/src/lib.rs +++ b/svd/src/lib.rs @@ -74,10 +74,16 @@ fn svd_deserialize() -> Result { "stm32l4s5" => patch_stm32l4plus(parse_svd("STM32L4S5.svd")?), "stm32l4s7" => patch_stm32l4plus(parse_svd("STM32L4S7.svd")?), "stm32l4s9" => patch_stm32l4plus(parse_svd("STM32L4S9.svd")?), + "stm32wbx5" => patch_stm32wbx5(parse_svd("STM32WBxx_CM4.svd")?), _ => bail!("invalid `stm32_mcu` cfg flag"), } } +fn patch_stm32wbx5(mut dev: Device) -> Result { + fix_802154(&mut dev)?; + Ok(dev) +} + fn patch_stm32f102(mut dev: Device) -> Result { spi::fix_spi2_1(&mut dev)?; Ok(dev) @@ -197,6 +203,199 @@ fn patch_stm32f413(mut dev: Device) -> Result { tim::fix_tim11_1(&mut dev)?; adc::fix_adc1_1(&mut dev)?; Ok(dev) +fn fix_802154(dev: &mut Device) -> Result<(), Error> { + dev.field_mut("PWR", "SR1", "802WUF").name = "IEEE802WUF".to_string(); + dev.field_mut("PWR", "C2CR1", "802EWKUP").name = "IEEE802EWKUP".to_string(); + Ok(()) +} + +fn add_dmamux(dev: &mut Device) -> Result<(), Error> { + dev.add_peripheral(serde_xml_rs::deserialize( + read_svd("patch/add_dmamux.xml")?.as_bytes(), + )?); + Ok(()) +} + +fn add_tim3(dev: &mut Device) -> Result<(), Error> { + dev.new_peripheral(|peripheral| { + peripheral.derived_from = Some("TIM2".to_string()); + peripheral.name = "TIM3".to_string(); + peripheral.base_address = 0x4000_0400; + peripheral.interrupt = vec![Interrupt { + name: "TIM3".to_string(), + description: "TIM3 global interrupt".to_string(), + value: 29, + }]; + }); + Ok(()) +} + +fn fix_adc(dev: &mut Device) -> Result<(), Error> { + dev.field_mut("RCC", "AHB2SMENR", "ADCFSSMEN").name = "ADCSMEN".to_string(); + Ok(()) +} + +fn fix_exti(dev: &mut Device) -> Result<(), Error> { + for (reg_name, field_name) in &[("IMR2", "MR39"), ("EMR2", "MR39")] { + let mut field = dev.field("EXTI", reg_name, field_name).clone(); + field.name = field.name.replace("39", "40"); + field.description = field.description.replace("39", "40"); + field.bit_offset += 1; + dev.add_field("EXTI", reg_name, field); + } + Ok(()) +} + +fn fix_i2c(dev: &mut Device) -> Result<(), Error> { + dev.add_field("RCC", "APB1SMENR2", Field { + name: "I2C4SMEN".to_string(), + description: "I2C4 clocks enable during Sleep and Stop modes".to_string(), + bit_offset: 1, + bit_width: 1, + access: None, + }); + Ok(()) +} + +fn fix_lptim1(dev: &mut Device) -> Result<(), Error> { + dev.new_register("LPTIM1", |reg| { + reg.name = "OR".to_string(); + reg.description = format!("{} option register", "LPTIM1"); + reg.address_offset = 0x20; + reg.size = 0x20; + reg.access = Some(Access::ReadWrite); + reg.reset_value = 0x0000; + reg.add_field(Field { + name: "OR_0".to_string(), + description: "Option register bit 0".to_string(), + bit_offset: 0, + bit_width: 1, + access: None, + }); + reg.add_field(Field { + name: "OR_1".to_string(), + description: "Option register bit 1".to_string(), + bit_offset: 1, + bit_width: 1, + access: None, + }); + }); + Ok(()) +} + +fn fix_lptim2(dev: &mut Device) -> Result<(), Error> { + dev.new_register("LPTIM2", |reg| { + reg.name = "OR".to_string(); + reg.description = format!("{} option register", "LPTIM2"); + reg.address_offset = 0x20; + reg.size = 0x20; + reg.access = Some(Access::ReadWrite); + reg.reset_value = 0x0000; + reg.add_field(Field { + name: "OR_0".to_string(), + description: "Option register bit 0".to_string(), + bit_offset: 0, + bit_width: 1, + access: None, + }); + reg.add_field(Field { + name: "OR_1".to_string(), + description: "Option register bit 1".to_string(), + bit_offset: 1, + bit_width: 1, + access: None, + }); + }); + Ok(()) +} + +fn fix_lpuart1(dev: &mut Device) -> Result<(), Error> { + copy_field(dev, "USART3", "LPUART1", "CR3", "UCESM"); + Ok(()) +} + +fn fix_pwr(dev: &mut Device) -> Result<(), Error> { + dev.add_field("PWR", "CR1", Field { + name: "RRSTP".to_string(), + description: "SRAM3 retention in Stop 2 mode".to_string(), + bit_offset: 4, + bit_width: 1, + access: None, + }); + Ok(()) +} + +fn fix_rcc(dev: &mut Device) -> Result<(), Error> { + dev.new_register("RCC", |reg| { + reg.name = "CCIPR2".to_string(); + reg.description = "Peripherals independent clock configuration register".to_string(); + reg.address_offset = 0x9C; + reg.size = 0x20; + reg.access = Some(Access::ReadWrite); + reg.reset_value = 0x0000; + reg.add_field(Field { + name: "I2C4SEL".to_string(), + description: "I2C4 clock source selection".to_string(), + bit_offset: 0, + bit_width: 2, + access: None, + }); + }); + Ok(()) +} + +fn fix_rtc(dev: &mut Device) -> Result<(), Error> { + dev.add_field("RCC", "APB1ENR1", Field { + name: "RTCAPBEN".to_string(), + description: "RTC APB clock enable".to_string(), + bit_offset: 10, + bit_width: 1, + access: None, + }); + dev.add_field("RCC", "APB1SMENR1", Field { + name: "RTCAPBSMEN".to_string(), + description: "RTC APB clock enable during Sleep and Stop modes".to_string(), + bit_offset: 10, + bit_width: 1, + access: None, + }); + Ok(()) +} + +fn fix_spi2_1(dev: &mut Device) -> Result<(), Error> { + dev.add_field("RCC", "APB1ENR", Field { + name: "SPI2EN".to_string(), + description: "SPI 2 clock enable".to_string(), + bit_offset: 14, + bit_width: 1, + access: None, + }); + dev.add_field("RCC", "APB1RSTR", Field { + name: "SPI2RST".to_string(), + description: "SPI2 reset".to_string(), + bit_offset: 14, + bit_width: 1, + access: None, + }); + copy_field(dev, "SPI1", "SPI2", "SR", "UDR"); + copy_field(dev, "SPI1", "SPI2", "SR", "CHSIDE"); + Ok(()) +} + +fn fix_spi2_2(dev: &mut Device) -> Result<(), Error> { + dev.add_field("RCC", "APB1ENR1", Field { + name: "SPI2EN".to_string(), + description: "SPI2 clock enable".to_string(), + bit_offset: 14, + bit_width: 1, + access: None, + }); + Ok(()) +} + +fn fix_spi3_1(dev: &mut Device) -> Result<(), Error> { + dev.field_mut("RCC", "APB1SMENR1", "SP3SMEN").name = "SPI3SMEN".to_string(); + Ok(()) } fn patch_stm32f427(mut dev: Device) -> Result { diff --git a/svd_files/STM32WBxx_CM4.svd b/svd_files/STM32WBxx_CM4.svd new file mode 100644 index 0000000..7106678 --- /dev/null +++ b/svd_files/STM32WBxx_CM4.svd @@ -0,0 +1,36971 @@ + + + STM32WBxx_CM4 + 1.6 + STM32WBxx_CM4 + + CM4 + r0p1 + little + true + true + 4 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel 7 interrupt + 17 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error flag (x = 1 ..7) + 27 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1 ..7) + 26 + 1 + + + TCIF7 + Channel x transfer complete flag (x = 1 ..7) + 25 + 1 + + + GIF7 + Channel x global interrupt flag (x = 1 ..7) + 24 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1 ..7) + 23 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1 ..7) + 22 + 1 + + + TCIF6 + Channel x transfer complete flag (x = 1 ..7) + 21 + 1 + + + GIF6 + Channel x global interrupt flag (x = 1 ..7) + 20 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1 ..7) + 19 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1 ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 ..7) + 4 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1 ..7) + 3 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1 ..7) + 2 + 1 + + + TCIF1 + Channel x transfer complete flag (x = 1 ..7) + 1 + 1 + + + GIF1 + Channel x global interrupt flag (x = 1 ..7) + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x transfer error clear (x = 1 ..7) + 27 + 1 + + + CHTIF7 + Channel x half transfer clear (x = 1 ..7) + 26 + 1 + + + CTCIF7 + Channel x transfer complete clear (x = 1 ..7) + 25 + 1 + + + CGIF7 + Channel x global interrupt clear (x = 1 ..7) + 24 + 1 + + + CTEIF6 + Channel x transfer error clear (x = 1 ..7) + 23 + 1 + + + CHTIF6 + Channel x half transfer clear (x = 1 ..7) + 22 + 1 + + + CTCIF6 + Channel x transfer complete clear (x = 1 ..7) + 21 + 1 + + + CGIF6 + Channel x global interrupt clear (x = 1 ..7) + 20 + 1 + + + CTEIF5 + Channel x transfer error clear (x = 1 ..7) + 19 + 1 + + + CHTIF5 + Channel x half transfer clear (x = 1 ..7) + 18 + 1 + + + CTCIF5 + Channel x transfer complete clear (x = 1 ..7) + 17 + 1 + + + CGIF5 + Channel x global interrupt clear (x = 1 ..7) + 16 + 1 + + + CTEIF4 + Channel x transfer error clear (x = 1 ..7) + 15 + 1 + + + CHTIF4 + Channel x half transfer clear (x = 1 ..7) + 14 + 1 + + + CTCIF4 + Channel x transfer complete clear (x = 1 ..7) + 13 + 1 + + + CGIF4 + Channel x global interrupt clear (x = 1 ..7) + 12 + 1 + + + CTEIF3 + Channel x transfer error clear (x = 1 ..7) + 11 + 1 + + + CHTIF3 + Channel x half transfer clear (x = 1 ..7) + 10 + 1 + + + CTCIF3 + Channel x transfer complete clear (x = 1 ..7) + 9 + 1 + + + CGIF3 + Channel x global interrupt clear (x = 1 ..7) + 8 + 1 + + + CTEIF2 + Channel x transfer error clear (x = 1 ..7) + 7 + 1 + + + CHTIF2 + Channel x half transfer clear (x = 1 ..7) + 6 + 1 + + + CTCIF2 + Channel x transfer complete clear (x = 1 ..7) + 5 + 1 + + + CGIF2 + Channel x global interrupt clear (x = 1 ..7) + 4 + 1 + + + CTEIF1 + Channel x transfer error clear (x = 1 ..7) + 3 + 1 + + + CHTIF1 + Channel x half transfer clear (x = 1 ..7) + 2 + 1 + + + CTCIF1 + Channel x transfer complete clear (x = 1 ..7) + 1 + 1 + + + CGIF1 + Channel x global interrupt clear (x = 1 ..7) + 0 + 1 + + + + + CCR1 + CCR1 + channel x configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + channel x configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + channel x number of data register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + channel x configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + channel x number of data register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + channel x configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR4 + CNDTR4 + channel x number of data register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + channel x configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR5 + CNDTR5 + channel x number of data register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + channel x configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR6 + CNDTR6 + channel x number of data register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + channel x configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR7 + CNDTR7 + channel x number of data register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + DMA2 + Direct memory access controller + DMA + 0x40020400 + + 0x0 + 0x400 + registers + + + DMA2_CH1 + DMA2 channel 1 interrupt + 55 + + + DMA2_CH2 + DMA2 channel 2 interrupt + 56 + + + DMA2_CH3 + DMA2 channel 3 interrupt + 57 + + + DMA2_CH4 + DMA2 channel 4 interrupt + 58 + + + DMA2_CH5 + DMA2 channel 5 interrupt + 59 + + + DMA2_CH6 + DMA2 channel 6 interrupt + 60 + + + DMA2_CH7 + DMA2 channel 7 interrupt + 61 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF7 + Channel x transfer error flag (x = 1 ..7) + 27 + 1 + + + HTIF7 + Channel x half transfer flag (x = 1 ..7) + 26 + 1 + + + TCIF7 + Channel x transfer complete flag (x = 1 ..7) + 25 + 1 + + + GIF7 + Channel x global interrupt flag (x = 1 ..7) + 24 + 1 + + + TEIF6 + Channel x transfer error flag (x = 1 ..7) + 23 + 1 + + + HTIF6 + Channel x half transfer flag (x = 1 ..7) + 22 + 1 + + + TCIF6 + Channel x transfer complete flag (x = 1 ..7) + 21 + 1 + + + GIF6 + Channel x global interrupt flag (x = 1 ..7) + 20 + 1 + + + TEIF5 + Channel x transfer error flag (x = 1 ..7) + 19 + 1 + + + HTIF5 + Channel x half transfer flag (x = 1 ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 ..7) + 4 + 1 + + + TEIF1 + Channel x transfer error flag (x = 1 ..7) + 3 + 1 + + + HTIF1 + Channel x half transfer flag (x = 1 ..7) + 2 + 1 + + + TCIF1 + Channel x transfer complete flag (x = 1 ..7) + 1 + 1 + + + GIF1 + Channel x global interrupt flag (x = 1 ..7) + 0 + 1 + + + + + IFCR + IFCR + interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF7 + Channel x transfer error clear (x = 1 ..7) + 27 + 1 + + + CHTIF7 + Channel x half transfer clear (x = 1 ..7) + 26 + 1 + + + CTCIF7 + Channel x transfer complete clear (x = 1 ..7) + 25 + 1 + + + CGIF7 + Channel x global interrupt clear (x = 1 ..7) + 24 + 1 + + + CTEIF6 + Channel x transfer error clear (x = 1 ..7) + 23 + 1 + + + CHTIF6 + Channel x half transfer clear (x = 1 ..7) + 22 + 1 + + + CTCIF6 + Channel x transfer complete clear (x = 1 ..7) + 21 + 1 + + + CGIF6 + Channel x global interrupt clear (x = 1 ..7) + 20 + 1 + + + CTEIF5 + Channel x transfer error clear (x = 1 ..7) + 19 + 1 + + + CHTIF5 + Channel x half transfer clear (x = 1 ..7) + 18 + 1 + + + CTCIF5 + Channel x transfer complete clear (x = 1 ..7) + 17 + 1 + + + CGIF5 + Channel x global interrupt clear (x = 1 ..7) + 16 + 1 + + + CTEIF4 + Channel x transfer error clear (x = 1 ..7) + 15 + 1 + + + CHTIF4 + Channel x half transfer clear (x = 1 ..7) + 14 + 1 + + + CTCIF4 + Channel x transfer complete clear (x = 1 ..7) + 13 + 1 + + + CGIF4 + Channel x global interrupt clear (x = 1 ..7) + 12 + 1 + + + CTEIF3 + Channel x transfer error clear (x = 1 ..7) + 11 + 1 + + + CHTIF3 + Channel x half transfer clear (x = 1 ..7) + 10 + 1 + + + CTCIF3 + Channel x transfer complete clear (x = 1 ..7) + 9 + 1 + + + CGIF3 + Channel x global interrupt clear (x = 1 ..7) + 8 + 1 + + + CTEIF2 + Channel x transfer error clear (x = 1 ..7) + 7 + 1 + + + CHTIF2 + Channel x half transfer clear (x = 1 ..7) + 6 + 1 + + + CTCIF2 + Channel x transfer complete clear (x = 1 ..7) + 5 + 1 + + + CGIF2 + Channel x global interrupt clear (x = 1 ..7) + 4 + 1 + + + CTEIF1 + Channel x transfer error clear (x = 1 ..7) + 3 + 1 + + + CHTIF1 + Channel x half transfer clear (x = 1 ..7) + 2 + 1 + + + CTCIF1 + Channel x transfer complete clear (x = 1 ..7) + 1 + 1 + + + CGIF1 + Channel x global interrupt clear (x = 1 ..7) + 0 + 1 + + + + + CCR1 + CCR1 + channel x configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + channel x configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + channel x number of data register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + channel x configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + channel x number of data register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + channel x configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR4 + CNDTR4 + channel x number of data register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + channel x configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR5 + CNDTR5 + channel x number of data register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + channel x configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR6 + CNDTR6 + channel x number of data register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + channel x configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt enable + 3 + 1 + + + HTIE + Half transfer interrupt enable + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR7 + CNDTR7 + channel x number of data register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CSELR + CSELR + channel selection register + 0xA8 + 0x20 + read-write + 0x00000000 + + + C7S + DMA channel 7 selection + 24 + 4 + + + C6S + DMA channel 6 selection + 20 + 4 + + + C5S + DMA channel 5 selection + 16 + 4 + + + C4S + DMA channel 4 selection + 12 + 4 + + + C3S + DMA channel 3 selection + 8 + 4 + + + C2S + DMA channel 2 selection + 4 + 4 + + + C1S + DMA channel 1 selection + 0 + 4 + + + + + + + DMAMUX1 + Direct memory access Multiplexer + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX_OVR + DMAMUX overrun interrupt + 62 + + + + C0CR + C0CR + DMA Multiplexer Channel 0 Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C1CR + C1CR + DMA Multiplexer Channel 1 Control register + 0x4 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C2CR + C2CR + DMA Multiplexer Channel 2 Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C3CR + C3CR + DMA Multiplexer Channel 3 Control register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C4CR + C4CR + DMA Multiplexer Channel 4 Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C5CR + C5CR + DMA Multiplexer Channel 5 Control register + 0x14 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C6CR + C6CR + DMA Multiplexer Channel 6 Control register + 0x18 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C7CR + C7CR + DMA Multiplexer Channel 7 Control register + 0x1C + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C8CR + C8CR + DMA Multiplexer Channel 8 Control register + 0x20 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C9CR + C9CR + DMA Multiplexer Channel 9 Control register + 0x24 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C10CR + C10CR + DMA Multiplexer Channel 10 Control register + 0x28 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C11CR + C11CR + DMA Multiplexer Channel 11 Control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C12CR + C12CR + DMA Multiplexer Channel 12 Control register + 0x30 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + C13CR + C13CR + DMA Multiplexer Channel 13 Control register + 0x34 + 0x20 + read-write + 0x00000000 + + + SYNC_ID + SYNC_ID + 24 + 5 + + + NBREQ + Nb request + 19 + 5 + + + SPOL + Sync polarity + 17 + 2 + + + SE + Synchronization enable + 16 + 1 + + + EGE + Event Generation Enable + 9 + 1 + + + SOIE + Synchronization Overrun Interrupt Enable + 8 + 1 + + + DMAREQ_ID + DMA Request ID + 0 + 8 + + + + + CSR + CSR + DMA Multiplexer Channel Status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF0 + Synchronization Overrun Flag 0 + 0 + 1 + + + SOF1 + Synchronization Overrun Flag 1 + 1 + 1 + + + SOF2 + Synchronization Overrun Flag 2 + 2 + 1 + + + SOF3 + Synchronization Overrun Flag 3 + 3 + 1 + + + SOF4 + Synchronization Overrun Flag 4 + 4 + 1 + + + SOF5 + Synchronization Overrun Flag 5 + 5 + 1 + + + SOF6 + Synchronization Overrun Flag 6 + 6 + 1 + + + SOF7 + Synchronization Overrun Flag 7 + 7 + 1 + + + SOF8 + Synchronization Overrun Flag 8 + 8 + 1 + + + SOF9 + Synchronization Overrun Flag 9 + 9 + 1 + + + SOF10 + Synchronization Overrun Flag 10 + 10 + 1 + + + SOF11 + Synchronization Overrun Flag 11 + 11 + 1 + + + SOF12 + Synchronization Overrun Flag 12 + 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G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 + 13 + 1 + + + G4_IO1 + G4_IO1 + 12 + 1 + + + G3_IO4 + G3_IO4 + 11 + 1 + + + G3_IO3 + G3_IO3 + 10 + 1 + + + G3_IO2 + G3_IO2 + 9 + 1 + + + G3_IO1 + G3_IO1 + 8 + 1 + + + G2_IO4 + G2_IO4 + 7 + 1 + + + G2_IO3 + G2_IO3 + 6 + 1 + + + G2_IO2 + G2_IO2 + 5 + 1 + + + G2_IO1 + G2_IO1 + 4 + 1 + + + G1_IO4 + G1_IO4 + 3 + 1 + + + G1_IO3 + G1_IO3 + 2 + 1 + + + G1_IO2 + G1_IO2 + 1 + 1 + + + G1_IO1 + G1_IO1 + 0 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G7_IO4 + G7_IO4 + 27 + 1 + + + G7_IO3 + G7_IO3 + 26 + 1 + + + G7_IO2 + G7_IO2 + 25 + 1 + + + G7_IO1 + G7_IO1 + 24 + 1 + + + G6_IO4 + G6_IO4 + 23 + 1 + + + G6_IO3 + G6_IO3 + 22 + 1 + + + G6_IO2 + G6_IO2 + 21 + 1 + + + G6_IO1 + G6_IO1 + 20 + 1 + + + G5_IO4 + G5_IO4 + 19 + 1 + + + G5_IO3 + G5_IO3 + 18 + 1 + + + G5_IO2 + G5_IO2 + 17 + 1 + + + G5_IO1 + G5_IO1 + 16 + 1 + + + G4_IO4 + G4_IO4 + 15 + 1 + + + G4_IO3 + G4_IO3 + 14 + 1 + + + G4_IO2 + G4_IO2 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+ 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WDGTB + Timer base + 11 + 3 + + + EWI + Early wakeup interrupt + 9 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + + + + + + + COMP + Comparator instance 1 + COMP + 0x40010200 + + 0x0 + 0x9 + registers + + + COMP + COMP2 & COMP1 interrupt through + AIEC[21:20] + 22 + + + + COMP1_CSR + COMP1_CSR + Comparator control and status register + 0x0 + 0x20 + 0x00000000 + + + COMP1_EN + Comparator enable + 0 + 1 + read-write + + + COMP1_PWRMODE + Comparator power mode + 2 + 2 + read-write + + + COMP1_INMSEL + Comparator input minus selection + 4 + 3 + read-write + + + COMP1_INPSEL + Comparator input plus selection + 7 + 2 + read-write + + + COMP1_POLARITY + Comparator output polarity + 15 + 1 + read-write + + + COMP1_HYST + Comparator hysteresis + 16 + 2 + read-write + + + COMP1_BLANKING + Comparator blanking source + 18 + 3 + read-write + + + COMP1_BRGEN + Comparator voltage scaler enable + 22 + 1 + read-write + + + COMP1_SCALEN + Comparator scaler bridge enable + 23 + 1 + read-write + + + COMP1_INMESEL + Comparator input minus extended selection + 25 + 2 + read-write + + + COMP1_VALUE + Comparator output level + 30 + 1 + read-only + + + COMP1_LOCK + Comparator lock + 31 + 1 + read-write + + + + + COMP2_CSR + COMP2_CSR + Comparator 2 control and status register + 0x4 + 0x20 + 0x00000000 + + + COMP2_EN + Comparator 2 enable bit + 0 + 1 + read-write + + + COMP2_PWRMODE + Power Mode of the comparator 2 + 2 + 2 + read-write + + + COMP2_INMSEL + Comparator 2 input minus selection bits + 4 + 2 + read-write + + + COMP2_INPSEL + Comparator 1 input plus selection bit + 7 + 2 + read-write + + + COMP2_WINMODE + Windows mode selection bit + 9 + 1 + read-write + + + COMP2_POLARITY + Comparator 2 polarity selection bit + 15 + 1 + read-write + + + COMP2_HYST + Comparator 2 hysteresis selection bits + 16 + 2 + read-write + + + COMP2_BLANKING + Comparator 2 blanking source selection bits + 18 + 3 + read-write + + + COMP2_BRGEN + Scaler bridge enable + 22 + 1 + read-write + + + COMP2_SCALEN + Voltage scaler enable bit + 23 + 1 + read-write + + + COMP2_INMESEL + comparator 2 input minus extended selection bits. + 25 + 2 + read-write + + + COMP2_VALUE + Comparator 2 output status bit + 30 + 1 + read-only + + + COMP2_LOCK + CSR register lock bit + 31 + 1 + read-write + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 30 + + + I2C1_ER + I2C1 error interrupt + 31 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave mode) + 15 + 1 + + + STOP + Stop generation (master mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + + SADD + Slave address bit (master mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + SCLH + SCL high period (master mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 32 + + + I2C3_ER + I2C3 error interrupt + 33 + + + + Flash + Flash + Flash + 0x58004000 + + 0x0 + 0x90 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 3 + + + PRFTEN + Prefetch enable + 8 + 1 + + + ICEN + Instruction cache enable + 9 + 1 + + + DCEN + Data cache enable + 10 + 1 + + + ICRST + Instruction cache reset + 11 + 1 + + + DCRST + Data cache reset + 12 + 1 + + + PES + CPU1 CortexM4 program erase suspend request + 15 + 1 + + + EMPTY + Flash User area empty + 16 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEYR + KEYR + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + PROGERR + Programming error + 3 + 1 + read-write + + + WRPERR + Write protected error + 4 + 1 + read-write + + + PGAERR + Programming alignment error + 5 + 1 + read-write + + + SIZERR + Size error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + MISERR + Fast programming data miss error + 8 + 1 + read-write + + + FASTERR + Fast programming error + 9 + 1 + read-write + + + OPTNV + User Option OPTVAL indication + 13 + 1 + read-only + + + RDERR + PCROP read error + 14 + 1 + read-write + + + OPTVERR + Option validity error + 15 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + CFGBSY + Programming or erase configuration busy + 18 + 1 + read-only + + + PESD + Programming or erase operation suspended + 19 + 1 + read-only + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + PG + Programming + 0 + 1 + + + PER + Page erase + 1 + 1 + + + MER + This bit triggers the mass erase (all user pages) when set + 2 + 1 + + + PNB + Page number selection + 3 + 8 + + + STRT + Start + 16 + 1 + + + OPTSTRT + Options modification start + 17 + 1 + + + FSTPG + Fast programming + 18 + 1 + + + EOPIE + End of operation interrupt enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + RDERRIE + PCROP read error interrupt enable + 26 + 1 + + + OBL_LAUNCH + Force the option byte loading + 27 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + + + ECCR + ECCR + Flash ECC register + 0x18 + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 17 + read-only + + + SYSF_ECC + System Flash ECC fail + 20 + 1 + read-only + + + ECCCIE + ECC correction interrupt enable + 24 + 1 + read-write + + + CPUID + CPU identification + 26 + 3 + read-only + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x10708000 + + + RDP + Read protection level + 0 + 8 + + + ESE + Security enabled + 8 + 1 + + + BOR_LEV + BOR reset Level + 9 + 3 + + + nRST_STOP + nRST_STOP + 12 + 1 + + + nRST_STDBY + nRST_STDBY + 13 + 1 + + + nRST_SHDW + nRST_SHDW + 14 + 1 + + + IDWG_SW + Independent watchdog selection + 16 + 1 + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + + + WWDG_SW + Window watchdog selection + 19 + 1 + + + nBOOT1 + Boot configuration + 23 + 1 + + + SRAM2_PE + SRAM2 parity check enable + 24 + 1 + + + SRAM2_RST + SRAM2 Erase when system reset + 25 + 1 + + + nSWBOOT0 + Software Boot0 + 26 + 1 + + + nBOOT0 + nBoot0 option bit + 27 + 1 + + + AGC_TRIM + Radio Automatic Gain Control Trimming + 29 + 3 + + + + + PCROP1ASR + PCROP1ASR + Flash Bank 1 PCROP Start address zone A register + 0x24 + 0x20 + read-write + 0xFFFFFE00 + + + PCROP1A_STRT + Bank 1 PCROPQ area start offset + 0 + 9 + + + + + PCROP1AER + PCROP1AER + Flash Bank 1 PCROP End address zone A register + 0x28 + 0x20 + read-write + 0x7FFFFE00 + + + PCROP1A_END + Bank 1 PCROP area end offset + 0 + 9 + + + PCROP_RDP + PCROP area preserved when RDP level decreased + 31 + 1 + + + + + WRP1AR + WRP1AR + Flash Bank 1 WRP area A address register + 0x2C + 0x20 + read-write + 0xFF00FF00 + + + WRP1A_STRT + Bank 1 WRP first area A start offset + 0 + 8 + + + WRP1A_END + Bank 1 WRP first area A end offset + 16 + 8 + + + + + WRP1BR + WRP1BR + Flash Bank 1 WRP area B address register + 0x30 + 0x20 + read-write + 0xFF00FF00 + + + WRP1B_STRT + Bank 1 WRP second area B end offset + 16 + 8 + + + WRP1B_END + Bank 1 WRP second area B start offset + 0 + 8 + + + + + PCROP1BSR + PCROP1BSR + Flash Bank 1 PCROP Start address area B register + 0x34 + 0x20 + read-write + 0xFFFFFE00 + + + PCROP1B_STRT + Bank 1 PCROP area B start offset + 0 + 9 + + + + + PCROP1BER + PCROP1BER + Flash Bank 1 PCROP End address area B register + 0x38 + 0x20 + read-write + 0xFFFFFE00 + + + PCROP1B_END + Bank 1 PCROP area end area B offset + 0 + 9 + + + + + IPCCBR + IPCCBR + IPCC mailbox data buffer address register + 0x3C + 0x20 + read-write + 0xFFFFC000 + + + IPCCDBA + PCC mailbox data buffer base address + 0 + 14 + + + + + C2ACR + C2ACR + CPU2 cortex M0 access control register + 0x5C + 0x20 + read-write + 0x00000600 + + + PRFTEN + CPU2 cortex M0 prefetch enable + 8 + 1 + + + ICEN + CPU2 cortex M0 instruction cache enable + 9 + 1 + + + ICRST + CPU2 cortex M0 instruction cache reset + 11 + 1 + + + PES + CPU2 cortex M0 program erase suspend request + 15 + 1 + + + + + C2SR + C2SR + CPU2 cortex M0 status register + 0x60 + 0x20 + read-write + 0x00000000 + + + EOP + End of operation + 0 + 1 + + + OPERR + Operation error + 1 + 1 + + + PROGERR + Programming error + 3 + 1 + + + WRPERR + write protection error + 4 + 1 + + + PGAERR + Programming alignment error + 5 + 1 + + + SIZERR + Size error + 6 + 1 + + + PGSERR + Programming sequence error + 7 + 1 + + + MISSERR + Fast programming data miss error + 8 + 1 + + + FASTERR + Fast programming error + 9 + 1 + + + RDERR + PCROP read error + 14 + 1 + + + BSY + Busy + 16 + 1 + + + CFGBSY + Programming or erase configuration busy + 18 + 1 + + + PESD + Programming or erase operation suspended + 19 + 1 + + + + + C2CR + C2CR + CPU2 cortex M0 control register + 0x64 + 0x20 + read-write + 0x00000000 + + + PG + Programming + 0 + 1 + + + PER + Page erase + 1 + 1 + + + MER + Masse erase + 2 + 1 + + + PNB + Page Number selection + 3 + 8 + + + STRT + Start + 16 + 1 + + + FSTPG + Fast programming + 18 + 1 + + + EOPIE + End of operation interrupt enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + RDERRIE + PCROP read error interrupt enable + 26 + 1 + + + + + SFR + SFR + Secure flash start address register + 0x80 + 0x20 + read-write + 0xFFFFEE00 + + + SFSA + Secure flash start address + 0 + 8 + + + DDS + Disable Cortex M0 debug access + 12 + 1 + + + FSD + Flash security disable + 8 + 1 + + + + + SRRVR + SRRVR + Secure SRAM2 start address and cortex M0 reset vector register + 0x84 + 0x20 + read-write + 0x01000000 + + + SBRV + cortex M0 access control register + 0 + 18 + + + SBRSA + Secure backup SRAM2a start address + 18 + 5 + + + BRSD + backup SRAM2a security disable + 23 + 1 + + + SNBRSA + Secure non backup SRAM2a start address + 25 + 5 + + + C2OPT + CPU2 cortex M0 boot reset vector memory selection + 31 + 1 + + + NBRSD + non-backup SRAM2b security disable + 30 + 1 + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QUADSPI + QSPI global interrupt + 50 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt enable + 19 + 1 + + + FTIE + FIFO threshold interrupt enable + 18 + 1 + + + TCIE + Transfer complete interrupt enable + 17 + 1 + + + TEIE + Transfer error interrupt enable + 16 + 1 + + + FTHRES + FIFO threshold level + 8 + 4 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 5 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + SIOO + Send instruction only once mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 + + + DMODE + Data mode + 24 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ADMODE + Address mode + 10 + 2 + + + IMODE + Instruction mode + 8 + 2 + + + INSTRUCTION + Instruction + 0 + 8 + + + + + AR + AR + address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Address + 0 + 32 + + + + + ABR + ABR + ABR + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + DR + DR + data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval + 0 + 16 + + + + + LPTR + LPTR + low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + + + RCC + Reset and clock control + RCC + 0x58000000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000061 + + + PLLSAI1RDY + SAI1 PLL clock ready flag + 27 + 1 + read-only + + + PLLSAI1ON + SAI1 PLL enable + 26 + 1 + read-write + + + PLLRDY + Main PLL clock ready flag + 25 + 1 + read-only + + + PLLON + Main PLL enable + 24 + 1 + read-write + + + HSEPRE + HSE sysclk and PLL M divider prescaler + 20 + 1 + read-write + + + CSSON + HSE Clock security system enable + 19 + 1 + write-only + + + HSEBYP + HSE crystal oscillator bypass + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enabled + 16 + 1 + read-write + + + HSIKERDY + HSI kernel clock ready flag for peripherals requests + 12 + 1 + read-only + + + HSIASFS + HSI automatic start from Stop + 11 + 1 + read-write + + + HSIRDY + HSI clock ready flag + 10 + 1 + read-only + + + HSIKERON + HSI always enable for peripheral kernels + 9 + 1 + read-write + + + HSION + HSI clock enabled + 8 + 1 + read-write + + + MSIRANGE + MSI clock ranges + 4 + 4 + read-write + + + MSIPLLEN + MSI clock PLL enable + 2 + 1 + read-write + + + MSIRDY + MSI clock ready flag + 1 + 1 + read-only + + + MSION + MSI clock enable + 0 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration register + 0x4 + 0x20 + 0x40000000 + + + HSITRIM + HSI clock trimming + 24 + 7 + read-write + + + HSICAL + HSI clock calibration + 16 + 8 + read-only + + + MSITRIM + MSI clock trimming + 8 + 8 + read-write + + + MSICAL + MSI clock calibration + 0 + 8 + read-only + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00070000 + + + MCOPRE + Microcontroller clock output prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock output + 24 + 4 + read-write + + + PPRE2F + APB2 prescaler flag + 18 + 1 + read-only + + + PPRE1F + APB1 prescaler flag + 17 + 1 + read-only + + + HPREF + AHB prescaler flag + 16 + 1 + read-only + + + STOPWUCK + Wakeup from Stop and CSS backup clock selection + 15 + 1 + read-write + + + PPRE2 + APB high-speed prescaler (APB2) + 11 + 3 + read-write + + + PPRE1 + PB low-speed prescaler (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + PLLCFGR + PLLCFGR + PLLSYS configuration register + 0xC + 0x20 + read-write + 0x22040100 + + + PLLR + Main PLLSYS division factor R for SYSCLK (system clock) + 29 + 3 + + + PLLREN + Main PLLSYSR PLLCLK output enable + 28 + 1 + + + PLLQ + Main PLLSYS division factor Q for PLLSYSUSBCLK + 25 + 3 + + + PLLQEN + Main PLLSYSQ output enable + 24 + 1 + + + PLLP + Main PLL division factor P for PPLSYSSAICLK + 17 + 5 + + + PLLPEN + Main PLLSYSP output enable + 16 + 1 + + + PLLN + Main PLLSYS multiplication factor N + 8 + 7 + + + PLLM + Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + 4 + 3 + + + PLLSRC + Main PLL, PLLSAI1 and PLLSAI2 entry clock source + 0 + 2 + + + + + PLLSAI1CFGR + PLLSAI1CFGR + PLLSAI1 configuration register + 0x10 + 0x20 + read-write + 0x22040100 + + + PLLR + PLLSAI division factor R for PLLADC1CLK (ADC clock) + 29 + 3 + + + PLLREN + PLLSAI PLLADC1CLK output enable + 28 + 1 + + + PLLQ + SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock) + 25 + 3 + + + PLLQEN + SAIPLL PLLSAIUSBCLK output enable + 24 + 1 + + + PLLP + SAI1PLL division factor P for PLLSAICLK (SAI1clock) + 17 + 5 + + + PLLPEN + SAIPLL PLLSAI1CLK output enable + 16 + 1 + + + PLLN + SAIPLL multiplication factor for VCO + 8 + 7 + + + + + CIER + CIER + Clock interrupt enable register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSI2RDYIE + LSI2 ready interrupt enable + 11 + 1 + + + HSI48RDYIE + HSI48 ready interrupt enable + 10 + 1 + + + LSECSSIE + LSE clock security system interrupt enable + 9 + 1 + + + PLLSAI1RDYIE + PLLSAI1 ready interrupt enable + 6 + 1 + + + PLLRDYIE + PLLSYS ready interrupt enable + 5 + 1 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + MSIRDYIE + MSI ready interrupt enable + 2 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + LSI1RDYIE + LSI1 ready interrupt enable + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSI2RDYF + LSI2 ready interrupt flag + 11 + 1 + + + HSI48RDYF + HSI48 ready interrupt flag + 10 + 1 + + + LSECSSF + LSE Clock security system interrupt flag + 9 + 1 + + + HSECSSF + HSE Clock security system interrupt flag + 8 + 1 + + + PLLSAI1RDYF + PLLSAI1 ready interrupt flag + 6 + 1 + + + PLLRDYF + PLL ready interrupt flag + 5 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + MSIRDYF + MSI ready interrupt flag + 2 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSI1RDYF + LSI1 ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSI2RDYC + LSI2 ready interrupt clear + 11 + 1 + + + HSI48RDYC + HSI48 ready interrupt clear + 10 + 1 + + + LSECSSC + LSE Clock security system interrupt clear + 9 + 1 + + + HSECSSC + HSE Clock security system interrupt clear + 8 + 1 + + + PLLSAI1RDYC + PLLSAI1 ready interrupt clear + 6 + 1 + + + PLLRDYC + PLL ready interrupt clear + 5 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + MSIRDYC + MSI ready interrupt clear + 2 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + LSI1RDYC + LSI1 ready interrupt clear + 0 + 1 + + + + + SMPSCR + SMPSCR + Step Down converter control register + 0x24 + 0x20 + 0x00000301 + + + SMPSSWS + Step Down converter clock switch status + 8 + 2 + read-only + + + SMPSDIV + Step Down converter clock prescaler + 4 + 2 + read-write + + + SMPSSEL + Step Down converter clock selection + 0 + 2 + read-write + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + TSCRST + Touch Sensing Controller reset + 16 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMAMUXRST + DMAMUX reset + 2 + 1 + + + DMA2RST + DMA2 reset + 1 + 1 + + + DMA1RST + DMA1 reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + read-write + 0x00000000 + + + AES1RST + AES1 hardware accelerator reset + 16 + 1 + + + ADCRST + ADC reset + 13 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + read-write + 0x00000000 + + + FLASHRST + Flash interface reset + 25 + 1 + + + IPCCRST + IPCC interface reset + 20 + 1 + + + HSEMRST + HSEM interface reset + 19 + 1 + + + RNGRST + RNG interface reset + 18 + 1 + + + AES2RST + AES2 interface reset + 17 + 1 + + + PKARST + PKA interface reset + 16 + 1 + + + QSPIRST + Quad SPI memory interface reset + 8 + 1 + + + + + APB1RSTR1 + APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low Power Timer 1 reset + 31 + 1 + + + USBFSRST + USB FS reset + 26 + 1 + + + CRSRST + CRS reset + 24 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + LCDRST + LCD interface reset + 9 + 1 + + + TIM2RST + TIM2 timer reset + 0 + 1 + + + + + APB1RSTR2 + APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIM2RST + Low-power timer 2 reset + 5 + 1 + + + LPUART1RST + Low-power UART 1 reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + read-write + 0x00000000 + + + SAI1RST + Serial audio interface 1 (SAI1) reset + 21 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + + + APB3RSTR + APB3RSTR + APB3 peripheral reset register + 0x44 + 0x20 + read-write + 0x00000000 + + + RFRST + Radio system BLE reset + 0 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock enable register + 0x48 + 0x20 + read-write + 0x00000100 + + + TSCEN + Touch Sensing Controller clock enable + 16 + 1 + + + CRCEN + CPU1 CRC clock enable + 12 + 1 + + + DMAMUXEN + DMAMUX clock enable + 2 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + read-write + 0x00000000 + + + AES1EN + AES1 accelerator clock enable + 16 + 1 + + + ADCEN + ADC clock enable + 13 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable register + 0x50 + 0x20 + read-write + 0x02080000 + + + FLASHEN + FLASHEN + 25 + 1 + + + IPCCEN + IPCCEN + 20 + 1 + + + HSEMEN + HSEMEN + 19 + 1 + + + RNGEN + RNGEN + 18 + 1 + + + AES2EN + AES2EN + 17 + 1 + + + PKAEN + PKAEN + 16 + 1 + + + QSPIEN + QSPIEN + 8 + 1 + + + + + APB1ENR1 + APB1ENR1 + APB1ENR1 + 0x58 + 0x20 + read-write + 0x00000400 + + + LPTIM1EN + CPU1 Low power timer 1 clock enable + 31 + 1 + + + USBEN + CPU1 USB clock enable + 26 + 1 + + + CRSEN + CPU1 CRS clock enable + 24 + 1 + + + I2C3EN + CPU1 I2C3 clock enable + 23 + 1 + + + I2C1EN + CPU1 I2C1 clock enable + 21 + 1 + + + SPI2EN + CPU1 SPI2 clock enable + 14 + 1 + + + WWDGEN + CPU1 Window watchdog clock enable + 11 + 1 + + + RTCAPBEN + CPU1 RTC APB clock enable + 10 + 1 + + + LCDEN + CPU1 LCD clock enable + 9 + 1 + + + TIM2EN + CPU1 TIM2 timer clock enable + 0 + 1 + + + + + APB1ENR2 + APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + CPU1 LPTIM2EN + 5 + 1 + + + LPUART1EN + CPU1 Low power UART 1 clock enable + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2ENR + 0x60 + 0x20 + read-write + 0x00000000 + + + SAI1EN + CPU1 SAI1 clock enable + 21 + 1 + + + TIM17EN + CPU1 TIM17 timer clock enable + 18 + 1 + + + TIM16EN + CPU1 TIM16 timer clock enable + 17 + 1 + + + USART1EN + CPU1 USART1clock enable + 14 + 1 + + + SPI1EN + CPU1 SPI1 clock enable + 12 + 1 + + + TIM1EN + CPU1 TIM1 timer clock enable + 11 + 1 + + + + + AHB1SMENR + AHB1SMENR + AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x68 + 0x20 + read-write + 0x00011207 + + + TSCSMEN + CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes + 16 + 1 + + + CRCSMEN + CPU1 CRCSMEN + 12 + 1 + + + SRAM1SMEN + CPU1 SRAM1 interface clocks enable during Sleep and Stop modes + 9 + 1 + + + DMAMUXSMEN + CPU1 DMAMUX clocks enable during Sleep and Stop modes + 2 + 1 + + + DMA2SMEN + CPU1 DMA2 clocks enable during Sleep and Stop modes + 1 + 1 + + + DMA1SMEN + CPU1 DMA1 clocks enable during Sleep and Stop modes + 0 + 1 + + + + + AHB2SMENR + AHB2SMENR + AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x6C + 0x20 + read-write + 0x0001209F + + + AES1SMEN + CPU1 AES1 accelerator clocks enable during Sleep and Stop modes + 16 + 1 + + + ADCFSSMEN + CPU1 ADC clocks enable during Sleep and Stop modes + 13 + 1 + + + GPIOHSMEN + CPU1 IO port H clocks enable during Sleep and Stop modes + 7 + 1 + + + GPIOESMEN + CPU1 IO port E clocks enable during Sleep and Stop modes + 4 + 1 + + + GPIODSMEN + CPU1 IO port D clocks enable during Sleep and Stop modes + 3 + 1 + + + GPIOCSMEN + CPU1 IO port C clocks enable during Sleep and Stop modes + 2 + 1 + + + GPIOBSMEN + CPU1 IO port B clocks enable during Sleep and Stop modes + 1 + 1 + + + GPIOASMEN + CPU1 IO port A clocks enable during Sleep and Stop modes + 0 + 1 + + + + + AHB3SMENR + AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 + 0x20 + read-write + 0x03070100 + + + FLASHSMEN + Flash interface clocks enable during CPU1 sleep mode + 25 + 1 + + + SRAM2SMEN + SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode + 24 + 1 + + + RNGSMEN + True RNG clocks enable during CPU1 sleep mode + 18 + 1 + + + AES2SMEN + AES2 accelerator clocks enable during CPU1 sleep mode + 17 + 1 + + + PKASMEN + PKA accelerator clocks enable during CPU1 sleep mode + 16 + 1 + + + QSPISMEN + QSPISMEN + 8 + 1 + + + + + APB1SMENR1 + APB1SMENR1 + APB1SMENR1 + 0x78 + 0x20 + read-write + 0x85A04E01 + + + LPTIM1SMEN + Low power timer 1 clocks enable during CPU1 Sleep mode + 31 + 1 + + + USBSMEN + USB FS clocks enable during CPU1 Sleep mode + 26 + 1 + + + CRSMEN + CRS clocks enable during CPU1 Sleep mode + 24 + 1 + + + I2C3SMEN + I2C3 clocks enable during CPU1 Sleep mode + 23 + 1 + + + I2C1SMEN + I2C1 clocks enable during CPU1 Sleep mode + 21 + 1 + + + SPI2SMEN + SPI2 clocks enable during CPU1 Sleep mode + 14 + 1 + + + WWDGSMEN + Window watchdog clocks enable during CPU1 Sleep mode + 11 + 1 + + + RTCAPBSMEN + RTC APB clocks enable during CPU1 Sleep mode + 10 + 1 + + + LCDSMEN + LCD clocks enable during CPU1 Sleep mode + 9 + 1 + + + TIM2SMEN + TIM2 timer clocks enable during CPU1 Sleep mode + 0 + 1 + + + + + APB1SMENR2 + APB1SMENR2 + APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x7C + 0x20 + read-write + 0x000000021 + + + LPTIM2SMEN + Low power timer 2 clocks enable during CPU1 Sleep mode + 5 + 1 + + + LPUART1SMEN + Low power UART 1 clocks enable during CPU1 Sleep mode + 0 + 1 + + + + + APB2SMENR + APB2SMENR + APB2SMENR + 0x80 + 0x20 + read-write + 0x00265800 + + + SAI1SMEN + SAI1 clocks enable during CPU1 Sleep mode + 21 + 1 + + + TIM17SMEN + TIM17 timer clocks enable during CPU1 Sleep mode + 18 + 1 + + + TIM16SMEN + TIM16 timer clocks enable during CPU1 Sleep mode + 17 + 1 + + + USART1SMEN + USART1clocks enable during CPU1 Sleep mode + 14 + 1 + + + SPI1SMEN + SPI1 clocks enable during CPU1 Sleep mode + 12 + 1 + + + TIM1SMEN + TIM1 timer clocks enable during CPU1 Sleep mode + 11 + 1 + + + + + CCIPR + CCIPR + CCIPR + 0x88 + 0x20 + read-write + 0x00000000 + + + RNGSEL + RNG clock source selection + 30 + 2 + + + ADCSEL + ADCs clock source selection + 28 + 2 + + + CLK48SEL + 48 MHz clock source selection + 26 + 2 + + + SAI1SEL + SAI1 clock source selection + 22 + 2 + + + LPTIM2SEL + Low power timer 2 clock source selection + 20 + 2 + + + LPTIM1SEL + Low power timer 1 clock source selection + 18 + 2 + + + I2C3SEL + I2C3 clock source selection + 16 + 2 + + + I2C1SEL + I2C1 clock source selection + 12 + 2 + + + LPUART1SEL + LPUART1 clock source selection + 10 + 2 + + + USART1SEL + USART1 clock source selection + 0 + 2 + + + + + BDCR + BDCR + BDCR + 0x90 + 0x20 + 0x00000000 + + + LSCOSEL + Low speed clock output selection + 25 + 2 + read-write + + + LSCOEN + Low speed clock output enable + 24 + 1 + read-write + + + BDRST + Backup domain software reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + LSECSSD_ + CSS on LSE failure detection + 6 + 1 + read-only + + + LSECSSON + LSECSSON + 5 + 1 + read-write + + + LSEDRV + SE oscillator drive capability + 3 + 2 + read-write + + + LSEBYP + LSE oscillator bypass + 2 + 1 + read-write + + + LSERDY + LSE oscillator ready + 1 + 1 + read-only + + + LSEON + LSE oscillator enable + 0 + 1 + read-write + + + + + CSR + CSR + CSR + 0x94 + 0x20 + 0x0C000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-only + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-only + + + IWDGRSTF + Independent window watchdog reset flag + 29 + 1 + read-only + + + SFTRSTF + Software reset flag + 28 + 1 + read-only + + + BORRSTF + BOR flag + 27 + 1 + read-only + + + PINRSTF + Pin reset flag + 26 + 1 + read-only + + + OBLRSTF + Option byte loader reset flag + 25 + 1 + read-only + + + RMVF + Remove reset flag + 23 + 1 + read-write + + + RFWKPSEL + RF system wakeup clock source selection + 14 + 2 + read-write + + + LSI2BW + LSI2 oscillator bias configuration + 8 + 4 + read-write + + + LSI2TRIMOK + LSI2 oscillator trim OK + 5 + 1 + read-only + + + LSI2TRIMEN + LSI2 oscillator trimming enable + 4 + 1 + read-write + + + LSI2RDY + LSI2 oscillator ready + 3 + 1 + read-only + + + LSI2ON + LSI2 oscillator enabled + 2 + 1 + read-write + + + LSI1RDY + LSI1 oscillator ready + 1 + 1 + read-only + + + LSI1ON + LSI1 oscillator enabled + 0 + 1 + read-write + + + RFRSTS + Radio system BLE and 802.15.4 reset status + 16 + 1 + read-only + + + + + CRRCR + CRRCR + Clock recovery RC register + 0x98 + 0x20 + 0x00000000 + + + HSI48CAL + HSI48 clock calibration + 7 + 9 + read-only + + + HSI48RDY + HSI48 clock ready + 1 + 1 + read-only + + + HSI48ON + HSI48 oscillator enabled + 0 + 1 + read-write + + + + + HSECR + HSECR + Clock HSE register + 0x9C + 0x20 + 0x00000030 + + + HSETUNE + HSE capacitor tuning + 8 + 6 + read-only + + + HSEGMC + HSE current control + 4 + 3 + read-write + + + HSES + HSE Sense amplifier threshold + 3 + 1 + read-write + + + UNLOCKED + Register lock system + 0 + 1 + read-write + + + + + EXTCFGR + EXTCFGR + Extended clock recovery register + 0x108 + 0x20 + 0x00030000 + + + RFCSS + RF clock source selected + 20 + 1 + read-only + + + C2HPREF + CPU2 AHB prescaler flag + 17 + 1 + read-only + + + SHDHPREF + Shared AHB prescaler flag + 16 + 1 + read-only + + + C2HPRE + CPU2 AHB prescaler + 4 + 4 + read-write + + + SHDHPRE + Shared AHB prescaler + 0 + 4 + read-write + + + + + C2AHB1ENR + C2AHB1ENR + CPU2 AHB1 peripheral clock enable register + 0x148 + 0x20 + read-write + 0x00000000 + + + TSCEN + CPU2 Touch Sensing Controller clock enable + 16 + 1 + + + CRCEN + CPU2 CRC clock enable + 12 + 1 + + + SRAM1EN + CPU2 SRAM1 clock enable + 9 + 1 + + + DMAMUXEN + CPU2 DMAMUX clock enable + 2 + 1 + + + DMA2EN + CPU2 DMA2 clock enable + 1 + 1 + + + DMA1EN + CPU2 DMA1 clock enable + 0 + 1 + + + + + C2AHB2ENR + C2AHB2ENR + CPU2 AHB2 peripheral clock enable register + 0x14C + 0x20 + read-write + 0x00000000 + + + AES1EN + CPU2 AES1 accelerator clock enable + 16 + 1 + + + ADCEN + CPU2 ADC clock enable + 13 + 1 + + + GPIOHEN + CPU2 IO port H clock enable + 7 + 1 + + + GPIOEEN + CPU2 IO port E clock enable + 4 + 1 + + + GPIODEN + CPU2 IO port D clock enable + 3 + 1 + + + GPIOCEN + CPU2 IO port C clock enable + 2 + 1 + + + GPIOBEN + CPU2 IO port B clock enable + 1 + 1 + + + GPIOAEN + CPU2 IO port A clock enable + 0 + 1 + + + + + C2AHB3ENR + C2AHB3ENR + CPU2 AHB3 peripheral clock enable register + 0x150 + 0x20 + read-write + 0x02080000 + + + FLASHEN + CPU2 FLASHEN + 25 + 1 + + + IPCCEN + CPU2 IPCCEN + 20 + 1 + + + HSEMEN + CPU2 HSEMEN + 19 + 1 + + + RNGEN + CPU2 RNGEN + 18 + 1 + + + AES2EN + CPU2 AES2EN + 17 + 1 + + + PKAEN + CPU2 PKAEN + 16 + 1 + + + + + C2APB1ENR1 + C2APB1ENR1 + CPU2 APB1ENR1 + 0x158 + 0x20 + read-write + 0x00000400 + + + LPTIM1EN + CPU2 Low power timer 1 clock enable + 31 + 1 + + + USBEN + CPU2 USB clock enable + 26 + 1 + + + CRSEN + CPU2 CRS clock enable + 24 + 1 + + + I2C3EN + CPU2 I2C3 clock enable + 23 + 1 + + + I2C1EN + CPU2 I2C1 clock enable + 21 + 1 + + + SPI2EN + CPU2 SPI2 clock enable + 14 + 1 + + + RTCAPBEN + CPU2 RTC APB clock enable + 10 + 1 + + + LCDEN + CPU2 LCD clock enable + 9 + 1 + + + TIM2EN + CPU2 TIM2 timer clock enable + 0 + 1 + + + + + C2APB1ENR2 + C2APB1ENR2 + CPU2 APB1 peripheral clock enable register 2 + 0x15C + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + CPU2 LPTIM2EN + 5 + 1 + + + LPUART1EN + CPU2 Low power UART 1 clock enable + 0 + 1 + + + + + C2APB2ENR + C2APB2ENR + CPU2 APB2ENR + 0x160 + 0x20 + read-write + 0x00000000 + + + SAI1EN + CPU2 SAI1 clock enable + 21 + 1 + + + TIM17EN + CPU2 TIM17 timer clock enable + 18 + 1 + + + TIM16EN + CPU2 TIM16 timer clock enable + 17 + 1 + + + USART1EN + CPU2 USART1clock enable + 14 + 1 + + + SPI1EN + CPU2 SPI1 clock enable + 12 + 1 + + + TIM1EN + CPU2 TIM1 timer clock enable + 11 + 1 + + + + + C2APB3ENR + C2APB3ENR + CPU2 APB3ENR + 0x164 + 0x20 + read-write + 0x00000000 + + + EN802 + CPU2 802.15.4 interface clock enable + 1 + 1 + + + BLEEN + CPU2 BLE interface clock enable + 0 + 1 + + + + + C2AHB1SMENR + C2AHB1SMENR + CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x168 + 0x20 + read-write + 0x00011207 + + + TSCSMEN + CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes + 16 + 1 + + + CRCSMEN + CPU2 CRCSMEN + 12 + 1 + + + SRAM1SMEN + SRAM1 interface clock enable during CPU1 CSleep mode + 9 + 1 + + + DMAMUXSMEN + CPU2 DMAMUX clocks enable during Sleep and Stop modes + 2 + 1 + + + DMA2SMEN + CPU2 DMA2 clocks enable during Sleep and Stop modes + 1 + 1 + + + DMA1SMEN + CPU2 DMA1 clocks enable during Sleep and Stop modes + 0 + 1 + + + + + C2AHB2SMENR + C2AHB2SMENR + CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x16C + 0x20 + read-write + 0x0001209F + + + AES1SMEN + CPU2 AES1 accelerator clocks enable during Sleep and Stop modes + 16 + 1 + + + ADCFSSMEN + CPU2 ADC clocks enable during Sleep and Stop modes + 13 + 1 + + + GPIOHSMEN + CPU2 IO port H clocks enable during Sleep and Stop modes + 7 + 1 + + + GPIOESMEN + CPU2 IO port E clocks enable during Sleep and Stop modes + 4 + 1 + + + GPIODSMEN + CPU2 IO port D clocks enable during Sleep and Stop modes + 3 + 1 + + + GPIOCSMEN + CPU2 IO port C clocks enable during Sleep and Stop modes + 2 + 1 + + + GPIOBSMEN + CPU2 IO port B clocks enable during Sleep and Stop modes + 1 + 1 + + + GPIOASMEN + CPU2 IO port A clocks enable during Sleep and Stop modes + 0 + 1 + + + + + C2AHB3SMENR + C2AHB3SMENR + CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x170 + 0x20 + read-write + 0x03070000 + + + FLASHSMEN + Flash interface clocks enable during CPU2 sleep modes + 25 + 1 + + + SRAM2SMEN + SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes + 24 + 1 + + + RNGSMEN + True RNG clocks enable during CPU2 sleep modes + 18 + 1 + + + AES2SMEN + AES2 accelerator clocks enable during CPU2 sleep modes + 17 + 1 + + + PKASMEN + PKA accelerator clocks enable during CPU2 sleep modes + 16 + 1 + + + + + C2APB1SMENR1 + C2APB1SMENR1 + CPU2 APB1SMENR1 + 0x178 + 0x20 + read-write + 0x85A04601 + + + LPTIM1SMEN + Low power timer 1 clocks enable during CPU2 Sleep mode + 31 + 1 + + + USBSMEN + USB FS clocks enable during CPU2 Sleep mode + 26 + 1 + + + CRSMEN + CRS clocks enable during CPU2 Sleep mode + 24 + 1 + + + I2C3SMEN + I2C3 clocks enable during CPU2 Sleep mode + 23 + 1 + + + I2C1SMEN + I2C1 clocks enable during CPU2 Sleep mode + 21 + 1 + + + SPI2SMEN + SPI2 clocks enable during CPU2 Sleep mode + 14 + 1 + + + RTCAPBSMEN + RTC APB clocks enable during CPU2 Sleep mode + 10 + 1 + + + LCDSMEN + LCD clocks enable during CPU2 Sleep mode + 9 + 1 + + + TIM2SMEN + TIM2 timer clocks enable during CPU2 Sleep mode + 0 + 1 + + + + + C2APB1SMENR2 + C2APB1SMENR2 + CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x17C + 0x20 + read-write + 0x000000021 + + + LPTIM2SMEN + Low power timer 2 clocks enable during CPU2 Sleep mode + 5 + 1 + + + LPUART1SMEN + Low power UART 1 clocks enable during CPU2 Sleep mode + 0 + 1 + + + + + C2APB2SMENR + C2APB2SMENR + CPU2 APB2SMENR + 0x180 + 0x20 + read-write + 0x00265800 + + + SAI1SMEN + SAI1 clocks enable during CPU2 Sleep mode + 21 + 1 + + + TIM17SMEN + TIM17 timer clocks enable during CPU2 Sleep mode + 18 + 1 + + + TIM16SMEN + TIM16 timer clocks enable during CPU2 Sleep mode + 17 + 1 + + + USART1SMEN + USART1clocks enable during CPU2 Sleep mode + 14 + 1 + + + SPI1SMEN + SPI1 clocks enable during CPU2 Sleep mode + 12 + 1 + + + TIM1SMEN + TIM1 timer clocks enable during CPU2 Sleep mode + 11 + 1 + + + + + C2APB3SMENR + C2APB3SMENR + CPU2 APB3SMENR + 0x184 + 0x20 + read-write + 0x0000003 + + + SMEN802 + 802.15.4 interface clocks enable during CPU2 Sleep modes + 1 + 1 + + + BLESMEN + BLE interface clocks enable during CPU2 Sleep mode + 0 + 1 + + + + + + + PWR + Power control + PWR + 0x58000400 + + 0x0 + 0x400 + registers + + + PWR_SOTF + PWR switching on the fly + interrupt + 43 + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00000200 + + + LPR + Low-power run + 14 + 1 + + + VOS + Voltage scaling range selection + 9 + 2 + + + DBP + Disable backup domain write protection + 8 + 1 + + + FPDS + Flash power down mode during LPsSleep for CPU1 + 5 + 1 + + + FPDR + Flash power down mode during LPRun for CPU1 + 4 + 1 + + + LPMS + Low-power mode selection for CPU1 + 0 + 3 + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + USV + VDDUSB USB supply valid + 10 + 1 + + + PVME3 + Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V + 6 + 1 + + + PVME1 + Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V + 4 + 1 + + + PLS + Power voltage detector level selection + 1 + 3 + + + PVDE + Power voltage detector enable + 0 + 1 + + + + + CR3 + CR3 + Power control register 3 + 0x8 + 0x20 + read-write + 0x00008000 + + + EIWUL + Enable internal wakeup line for CPU1 + 15 + 1 + + + EC2H + Enable CPU2 Hold interrupt for CPU1 + 14 + 1 + + + E802A + Enable end of activity interrupt for CPU1 + 13 + 1 + + + EBLEA + Enable BLE end of activity interrupt for CPU1 + 11 + 1 + + + ECRPE + Enable critical radio phase end of activity interrupt for CPU1 + 12 + 1 + + + APC + Apply pull-up and pull-down configuration + 10 + 1 + + + RRS + SRAM2a retention in Standby mode + 9 + 1 + + + EBORHSDFB + Enable BORH and Step Down counverter forced in Bypass interrups for CPU1 + 8 + 1 + + + EWUP5 + Enable Wakeup pin WKUP5 + 4 + 1 + + + EWUP4 + Enable Wakeup pin WKUP4 + 3 + 1 + + + EWUP3 + Enable Wakeup pin WKUP3 + 2 + 1 + + + EWUP2 + Enable Wakeup pin WKUP2 + 1 + 1 + + + EWUP1 + Enable Wakeup pin WKUP1 + 0 + 1 + + + + + CR4 + CR4 + Power control register 4 + 0xC + 0x20 + read-write + 0x00000000 + + + C2BOOT + BOOT CPU2 after reset or wakeup from Stop or Standby modes + 15 + 1 + + + VBRS + VBAT battery charging resistor selection + 9 + 1 + + + VBE + VBAT battery charging enable + 8 + 1 + + + WP5 + Wakeup pin WKUP5 polarity + 4 + 1 + + + WP4 + Wakeup pin WKUP4 polarity + 3 + 1 + + + WP3 + Wakeup pin WKUP3 polarity + 2 + 1 + + + WP2 + Wakeup pin WKUP2 polarity + 1 + 1 + + + WP1 + Wakeup pin WKUP1 polarity + 0 + 1 + + + + + SR1 + SR1 + Power status register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + WUFI + Internal Wakeup interrupt flag + 15 + 1 + + + C2HF + CPU2 Hold interrupt flag + 14 + 1 + + + AF802 + 802.15.4 end of activity interrupt flag + 13 + 1 + + + BLEAF + BLE end of activity interrupt flag + 12 + 1 + + + CRPEF + Enable critical radio phase end of activity interrupt flag + 11 + 1 + + + 802WUF + 802.15.4 wakeup interrupt flag + 10 + 1 + + + BLEWUF + BLE wakeup interrupt flag + 9 + 1 + + + BORHF + BORH interrupt flag + 8 + 1 + + + SDFBF + Step Down converter forced in Bypass interrupt flag + 7 + 1 + + + CWUF5 + Wakeup flag 5 + 4 + 1 + + + CWUF4 + Wakeup flag 4 + 3 + 1 + + + CWUF3 + Wakeup flag 3 + 2 + 1 + + + CWUF2 + Wakeup flag 2 + 1 + 1 + + + CWUF1 + Wakeup flag 1 + 0 + 1 + + + + + SR2 + SR2 + Power status register 2 + 0x14 + 0x20 + read-only + 0x00000002 + + + PVMO3 + Peripheral voltage monitoring output: VDDA vs. 1.62 V + 14 + 1 + + + PVMO1 + Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + 12 + 1 + + + PVDO + Power voltage detector output + 11 + 1 + + + VOSF + Voltage scaling flag + 10 + 1 + + + REGLPF + Low-power regulator flag + 9 + 1 + + + REGLPS + Low-power regulator started + 8 + 1 + + + SDSMPSF + Step Down converter SMPS mode flag + 1 + 1 + + + SDBF + Step Down converter Bypass mode flag + 0 + 1 + + + + + SCR + SCR + Power status clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + CC2HF + Clear CPU2 Hold interrupt flag + 14 + 1 + + + C802AF + Clear 802.15.4 end of activity interrupt flag + 13 + 1 + + + CBLEAF + Clear BLE end of activity interrupt flag + 12 + 1 + + + CCRPEF + Clear critical radio phase end of activity interrupt flag + 11 + 1 + + + C802WUF + Clear 802.15.4 wakeup interrupt flag + 10 + 1 + + + CBLEWUF + Clear BLE wakeup interrupt flag + 9 + 1 + + + CBORHF + Clear BORH interrupt flag + 8 + 1 + + + CSMPSFBF + Clear SMPS Step Down converter forced in Bypass interrupt flag + 7 + 1 + + + CWUF5 + Clear wakeup flag 5 + 4 + 1 + + + CWUF4 + Clear wakeup flag 4 + 3 + 1 + + + CWUF3 + Clear wakeup flag 3 + 2 + 1 + + + CWUF2 + Clear wakeup flag 2 + 1 + 1 + + + CWUF1 + Clear wakeup flag 1 + 0 + 1 + + + + + CR5 + CR5 + Power control register 5 + 0x1C + 0x20 + read-write + 0x00004270 + + + SDEB + Enable Step Down converter SMPS mode enabled + 15 + 1 + + + SDBEN + Enable Step Down converter Bypass mode enabled + 14 + 1 + + + SMPSCFG + VOS configuration selection (non user) + 9 + 1 + + + BORHC + BORH configuration selection + 8 + 1 + + + SDSC + Step Down converter supplt startup current selection + 4 + 3 + + + SDVOS + Step Down converter voltage output scaling + 0 + 4 + + + + + PUCRA + PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + read-write + 0x00000000 + + + PU15 + Port A pull-up bit y (y=0..15) + 15 + 1 + + + PU13 + Port A pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port A pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port A pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port A pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port A pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port A pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port A pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port A pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port A pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port A pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port A pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port A pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port A pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port A pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRA + PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + read-write + 0x00000000 + + + PD14 + Port A pull-down bit y (y=0..15) + 14 + 1 + + + PD12 + Port A pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port A pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port A pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port A pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port A pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port A pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port A pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port A pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port A pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port A pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port A pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port A pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port A pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRB + PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + read-write + 0x00000000 + + + PU15 + Port B pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port B pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port B pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port B pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port B pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port B pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port B pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port B pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port B pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port B pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port B pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port B pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port B pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port B pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port B pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port B pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRB + PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD15 + Port B pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port B pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port B pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port B pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port B pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port B pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port B pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port B pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port B pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port B pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port B pull-down bit y (y=0..15) + 5 + 1 + + + PD3 + Port B pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port B pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port B pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port B pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRC + PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + read-write + 0x00000000 + + + PU15 + Port C pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port C pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port C pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port C pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port C pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port C pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port C pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port C pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port C pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port C pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port C pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port C pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port C pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port C pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port C pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port C pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRC + PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + read-write + 0x00000000 + + + PD15 + Port C pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port C pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port C pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port C pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port C pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port C pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port C pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port C pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port C pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port C pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port C pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port C pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port C pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port C pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port C pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port C pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRD + PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + read-write + 0x00000000 + + + PU15 + Port D pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port D pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port D pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port D pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port D pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port D pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port D pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port D pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port D pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port D pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port D pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port D pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port D pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port D pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port D pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port D pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRD + PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + read-write + 0x00000000 + + + PD15 + Port D pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port D pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port D pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port D pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port D pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port D pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port D pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port D pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port D pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port D pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port D pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port D pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port D pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port D pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port D pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port D pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRE + PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + read-write + 0x00000000 + + + PU4 + Port E pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port E pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port E pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port E pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port E pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRE + PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PD4 + Port E pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port E pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port E pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port E pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port E pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRH + PUCRH + Power Port H pull-up control register + 0x58 + 0x20 + read-write + 0x00000000 + + + PU3 + Port H pull-up bit y (y=0..1) + 3 + 1 + + + PU1 + Port H pull-up bit y (y=0..1) + 1 + 1 + + + PU0 + Port H pull-up bit y (y=0..1) + 0 + 1 + + + + + PDCRH + PDCRH + Power Port H pull-down control register + 0x5C + 0x20 + read-write + 0x00000000 + + + PD3 + Port H pull-down bit y (y=0..1) + 3 + 1 + + + PD1 + Port H pull-down bit y (y=0..1) + 1 + 1 + + + PD0 + Port H pull-down bit y (y=0..1) + 0 + 1 + + + + + C2CR1 + C2CR1 + CPU2 Power control register 1 + 0x80 + 0x20 + read-write + 0x00000000 + + + 802EWKUP + 802.15.4 external wakeup signal + 15 + 1 + + + BLEEWKUP + BLE external wakeup signal + 14 + 1 + + + FPDS + Flash power down mode during LPSleep for CPU2 + 5 + 1 + + + FPDR + Flash power down mode during LPRun for CPU2 + 4 + 1 + + + LPMS + Low-power mode selection for CPU2 + 0 + 3 + + + + + C2CR3 + C2CR3 + CPU2 Power control register 3 + 0x84 + 0x20 + read-write + 0X00008000 + + + EIWUL + Enable internal wakeup line for CPU2 + 15 + 1 + + + APC + Apply pull-up and pull-down configuration for CPU2 + 12 + 1 + + + E802WUP + Enable 802.15.4 host wakeup interrupt for CPU2 + 10 + 1 + + + EBLEWUP + Enable BLE host wakeup interrupt for CPU2 + 9 + 1 + + + EWUP5 + Enable Wakeup pin WKUP5 for CPU2 + 4 + 1 + + + EWUP4 + Enable Wakeup pin WKUP4 for CPU2 + 3 + 1 + + + EWUP3 + Enable Wakeup pin WKUP3 for CPU2 + 2 + 1 + + + EWUP2 + Enable Wakeup pin WKUP2 for CPU2 + 1 + 1 + + + EWUP1 + Enable Wakeup pin WKUP1 for CPU2 + 0 + 1 + + + + + EXTSCR + EXTSCR + Power status clear register + 0x88 + 0x20 + 0x00000000 + + + C2DS + CPU2 deepsleep mode + 15 + 1 + read-only + + + C1DS + CPU1 deepsleep mode + 14 + 1 + read-only + + + CRPF + Critical Radio system phase + 13 + 1 + read-only + + + C2STOPF + System Stop flag for CPU2 + 11 + 1 + read-only + + + C2SBF + System Standby flag for CPU2 + 10 + 1 + read-only + + + C1STOPF + System Stop flag for CPU1 + 9 + 1 + read-only + + + C1SBF + System Standby flag for CPU1 + 8 + 1 + read-only + + + CCRPF + Clear Critical Radio system phase + 2 + 1 + write-only + + + C2CSSF + Clear CPU2 Stop Standby flags + 1 + 1 + write-only + + + C1CSSF + Clear CPU1 Stop Standby flags + 0 + 1 + write-only + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010100 + + 0x0 + 0x100 + registers + + + + MEMRMP + MEMRMP + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + 0 + 3 + + + + + CFGR1 + CFGR1 + configuration register 1 + 0x4 + 0x20 + read-write + 0x7C000001 + + + FPU_IE + Floating Point Unit interrupts enable bits + 26 + 6 + + + I2C3_FMP + I2C3 Fast-mode Plus driving capability activation + 22 + 1 + + + I2C1_FMP + I2C1 Fast-mode Plus driving capability activation + 20 + 1 + + + I2C_PB9_FMP + Fast-mode Plus (Fm+) driving capability activation on PB9 + 19 + 1 + + + I2C_PB8_FMP + Fast-mode Plus (Fm+) driving capability activation on PB8 + 18 + 1 + + + I2C_PB7_FMP + Fast-mode Plus (Fm+) driving capability activation on PB7 + 17 + 1 + + + I2C_PB6_FMP + Fast-mode Plus (Fm+) driving capability activation on PB6 + 16 + 1 + + + BOOSTEN + I/O analog switch voltage booster enable + 8 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI3 + EXTI 3 configuration bits + 12 + 3 + + + EXTI2 + EXTI 2 configuration bits + 8 + 3 + + + EXTI1 + EXTI 1 configuration bits + 4 + 3 + + + EXTI0 + EXTI 0 configuration bits + 0 + 3 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI7 + EXTI 7 configuration bits + 12 + 3 + + + EXTI6 + EXTI 6 configuration bits + 8 + 3 + + + EXTI5 + EXTI 5 configuration bits + 4 + 3 + + + EXTI4 + EXTI 4 configuration bits + 0 + 3 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI11 + EXTI 11 configuration bits + 12 + 3 + + + EXTI10 + EXTI 10 configuration bits + 8 + 3 + + + EXTI9 + EXTI 9 configuration bits + 4 + 3 + + + EXTI8 + EXTI 8 configuration bits + 0 + 3 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI15 + EXTI15 configuration bits + 12 + 3 + + + EXTI14 + EXTI14 configuration bits + 8 + 3 + + + EXTI13 + EXTI13 configuration bits + 4 + 3 + + + EXTI12 + EXTI12 configuration bits + 0 + 3 + + + + + SCSR + SCSR + SCSR + 0x18 + 0x20 + 0x00000000 + + + SRAM2BSY + SRAM2 busy by erase operation + 1 + 1 + read-only + + + SRAM2ER + SRAM2 Erase + 0 + 1 + read-write + + + C2RFD + CPU2 SRAM fetch (execution) disable. + 31 + 1 + read-write + + + + + CFGR2 + CFGR2 + CFGR2 + 0x1C + 0x20 + 0x00000000 + + + SPF + SRAM2 parity error flag + 8 + 1 + read-write + + + ECCL + ECC Lock + 3 + 1 + write-only + + + PVDL + PVD lock enable bit + 2 + 1 + write-only + + + SPL + SRAM2 parity lock bit + 1 + 1 + write-only + + + CLL + Cortex-M4 LOCKUP (Hardfault) output enable bit + 0 + 1 + write-only + + + + + SWPR + SWPR + SRAM2 write protection register + 0x20 + 0x20 + write-only + 0x00000000 + + + P31WP + SRAM2 page 31 write protection + 31 + 1 + + + P30WP + P30WP + 30 + 1 + + + P29WP + P29WP + 29 + 1 + + + P28WP + P28WP + 28 + 1 + + + P27WP + P27WP + 27 + 1 + + + P26WP + P26WP + 26 + 1 + + + P25WP + P25WP + 25 + 1 + + + P24WP + P24WP + 24 + 1 + + + P23WP + P23WP + 23 + 1 + + + P22WP + P22WP + 22 + 1 + + + P21WP + P21WP + 21 + 1 + + + P20WP + P20WP + 20 + 1 + + + P19WP + P19WP + 19 + 1 + + + P18WP + P18WP + 18 + 1 + + + P17WP + P17WP + 17 + 1 + + + P16WP + P16WP + 16 + 1 + + + P15WP + P15WP + 15 + 1 + + + P14WP + P14WP + 14 + 1 + + + P13WP + P13WP + 13 + 1 + + + P12WP + P12WP + 12 + 1 + + + P11WP + P11WP + 11 + 1 + + + P10WP + P10WP + 10 + 1 + + + P9WP + P9WP + 9 + 1 + + + P8WP + P8WP + 8 + 1 + + + P7WP + P7WP + 7 + 1 + + + P6WP + P6WP + 6 + 1 + + + P5WP + P5WP + 5 + 1 + + + P4WP + P4WP + 4 + 1 + + + P3WP + P3WP + 3 + 1 + + + P2WP + P2WP + 2 + 1 + + + P1WP + P1WP + 1 + 1 + + + P0WP + P0WP + 0 + 1 + + + + + SKR + SKR + SKR + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + SRAM2 write protection key for software erase + 0 + 8 + + + + + SWPR2 + SWPR2 + SRAM2 write protection register 2 + 0x28 + 0x20 + write-only + 0x00000000 + + + P63WP + SRAM2 page 63 write protection + 31 + 1 + + + P62WP + P62WP + 30 + 1 + + + P61WP + P61WP + 29 + 1 + + + P60WP + P60WP + 28 + 1 + + + P59WP + P59WP + 27 + 1 + + + P58WP + P58WP + 26 + 1 + + + P57WP + P57WP + 25 + 1 + + + P56WP + P56WP + 24 + 1 + + + P55WP + P55WP + 23 + 1 + + + P54WP + P54WP + 22 + 1 + + + P53WP + P53WP + 21 + 1 + + + P52WP + P52WP + 20 + 1 + + + P51WP + P51WP + 19 + 1 + + + P50WP + P50WP + 18 + 1 + + + P49WP + P49WP + 17 + 1 + + + P48WP + P48WP + 16 + 1 + + + P47WP + P47WP + 15 + 1 + + + P46WP + P46WP + 14 + 1 + + + P45WP + P45WP + 13 + 1 + + + P44WP + P44WP + 12 + 1 + + + P43WP + P43WP + 11 + 1 + + + P42WP + P42WP + 10 + 1 + + + P41WP + P41WP + 9 + 1 + + + P40WP + P40WP + 8 + 1 + + + P39WP + P39WP + 7 + 1 + + + P38WP + P38WP + 6 + 1 + + + P37WP + P37WP + 5 + 1 + + + P36WP + P36WP + 4 + 1 + + + P35WP + P35WP + 3 + 1 + + + P34WP + P34WP + 2 + 1 + + + P33WP + P33WP + 1 + 1 + + + P32WP + P32WP + 0 + 1 + + + + + IMR1 + IMR1 + CPU1 interrupt mask register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + TIM1IM + Peripheral TIM1 interrupt mask to CPU1 + 13 + 1 + + + TIM16IM + Peripheral TIM16 interrupt mask to CPU1 + 14 + 1 + + + TIM17IM + Peripheral TIM17 interrupt mask to CPU1 + 15 + 1 + + + EXIT5IM + Peripheral EXIT5 interrupt mask to CPU1 + 21 + 1 + + + EXIT6IM + Peripheral EXIT6 interrupt mask to CPU1 + 22 + 1 + + + EXIT7IM + Peripheral EXIT7 interrupt mask to CPU1 + 23 + 1 + + + EXIT8IM + Peripheral EXIT8 interrupt mask to CPU1 + 24 + 1 + + + EXIT9IM + Peripheral EXIT9 interrupt mask to CPU1 + 25 + 1 + + + EXIT10IM + Peripheral EXIT10 interrupt mask to CPU1 + 26 + 1 + + + EXIT11IM + Peripheral EXIT11 interrupt mask to CPU1 + 27 + 1 + + + EXIT12IM + Peripheral EXIT12 interrupt mask to CPU1 + 28 + 1 + + + EXIT13IM + Peripheral EXIT13 interrupt mask to CPU1 + 29 + 1 + + + EXIT14IM + Peripheral EXIT14 interrupt mask to CPU1 + 30 + 1 + + + EXIT15IM + Peripheral EXIT15 interrupt mask to CPU1 + 31 + 1 + + + + + IMR2 + IMR2 + CPU1 interrupt mask register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + PVM3IM + Peripheral PVM3 interrupt mask to CPU1 + 18 + 1 + + + PVM1IM + Peripheral PVM1 interrupt mask to CPU1 + 16 + 1 + + + PVDIM + Peripheral PVD interrupt mask to CPU1 + 20 + 1 + + + + + C2IMR1 + C2IMR1 + CPU2 interrupt mask register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + RTCSTAMP + Peripheral RTCSTAMP interrupt mask to CPU2 + 0 + 1 + + + RTCWKUP + Peripheral RTCWKUP interrupt mask to CPU2 + 3 + 1 + + + RTCALARM + Peripheral RTCALARM interrupt mask to CPU2 + 4 + 1 + + + RCC + Peripheral RCC interrupt mask to CPU2 + 5 + 1 + + + FLASH + Peripheral FLASH interrupt mask to CPU2 + 6 + 1 + + + PKA + Peripheral PKA interrupt mask to CPU2 + 8 + 1 + + + RNG + Peripheral RNG interrupt mask to CPU2 + 9 + 1 + + + AES1 + Peripheral AES1 interrupt mask to CPU2 + 10 + 1 + + + COMP + Peripheral COMP interrupt mask to CPU2 + 11 + 1 + + + ADC + Peripheral ADC interrupt mask to CPU2 + 12 + 1 + + + + + C2IMR2 + C2IMR2 + CPU2 interrupt mask register 1 + 0x38 + 0x20 + read-write + 0x00000000 + + + DMA1_CH1_IM + Peripheral DMA1 CH1 interrupt mask to CPU2 + 0 + 1 + + + DMA1_CH2_IM + Peripheral DMA1 CH2 interrupt mask to CPU2 + 1 + 1 + + + DMA1_CH3_IM + Peripheral DMA1 CH3 interrupt mask to CPU2 + 2 + 1 + + + DMA1_CH4_IM + Peripheral DMA1 CH4 interrupt mask to CPU2 + 3 + 1 + + + DMA1_CH5_IM + Peripheral DMA1 CH5 interrupt mask to CPU2 + 4 + 1 + + + DMA1_CH6_IM + Peripheral DMA1 CH6 interrupt mask to CPU2 + 5 + 1 + + + DMA1_CH7_IM + Peripheral DMA1 CH7 interrupt mask to CPU2 + 6 + 1 + + + DMA2_CH1_IM + Peripheral DMA2 CH1 interrupt mask to CPU1 + 8 + 1 + + + DMA2_CH2_IM + Peripheral DMA2 CH2 interrupt mask to CPU1 + 9 + 1 + + + DMA2_CH3_IM + Peripheral DMA2 CH3 interrupt mask to CPU1 + 10 + 1 + + + DMA2_CH4_IM + Peripheral DMA2 CH4 interrupt mask to CPU1 + 11 + 1 + + + DMA2_CH5_IM + Peripheral DMA2 CH5 interrupt mask to CPU1 + 12 + 1 + + + DMA2_CH6_IM + Peripheral DMA2 CH6 interrupt mask to CPU1 + 13 + 1 + + + DMA2_CH7_IM + Peripheral DMA2 CH7 interrupt mask to CPU1 + 14 + 1 + + + DMAM_UX1_IM + Peripheral DMAM UX1 interrupt mask to CPU1 + 15 + 1 + + + PVM1IM + Peripheral PVM1IM interrupt mask to CPU1 + 16 + 1 + + + PVM3IM + Peripheral PVM3IM interrupt mask to CPU1 + 18 + 1 + + + PVDIM + Peripheral PVDIM interrupt mask to CPU1 + 20 + 1 + + + TSCIM + Peripheral TSCIM interrupt mask to CPU1 + 21 + 1 + + + LCDIM + Peripheral LCDIM interrupt mask to CPU1 + 22 + 1 + + + + + SIPCR + SIPCR + secure IP control register + 0x3C + 0x20 + read-write + 0x00000000 + + + SAES1 + Enable AES1 KEY[7:0] security. + 0 + 1 + + + SAES2 + Enable AES2 security. + 1 + 1 + + + SPKA + Enable PKA security + 2 + 1 + + + SRNG + Enable True RNG security + 3 + 1 + + + + + + + RNG + Random number generator + RNG + 0x58001000 + + 0x0 + 0x400 + registers + + + True_RNG + True random number generator + interrupt + 53 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RNGEN + Random number generator enable + 2 + 1 + + + IE + Interrupt enable + 3 + 1 + + + BYP + Bypass mode enable + 6 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + AES1 + Advanced encryption standard hardware accelerator 1 + AES1 + 0x50060000 + + 0x0 + 0x400 + registers + + + AES1 + AES1 global interrupt + 51 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + NPBLB + Number of padding bytes in last block of payload + 20 + 4 + + + KEYSIZE + Key size selection + 18 + 1 + + + CHMOD2 + AES chaining mode Bit2 + 16 + 1 + + + GCMPH + Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected + 13 + 2 + + + DMAOUTEN + Enable DMA management of data output phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag Clear + 7 + 1 + + + CHMOD10 + AES chaining mode Bit1 Bit0 + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and data out to/from the cryptographic block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + BUSY + Busy flag + 3 + 1 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR [127:96]) + 0 + 32 + + + + + KEYR4 + KEYR4 + key register 4 + 0x30 + 0x20 + read-write + 0x00000000 + + + AES_KEYR4 + AES key register (MSB key [159:128]) + 0 + 32 + + + + + KEYR5 + KEYR5 + key register 5 + 0x34 + 0x20 + read-write + 0x00000000 + + + AES_KEYR5 + AES key register (MSB key [191:160]) + 0 + 32 + + + + + KEYR6 + KEYR6 + key register 6 + 0x38 + 0x20 + read-write + 0x00000000 + + + AES_KEYR6 + AES key register (MSB key [223:192]) + 0 + 32 + + + + + KEYR7 + KEYR7 + key register 7 + 0x3C + 0x20 + read-write + 0x00000000 + + + AES_KEYR7 + AES key register (MSB key [255:224]) + 0 + 32 + + + + + SUSP0R + SUSP0R + AES suspend register 0 + 0x40 + 0x20 + read-write + 0x00000000 + + + AES_SUSP0R + AES suspend register 0 + 0 + 32 + + + + + SUSP1R + SUSP1R + AES suspend register 1 + 0x44 + 0x20 + read-write + 0x00000000 + + + AES_SUSP1R + AES suspend register 1 + 0 + 32 + + + + + SUSP2R + SUSP2R + AES suspend register 2 + 0x48 + 0x20 + read-write + 0x00000000 + + + AES_SUSP2R + AES suspend register 2 + 0 + 32 + + + + + SUSP3R + SUSP3R + AES suspend register 3 + 0x4C + 0x20 + read-write + 0x00000000 + + + AES_SUSP3R + AES suspend register 3 + 0 + 32 + + + + + SUSP4R + SUSP4R + AES suspend register 4 + 0x50 + 0x20 + read-write + 0x00000000 + + + AES_SUSP4R + AES suspend register 4 + 0 + 32 + + + + + SUSP5R + SUSP5R + AES suspend register 5 + 0x54 + 0x20 + read-write + 0x00000000 + + + AES_SUSP5R + AES suspend register 5 + 0 + 32 + + + + + SUSP6R + SUSP6R + AES suspend register 6 + 0x58 + 0x20 + read-write + 0x00000000 + + + AES_SUSP6R + AES suspend register 6 + 0 + 32 + + + + + SUSP7R + SUSP7R + AES suspend register 7 + 0x5C + 0x20 + read-write + 0x00000000 + + + AES_SUSP7R + AES suspend register 7 + 0 + 32 + + + + + HWCFR + HWCFR + AES hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000002 + + + CFG4 + HW Generic 4 + 12 + 4 + + + CFG3 + HW Generic 3 + 8 + 4 + + + CFG2 + HW Generic 2 + 4 + 4 + + + CFG1 + HW Generic 1 + 0 + 4 + + + + + VERR + VERR + AES version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MAJREV + Major revision + 4 + 4 + + + MINREV + Minor revision + 0 + 4 + + + + + IPIDR + IPIDR + AES identification register + 0x3F8 + 0x20 + read-only + 0x00170023 + + + ID + Identification code + 0 + 32 + + + + + SIDR + SIDR + AES size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + ID + Size Identification code + 0 + 32 + + + + + + + AES2 + Advanced encryption standard hardware accelerator 1 + AES1 + 0x58001800 + + 0x0 + 0x400 + registers + + + AES2 + AES2 global interrupt + 52 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + NPBLB + Number of padding bytes in last block of payload + 20 + 4 + + + KEYSIZE + Key size selection + 18 + 1 + + + CHMOD2 + AES chaining mode Bit2 + 16 + 1 + + + GCMPH + Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected + 13 + 2 + + + DMAOUTEN + Enable DMA management of data output phase + 12 + 1 + + + DMAINEN + Enable DMA management of data input phase + 11 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + CCFIE + CCF flag interrupt enable + 9 + 1 + + + ERRC + Error clear + 8 + 1 + + + CCFC + Computation Complete Flag Clear + 7 + 1 + + + CHMOD10 + AES chaining mode Bit1 Bit0 + 5 + 2 + + + MODE + AES operating mode + 3 + 2 + + + DATATYPE + Data type selection (for data in and data out to/from the cryptographic block) + 1 + 2 + + + EN + AES enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x00000000 + + + BUSY + Busy flag + 3 + 1 + + + WRERR + Write error flag + 2 + 1 + + + RDERR + Read error flag + 1 + 1 + + + CCF + Computation complete flag + 0 + 1 + + + + + DINR + DINR + data input register + 0x8 + 0x20 + read-write + 0x00000000 + + + AES_DINR + Data Input Register + 0 + 32 + + + + + DOUTR + DOUTR + data output register + 0xC + 0x20 + read-only + 0x00000000 + + + AES_DOUTR + Data output register + 0 + 32 + + + + + KEYR0 + KEYR0 + key register 0 + 0x10 + 0x20 + read-write + 0x00000000 + + + AES_KEYR0 + Data Output Register (LSB key [31:0]) + 0 + 32 + + + + + KEYR1 + KEYR1 + key register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + AES_KEYR1 + AES key register (key [63:32]) + 0 + 32 + + + + + KEYR2 + KEYR2 + key register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + AES_KEYR2 + AES key register (key [95:64]) + 0 + 32 + + + + + KEYR3 + KEYR3 + key register 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + AES_KEYR3 + AES key register (MSB key [127:96]) + 0 + 32 + + + + + IVR0 + IVR0 + initialization vector register 0 + 0x20 + 0x20 + read-write + 0x00000000 + + + AES_IVR0 + initialization vector register (LSB IVR [31:0]) + 0 + 32 + + + + + IVR1 + IVR1 + initialization vector register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + AES_IVR1 + Initialization Vector Register (IVR [63:32]) + 0 + 32 + + + + + IVR2 + IVR2 + initialization vector register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + AES_IVR2 + Initialization Vector Register (IVR [95:64]) + 0 + 32 + + + + + IVR3 + IVR3 + initialization vector register 3 + 0x2C + 0x20 + read-write + 0x00000000 + + + AES_IVR3 + Initialization Vector Register (MSB IVR [127:96]) + 0 + 32 + + + + + KEYR4 + KEYR4 + key register 4 + 0x30 + 0x20 + read-write + 0x00000000 + + + AES_KEYR4 + AES key register (MSB key [159:128]) + 0 + 32 + + + + + KEYR5 + KEYR5 + key register 5 + 0x34 + 0x20 + read-write + 0x00000000 + + + AES_KEYR5 + AES key register (MSB key [191:160]) + 0 + 32 + + + + + KEYR6 + KEYR6 + key register 6 + 0x38 + 0x20 + read-write + 0x00000000 + + + AES_KEYR6 + AES key register (MSB key [223:192]) + 0 + 32 + + + + + KEYR7 + KEYR7 + key register 7 + 0x3C + 0x20 + read-write + 0x00000000 + + + AES_KEYR7 + AES key register (MSB key [255:224]) + 0 + 32 + + + + + SUSP0R + SUSP0R + AES suspend register 0 + 0x40 + 0x20 + read-write + 0x00000000 + + + AES_SUSP0R + AES suspend register 0 + 0 + 32 + + + + + SUSP1R + SUSP1R + AES suspend register 1 + 0x44 + 0x20 + read-write + 0x00000000 + + + AES_SUSP1R + AES suspend register 1 + 0 + 32 + + + + + SUSP2R + SUSP2R + AES suspend register 2 + 0x48 + 0x20 + read-write + 0x00000000 + + + AES_SUSP2R + AES suspend register 2 + 0 + 32 + + + + + SUSP3R + SUSP3R + AES suspend register 3 + 0x4C + 0x20 + read-write + 0x00000000 + + + AES_SUSP3R + AES suspend register 3 + 0 + 32 + + + + + SUSP4R + SUSP4R + AES suspend register 4 + 0x50 + 0x20 + read-write + 0x00000000 + + + AES_SUSP4R + AES suspend register 4 + 0 + 32 + + + + + SUSP5R + SUSP5R + AES suspend register 5 + 0x54 + 0x20 + read-write + 0x00000000 + + + AES_SUSP5R + AES suspend register 5 + 0 + 32 + + + + + SUSP6R + SUSP6R + AES suspend register 6 + 0x58 + 0x20 + read-write + 0x00000000 + + + AES_SUSP6R + AES suspend register 6 + 0 + 32 + + + + + SUSP7R + SUSP7R + AES suspend register 7 + 0x5C + 0x20 + read-write + 0x00000000 + + + AES_SUSP7R + AES suspend register 7 + 0 + 32 + + + + + HWCFR + HWCFR + AES hardware configuration register + 0x60 + 0x20 + read-only + 0x00000002 + + + CFG4 + HW Generic 4 + 12 + 4 + + + CFG3 + HW Generic 3 + 8 + 4 + + + CFG2 + HW Generic 2 + 4 + 4 + + + CFG1 + HW Generic 1 + 0 + 4 + + + + + VERR + VERR + AES version register + 0x64 + 0x20 + read-only + 0x00000010 + + + MAJREV + Major revision + 4 + 4 + + + MINREV + Minor revision + 0 + 4 + + + + + IPIDR + IPIDR + AES identification register + 0x68 + 0x20 + read-only + 0x00170023 + + + ID + Identification code + 0 + 32 + + + + + SIDR + SIDR + AES size ID register + 0x6C + 0x20 + read-only + 0x00170023 + + + ID + Size Identification code + 0 + 32 + + + + + + + HSEM + HSEM + Hardware_Semaphore + 0x58001400 + + 0x0 + 0x400 + registers + + + HSEM + Semaphore interrupt 0 to CPU1 + 46 + + + + R0 + R0 + Semaphore 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R1 + R1 + Semaphore 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R2 + R2 + Semaphore 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R3 + R3 + Semaphore 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R4 + R4 + Semaphore 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R5 + R5 + Semaphore 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R6 + R6 + Semaphore 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R7 + R7 + Semaphore 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R8 + R8 + Semaphore 8 register + 0x20 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R9 + R9 + Semaphore 9 register + 0x24 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R10 + R10 + Semaphore 10 register + 0x28 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R11 + R11 + Semaphore 11 register + 0x2C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R12 + R12 + Semaphore 12 register + 0x30 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R13 + R13 + Semaphore 13 register + 0x34 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R14 + R14 + Semaphore 14 register + 0x38 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R15 + R15 + Semaphore 15 register + 0x3C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R16 + R16 + Semaphore 16 register + 0x40 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R17 + R17 + Semaphore 17 register + 0x44 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R18 + R18 + Semaphore 18 register + 0x48 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R19 + R19 + Semaphore 19 register + 0x4C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R20 + R20 + Semaphore 20 register + 0x50 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R21 + R21 + Semaphore 21 register + 0x54 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R22 + R22 + Semaphore 22 register + 0x58 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R23 + R23 + Semaphore 23 register + 0x5C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R24 + R24 + Semaphore 24 register + 0x60 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R25 + R25 + Semaphore 25 register + 0x64 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R26 + R26 + Semaphore 26 register + 0x68 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R27 + R27 + Semaphore 27 register + 0x6C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R28 + R28 + Semaphore 28 register + 0x70 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R29 + R29 + Semaphore 29 register + 0x74 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R30 + R30 + Semaphore 30 register + 0x78 + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + R31 + R31 + Semaphore 31 register + 0x7C + 0x20 + read-write + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR0 + RLR0 + Semaphore 0 read lock register + 0x80 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR1 + RLR1 + Semaphore 1 read lock register + 0x84 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR2 + RLR2 + Semaphore 2 read lock register + 0x88 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR3 + RLR3 + Semaphore 3 read lock register + 0x8C + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR4 + RLR4 + Semaphore 4 read lock read lock register + 0x90 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR5 + RLR5 + Semaphore 5 read lock register + 0x94 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR6 + RLR6 + Semaphore 6 read lock register + 0x98 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR7 + RLR7 + Semaphore 7 read lock register + 0x9C + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR8 + RLR8 + Semaphore 8 read lock register + 0xA0 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR9 + RLR9 + Semaphore 9 read lock register + 0xA4 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR10 + RLR10 + Semaphore 10 read lock register + 0xA8 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR11 + RLR11 + Semaphore 11 read lock register + 0xAC + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR12 + RLR12 + Semaphore 12 read lock register + 0xB0 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR13 + RLR13 + Semaphore 13 read lock register + 0xB4 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR14 + RLR14 + Semaphore 14 read lock register + 0xB8 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR15 + RLR15 + Semaphore 15 read lock register + 0xBC + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR16 + RLR16 + Semaphore 16 read lock register + 0xC0 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR17 + RLR17 + Semaphore 17 read lock register + 0xC4 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR18 + RLR18 + Semaphore 18 read lock register + 0xC8 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR19 + RLR19 + Semaphore 19 read lock register + 0xCC + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR20 + RLR20 + Semaphore 20 read lock register + 0xD0 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR21 + RLR21 + Semaphore 21 read lock register + 0xD4 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR22 + RLR22 + Semaphore 22 read lock register + 0xD8 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR23 + RLR23 + Semaphore 23 read lock register + 0xDC + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR24 + RLR24 + Semaphore 24 read lock register + 0xE0 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR25 + RLR25 + Semaphore 25 read lock register + 0xE4 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR26 + RLR26 + Semaphore 26 read lock register + 0xE8 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR27 + RLR27 + Semaphore 27 read lock register + 0xEC + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR28 + RLR28 + Semaphore 28 read lock register + 0xF0 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR29 + RLR29 + Semaphore 29 read lock register + 0xF4 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR30 + RLR30 + Semaphore 30 read lock register + 0xF8 + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + RLR31 + RLR31 + Semaphore 31 read lock register + 0xFC + 0x20 + read-only + 0x00000000 + + + LOCK + lock indication + 31 + 1 + + + COREID + Semaphore CoreID + 8 + 4 + + + PROCID + Semaphore ProcessID + 0 + 8 + + + + + CR + CR + Semaphore Clear register + 0x140 + 0x20 + read-write + 0x00000000 + + + KEY + Semaphore clear Key + 16 + 16 + + + COREID + CoreID of semaphore to be cleared + 8 + 4 + + + + + KEYR + KEYR + Interrupt clear register + 0x144 + 0x20 + read-write + 0x00000000 + + + KEY + Semaphore Clear Key + 16 + 16 + + + + + HWCFGR2 + HWCFGR2 + Semaphore hardware configuration register 2 + 0x3EC + 0x20 + read-only + 0x00000084 + + + MASTERID4 + Hardware Configuration valid bus masters ID4 + 12 + 4 + + + MASTERID3 + Hardware Configuration valid bus masters ID3 + 8 + 4 + + + MASTERID2 + Hardware Configuration valid bus masters ID2 + 4 + 4 + + + MASTERID1 + Hardware Configuration valid bus masters ID1 + 0 + 4 + + + + + HWCFGR1 + HWCFGR1 + Semaphore hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x00000220 + + + NBINT + Hardware Configuration number of interrupts supported number of master IDs + 8 + 4 + + + NBSEM + Hardware Configuration number of semaphores + 0 + 8 + + + + + VERR + VERR + HSEM version register + 0x3F4 + 0x20 + read-only + 0x00000020 + + + MAJREV + Major Revision + 4 + 4 + + + MINREV + Minor Revision + 0 + 4 + + + + + IPIDR + IPIDR + HSEM indentification register + 0x3F8 + 0x20 + read-only + 0x00100072 + + + ID + Identification Code + 0 + 32 + + + + + SIDR + SIDR + HSEM size indentification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size Identification Code + 0 + 32 + + + + + C1IER0 + C1IER0 + HSEM Interrupt enable register + 0x100 + 0x20 + read-write + 0x00000000 + + + ISEm + CPU(n) semaphore m enable bit + 0 + 32 + + + + + C1ICR + C1ICR + HSEM Interrupt clear register + 0x104 + 0x20 + read-write + 0x00000000 + + + ISCm + CPU(n) semaphore m clear bit + 0 + 32 + + + + + C1ISR + C1ISR + HSEM Interrupt status register + 0x108 + 0x20 + read-only + 0x00000000 + + + ISFm + CPU(n) semaphore m status bit before enable (mask) + 0 + 32 + + + + + C1MISR + C1MISR + HSEM Masked interrupt status register + 0x10C + 0x20 + read-only + 0x00000000 + + + MISFm + masked CPU(n) semaphore m status bit after enable (mask). + 0 + 32 + + + + + C2IER0 + C2IER0 + HSEM Interrupt enable register + 0x110 + 0x20 + read-write + 0x00000000 + + + ISEm + CPU(2) semaphore m enable bit. + 0 + 32 + + + + + C2ICR + C2ICR + HSEM Interrupt clear register + 0x114 + 0x20 + read-write + 0x00000000 + + + ISCm + CPU(2) semaphore m clear bit + 0 + 32 + + + + + C2ISR + C2ISR + HSEM Interrupt status register + 0x118 + 0x20 + read-only + 0x00000000 + + + ISFm + CPU(2) semaphore m status bit before enable (mask). + 0 + 32 + + + + + C2MISR + C2MISR + HSEM Masked interrupt status register + 0x11C + 0x20 + read-only + 0x00000000 + + + MISFm + masked CPU(2) semaphore m status bit after enable (mask). + 0 + 32 + + + + + + + ADC + Analog to Digital Converter instance 1 + ADC + 0x50040000 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 18 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + ADC group injected contexts queue overflow flag + 10 + 1 + + + AWD3 + ADC analog watchdog 3 flag + 9 + 1 + + + AWD2 + ADC analog watchdog 2 flag + 8 + 1 + + + AWD1 + ADC analog watchdog 1 flag + 7 + 1 + + + JEOS + ADC group injected end of sequence conversions flag + 6 + 1 + + + JEOC + ADC group injected end of unitary conversion flag + 5 + 1 + + + OVR + ADC group regular overrun flag + 4 + 1 + + + EOS + ADC group regular end of sequence conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling flag + 1 + 1 + + + ADRDY + ADC ready flag + 0 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + ADC group injected contexts queue overflow interrupt + 10 + 1 + + + AWD3IE + ADC analog watchdog 3 interrupt + 9 + 1 + + + AWD2IE + ADC analog watchdog 2 interrupt + 8 + 1 + + + AWD1IE + ADC analog watchdog 1 interrupt + 7 + 1 + + + JEOSIE + ADC group injected end of sequence conversions interrupt + 6 + 1 + + + JEOCIE + ADC group injected end of unitary conversion interrupt + 5 + 1 + + + OVRIE + ADC group regular overrun interrupt + 4 + 1 + + + EOSIE + ADC group regular end of sequence conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling interrupt + 1 + 1 + + + ADRDYIE + ADC ready interrupt + 0 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC calibration + 31 + 1 + + + ADCALDIF + ADC differential mode for calibration + 30 + 1 + + + DEEPPWD + ADC deep power down enable + 29 + 1 + + + ADVREGEN + ADC voltage regulator enable + 28 + 1 + + + JADSTP + ADC group injected conversion stop + 5 + 1 + + + ADSTP + ADC group regular conversion stop + 4 + 1 + + + JADSTART + ADC group injected conversion start + 3 + 1 + + + ADSTART + ADC group regular conversion start + 2 + 1 + + + ADDIS + ADC disable + 1 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR + CFGR + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + ADC group injected contexts queue disable + 31 + 1 + + + AWDCH1CH + ADC analog watchdog 1 monitored channel selection + 26 + 5 + + + JAUTO + ADC group injected automatic trigger mode + 25 + 1 + + + JAWD1EN + ADC analog watchdog 1 enable on scope ADC group injected + 24 + 1 + + + AWD1EN + ADC analog watchdog 1 enable on scope ADC group regular + 23 + 1 + + + AWD1SGL + ADC analog watchdog 1 monitoring a single channel or all channels + 22 + 1 + + + JQM + ADC group injected contexts queue mode + 21 + 1 + + + JDISCEN + ADC group injected sequencer discontinuous mode + 20 + 1 + + + DISCNUM + ADC group regular sequencer discontinuous number of ranks + 17 + 3 + + + DISCEN + ADC group regular sequencer discontinuous mode + 16 + 1 + + + AUTDLY + ADC low power auto wait + 14 + 1 + + + CONT + ADC group regular continuous conversion mode + 13 + 1 + + + OVRMOD + ADC group regular overrun configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger source + 6 + 4 + + + ALIGN + ADC data alignement + 5 + 1 + + + RES + ADC data resolution + 3 + 2 + + + DMACFG + ADC DMA transfer configuration + 1 + 1 + + + DMAEN + ADC DMA transfer enable + 0 + 1 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + ROVSM + ADC oversampling mode managing interlaced conversions of ADC group regular and group injected + 10 + 1 + + + TOVS + ADC oversampling discontinuous mode (triggered mode) for ADC group regular + 9 + 1 + + + OVSS + ADC oversampling shift + 5 + 4 + + + OVSR + ADC oversampling ratio + 2 + 3 + + + JOVSE + ADC oversampler enable on scope ADC group injected + 1 + 1 + + + ROVSE + ADC oversampler enable on scope ADC group regular + 0 + 1 + + + + + SMPR1 + SMPR1 + ADC sampling time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + ADC channel 9 sampling time selection + 27 + 3 + + + SMP8 + ADC channel 8 sampling time selection + 24 + 3 + + + SMP7 + ADC channel 7 sampling time selection + 21 + 3 + + + SMP6 + ADC channel 6 sampling time selection + 18 + 3 + + + SMP5 + ADC channel 5 sampling time selection + 15 + 3 + + + SMP4 + ADC channel 4 sampling time selection + 12 + 3 + + + SMP3 + ADC channel 3 sampling time selection + 9 + 3 + + + SMP2 + ADC channel 2 sampling time selection + 6 + 3 + + + SMP1 + ADC channel 1 sampling time selection + 3 + 3 + + + + + SMPR2 + SMPR2 + ADC sampling time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + ADC channel 18 sampling time selection + 24 + 3 + + + SMP17 + ADC channel 17 sampling time selection + 21 + 3 + + + SMP16 + ADC channel 16 sampling time selection + 18 + 3 + + + SMP15 + ADC channel 15 sampling time selection + 15 + 3 + + + SMP14 + ADC channel 14 sampling time selection + 12 + 3 + + + SMP13 + ADC channel 13 sampling time selection + 9 + 3 + + + SMP12 + ADC channel 12 sampling time selection + 6 + 3 + + + SMP11 + ADC channel 11 sampling time selection + 3 + 3 + + + SMP10 + ADC channel 10 sampling time selection + 0 + 3 + + + + + TR1 + TR1 + ADC analog watchdog 1 threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + ADC analog watchdog 1 threshold high + 16 + 12 + + + LT1 + ADC analog watchdog 1 threshold low + 0 + 12 + + + + + TR2 + TR2 + ADC analog watchdog 2 threshold register + 0x24 + 0x20 + read-write + 0x0FFF0000 + + + HT2 + ADC analog watchdog 2 threshold high + 16 + 8 + + + LT2 + ADC analog watchdog 2 threshold low + 0 + 8 + + + + + TR3 + TR3 + ADC analog watchdog 3 threshold register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + HT3 + ADC analog watchdog 3 threshold high + 16 + 8 + + + LT3 + ADC analog watchdog 3 threshold low + 0 + 8 + + + + + SQR1 + SQR1 + ADC group regular sequencer ranks register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + ADC group regular sequencer rank 4 + 24 + 5 + + + SQ3 + ADC group regular sequencer rank 3 + 18 + 5 + + + SQ2 + ADC group regular sequencer rank 2 + 12 + 5 + + + SQ1 + ADC group regular sequencer rank 1 + 6 + 5 + + + L3 + L3 + 0 + 4 + + + + + SQR2 + SQR2 + ADC group regular sequencer ranks register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + ADC group regular sequencer rank 9 + 24 + 5 + + + SQ8 + ADC group regular sequencer rank 8 + 18 + 5 + + + SQ7 + ADC group regular sequencer rank 7 + 12 + 5 + + + SQ6 + ADC group regular sequencer rank 6 + 6 + 5 + + + SQ5 + ADC group regular sequencer rank 5 + 0 + 5 + + + + + SQR3 + SQR3 + ADC group regular sequencer ranks register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + ADC group regular sequencer rank 14 + 24 + 5 + + + SQ13 + ADC group regular sequencer rank 13 + 18 + 5 + + + SQ12 + ADC group regular sequencer rank 12 + 12 + 5 + + + SQ11 + ADC group regular sequencer rank 11 + 6 + 5 + + + SQ10 + ADC group regular sequencer rank 10 + 0 + 5 + + + + + SQR4 + SQR4 + ADC group regular sequencer ranks register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + ADC group regular sequencer rank 16 + 6 + 5 + + + SQ15 + ADC group regular sequencer rank 15 + 0 + 5 + + + + + DR + DR + ADC group regular conversion data register + 0x40 + 0x20 + 0x00000000 + + + RDATA_0_6 + Regular Data converted 0_6 + 0 + 6 + read-write + + + RDATA_7_15 + 15 + 7 + 9 + read-only + + + + + JSQR + JSQR + ADC group injected sequencer register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + ADC group injected sequencer rank 4 + 26 + 5 + + + JSQ3 + ADC group injected sequencer rank 3 + 20 + 5 + + + JSQ2 + ADC group injected sequencer rank 2 + 14 + 5 + + + JSQ1 + ADC group injected sequencer rank 1 + 8 + 5 + + + JEXTEN + ADC group injected external trigger polarity + 6 + 2 + + + JEXTSEL + ADC group injected external trigger source + 2 + 4 + + + JL + ADC group injected sequencer scan length + 0 + 2 + + + + + OFR1 + OFR1 + ADC offset number 1 register + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + ADC offset number 1 enable + 31 + 1 + + + OFFSET1_CH + ADC offset number 1 channel selection + 26 + 5 + + + OFFSET1 + ADC offset number 1 offset level + 0 + 12 + + + + + OFR2 + OFR2 + ADC offset number 2 register + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET2_EN + ADC offset number 2 enable + 31 + 1 + + + OFFSET2_CH + ADC offset number 2 channel selection + 26 + 5 + + + OFFSET2 + ADC offset number 2 offset level + 0 + 12 + + + + + OFR3 + OFR3 + ADC offset number 3 register + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET3_EN + ADC offset number 3 enable + 31 + 1 + + + OFFSET3_CH + ADC offset number 3 channel selection + 26 + 5 + + + OFFSET3 + ADC offset number 3 offset level + 0 + 12 + + + + + OFR4 + OFR4 + ADC offset number 4 register + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET4_EN + ADC offset number 4 enable + 31 + 1 + + + OFFSET4_CH + ADC offset number 4 channel selection + 26 + 5 + + + OFFSET4 + ADC offset number 4 offset level + 0 + 12 + + + + + JDR1 + JDR1 + ADC group injected sequencer rank 1 register + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + ADC group injected sequencer rank 1 conversion data + 0 + 16 + + + + + JDR2 + JDR2 + ADC group injected sequencer rank 2 register + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + ADC group injected sequencer rank 2 conversion data + 0 + 16 + + + + + JDR3 + JDR3 + ADC group injected sequencer rank 3 register + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + ADC group injected sequencer rank 3 conversion data + 0 + 16 + + + + + JDR4 + JDR4 + ADC group injected sequencer rank 4 register + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + ADC group injected sequencer rank 4 conversion data + 0 + 16 + + + + + AWD2CR + AWD2CR + ADC analog watchdog 2 configuration register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + ADC analog watchdog 2 monitored channel selection + 0 + 19 + + + + + AWD3CR + AWD3CR + ADC analog watchdog 3 configuration register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + ADC analog watchdog 3 monitored channel selection + 0 + 19 + + + + + DIFSEL + DIFSEL + ADC channel differential or single-ended mode selection register + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + ADC channel differential or single-ended mode for channel 0 + 0 + 1 + read-only + + + DIFSEL_1_15 + ADC channel differential or single-ended mode for channels 1 to 15 + 1 + 15 + read-write + + + DIFSEL_16_18 + ADC channel differential or single-ended mode for channels 18 to 16 + 16 + 3 + read-only + + + + + CALFACT + CALFACT + ADC calibration factors register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + ADC calibration factor in differential mode + 16 + 7 + + + CALFACT_S + ADC calibration factor in single-ended mode + 0 + 7 + + + + + CCR + CCR + ADC common control register + 0x308 + 0x20 + read-write + 0x00000000 + + + VBATEN + VBAT enable + 24 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + VREFEN + 22 + 1 + + + PRESC + ADC prescaler + 18 + 4 + + + CKMODE + ADC clock mode + 16 + 2 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x48000400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFEBF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000100 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + 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lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 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configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 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reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + General-purpose I/Os + GPIO + 0x48001000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x000003FF + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + + + + + GPIOH + General-purpose I/Os + GPIO + 0x48001C00 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x000000CF + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFSEL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + + + + + SAI1 + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 38 + + + + GCR + GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCOUT + Synchronization outputs + 4 + 2 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKEN + Master clock generation enable + 27 + 1 + + + OSR + Oversampling ratio for master clock + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000008 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKEN + Master clock generation enable + 27 + 1 + + + OSR + Oversampling ratio for master clock + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-only + 0x00000008 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PDMCR + PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + CKEN4 + Clock enable of bitstream clock number 4 + 11 + 1 + + + CKEN3 + Clock enable of bitstream clock number 3 + 10 + 1 + + + CKEN2 + Clock enable of bitstream clock number 2 + 9 + 1 + + + CKEN1 + Clock enable of bitstream clock number 1 + 8 + 1 + + + MICNBR + Number of microphones + 4 + 2 + + + PDMEN + PDM enable + 0 + 1 + + + + + PDMDLY + PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM4R + Delay line for second microphone of pair 4 + 28 + 3 + + + DLYM4L + Delay line for first microphone of pair 4 + 24 + 3 + + + DLYM3R + Delay line for second microphone of pair 3 + 20 + 3 + + + DLYM3L + Delay line for first microphone of pair 3 + 16 + 3 + + + DLYM2R + Delay line for second microphone of pair 2 + 12 + 3 + + + DLYM2L + Delay line for first microphone of pair 2 + 8 + 3 + + + DLYM1R + Delay line for second microphone of pair 1 + 4 + 3 + + + DLYM1L + Delay line for first microphone of pair 1 + 0 + 3 + + + + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output compare 2 clear enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload enable + 11 + 1 + + + OC2FE + Output compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output compare 1 clear enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload enable + 3 + 1 + + + OC1FE + Output compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT_H + High counter value (TIM2 only) + 16 + 15 + read-write + + + CNT_L + Low counter value + 0 + 16 + read-write + + + UIFCPY + Value depends on IUFREMAP in TIM2_CR1. + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write 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+ 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR + OR + TIM2 option register + 0x50 + 0x20 + read-write + 0x0000 + + + TI4_RMP + Input capture 4 remap + 2 + 2 + + + ETR_RMP + External trigger remap + 1 + 1 + + + ITR_RMP + Internal trigger remap + 0 + 1 + + + + + AF + AF + TIM2 alternate function option register 1 + 0x60 + 0x20 + read-write + 0x0000 + + + ETRSEL + External trigger source selection + 14 + 3 + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarit + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarit + 11 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_2 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR + OR + TIM16 option register 1 + 0x50 + 0x20 + read-write + 0x0000 + + + TI1_RMP + Input capture 1 remap + 0 + 2 + + + + + AF1 + AF1 + TIM17 option register 1 + 0x60 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarit + 11 + 1 + + + + + + + TIM17 + General purpose timers + TIM + 0x40014800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0x8 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarit + 11 + 1 + + + + + SR + SR + status register + 0xC + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x10 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x14 + 0x20 + read-write + 0x00000000 + + + OC1M_2 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x1C + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x20 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x24 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x28 + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x2C + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x34 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x38 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR + OR + TIM16 option register 1 + 0x40 + 0x20 + read-write + 0x0000 + + + TI1_RMP + Input capture 1 remap + 0 + 2 + + + + + AF1 + AF1 + TIM17 option register 1 + 0x44 + 0x20 + read-write + 0x0000 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarit + 11 + 1 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK + Timer 1 break interrupt + 24 + + + TIM1_UP + Timer 1 Update + 25 + + + TIM1_TRG_COM_TIM17 + TIM1 Trigger and Commutation interrupts and + TIM17 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + TG + Trigger generation + 6 + 1 + + + BG + Break generation + 7 + 1 + + + B2G + Break 2 generation + 8 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + C1F + Input capture 1 filter + 4 + 4 + + + CC2S + capture/Compare 2 selection + 8 + 2 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + IC2F + Input capture 2 filter + 12 + 4 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + CCMR1_Input + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (output mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + C3PSC + Input capture 3 prescaler + 2 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + IC4F + Input capture 4 filter + 12 + 4 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BK2F + Break 2 filter + 20 + 4 + + + BK2E + Break 2 enable + 24 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst accesses + 0 + 16 + + + + + OR + OR + DMA address for full transfer + 0x50 + 0x20 + read-write + 0x0000 + + + TIM1_ETR_ADC1_RMP + TIM1_ETR_ADC1 remapping capability + 0 + 2 + + + TI1_RMP + Input Capture 1 remap + 4 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 1 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + AF1 + AF1 + DMA address for full transfer + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 3 + + + + + AF2 + AF2 + DMA address for full transfer + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DFBK0E + BRK2 DFSDM_BREAK0 enable + 8 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + + + LPTIM1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPtimer 1 global interrupt + 47 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + COUNTRST + Counter reset + 3 + 1 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + OR + OR + Option Register + 0x20 + 0x20 + read-write + 0x00000000 + + + OR1 + Option register bit 1 + 0 + 1 + + + OR2 + Option register bit 2 + 1 + 1 + + + + + + + LPTIM2 + 0x40009400 + + LPTIM2 + LPtimer 2 global interrupt + 48 + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 36 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFIFO Full interrupt enable + 31 + 1 + + + TXFEIE + TXFIFO empty interrupt enable + 30 + 1 + + + FIFOEN + FIFO mode enable + 29 + 1 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + When the DSI_NSS bit is set, the NSS pin input will be ignored + 3 + 1 + + + SLVEN + Synchronous Slave mode enable + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFIFO threshold configuration + 29 + 3 + + + RXFTIE + RXFIFO threshold interrupt enable + 28 + 1 + + + RXFTCFG + Receive FIFO threshold configuration + 25 + 3 + + + TCBGTIE + Tr Complete before guard time, interrupt enable + 24 + 1 + + + TXFTIE + threshold interrupt enable + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR_4_15 + 0 + 16 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFIFO threshold flag + 27 + 1 + + + RXFT + RXFIFO threshold flag + 26 + 1 + + + TCBGT + Transmission complete before guard time flag + 25 + 1 + + + RXFF + RXFIFO Full + 24 + 1 + + + TXFE + TXFIFO Empty + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + SPI slave underrun error flag + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + SPI slave underrun clear flag + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + Transmission complete before Guard time clear flag + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFIFO empty clear flag + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + Clock prescaler + 0 + 4 + + + + + + + LPUART1 + 0x40008000 + + LPUART1 + LPUART1 global interrupt + 37 + + + + SPI1 + Serial peripheral interface/Inter-IC sound + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI 1 global interrupt + 34 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI1 global interrupt + 35 + + + + VREFBUF + Voltage reference buffer + VREF + 0x40010030 + + 0x0 + 0xD0 + registers + + + + CSR + CSR + VREF control and status register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Voltage reference buffer enable + 0 + 1 + read-write + + + HIZ + High impedance mode + 1 + 1 + read-write + + + VRS + Voltage reference scale + 2 + 1 + read-write + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + + + CCR + CCR + calibration control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code + 0 + 6 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP + RTC/TAMP/CSS on LSE through EXTI line 19 interrupt + 2 + + + RTC_WKUP + RTC wakeup interrupt through EXTI[19] + 3 + + + RTC_ALARM + RTC Alarms (A and B) interrupt through + AIEC + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + ITSE + timestamp on internal event enable + 24 + 1 + + + + + ISR + ISR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + ITSF + INTERNAL TIME-STAMP FLAG + 17 + 1 + read-write + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAMPCR + TAMPCR + tamper configuration register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP3E + Tamper 3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for tamper 3 + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection event + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMP1IE + Tamper 1 interrupt enable + 16 + 1 + + + TAMP1NOERASE + Tamper 1 no erase + 17 + 1 + + + TAMP1MF + Tamper 1 mask flag + 18 + 1 + + + TAMP2IE + Tamper 2 interrupt enable + 19 + 1 + + + TAMP2NOERASE + Tamper 2 no erase + 20 + 1 + + + TAMP2MF + Tamper 2 mask flag + 21 + 1 + + + TAMP3IE + Tamper 3 interrupt enable + 22 + 1 + + + TAMP3NOERASE + Tamper 3 no erase + 23 + 1 + + + TAMP3MF + Tamper 3 mask flag + 24 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + OR + OR + option register + 0x4C + 0x20 + read-write + 0x00000000 + + + RTC_ALARM_TYPE + RTC_ALARM on PC13 output type + 0 + 1 + + + RTC_OUT_RMP + RTC_OUT remap + 1 + 1 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 12 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace port and clock enable + 5 + 1 + + + TRGOEN + External trigger output enable + 28 + 1 + + + + + APB1FZR1 + APB1FZR1 + APB1 Low Freeze Register CPU1 + 0x3C + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + 0 + 1 + + + DBG_RTC_STOP + RTC counter stopped when core is halted + 10 + 1 + + + DBG_WWDG_STOP + WWDG counter stopped when core is halted + 11 + 1 + + + DBG_IWDG_STOP + IWDG counter stopped when core is halted + 12 + 1 + + + DBG_I2C1_STOP + Debug I2C1 SMBUS timeout stopped when Core is halted + 21 + 1 + + + DBG_I2C3_STOP + Debug I2C3 SMBUS timeout stopped when core is halted + 23 + 1 + + + DBG_LPTIM1_STOP + Debug LPTIM1 stopped when Core is halted + 31 + 1 + + + + + C2AP_B1FZR1 + C2AP_B1FZR1 + APB1 Low Freeze Register CPU2 + 0x40 + 0x20 + read-write + 0x0 + + + DBG_LPTIM2_STOP + LPTIM2 counter stopped when core is halted + 0 + 1 + + + DBG_RTC_STOP + RTC counter stopped when core is halted + 10 + 1 + + + DBG_IWDG_STOP + IWDG stopped when core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stopped when core is halted + 21 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout stopped when core is halted + 23 + 1 + + + DBG_LPTIM1_STOP + LPTIM1 counter stopped when core is halted + 31 + 1 + + + + + APB1FZR2 + APB1FZR2 + APB1 High Freeze Register CPU1 + 0x44 + 0x20 + read-write + 0x0 + + + DBG_LPTIM2_STOP + LPTIM2 counter stopped when core is halted + 5 + 1 + + + + + C2APB1FZR2 + C2APB1FZR2 + APB1 High Freeze Register CPU2 + 0x48 + 0x20 + read-write + 0x0 + + + DBG_LPTIM2_STOP + LPTIM2 counter stopped when core is halted + 5 + 1 + + + + + APB2FZR + APB2FZR + APB2 Freeze Register CPU1 + 0x4C + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + + + C2APB2FZR + C2APB2FZR + APB2 Freeze Register CPU2 + C2APB1FZR2 + 0x48 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + + + + + PKA + PKA + PKA + 0x58002000 + + 0x0 + 0x2000 + registers + + + PKA + Private key accelerator + interrupt + 29 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + ADDRERRIE + Address error interrupt enable + 20 + 1 + + + RAMERRIE + RAM error interrupt enable + 19 + 1 + + + PROCENDIE + End of operation interrupt enable + 17 + 1 + + + MODE + PKA Operation Mode + 8 + 6 + + + SECLVL + Security Enable + 2 + 1 + + + START + Start the operation + 1 + 1 + + + EN + Peripheral Enable + 0 + 1 + + + + + SR + SR + PKA status register + 0x4 + 0x20 + read-only + 0x00000000 + + + ADDRERRF + Address error flag + 20 + 1 + + + RAMERRF + RAM error flag + 19 + 1 + + + PROCENDF + PKA End of Operation flag + 17 + 1 + + + BUSY + PKA Operation in progress + 16 + 1 + + + + + CLRFR + CLRFR + PKA clear flag register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDRERRFC + Clear Address error flag + 20 + 1 + + + RAMERRFC + Clear RAM error flag + 19 + 1 + + + PROCENDFC + Clear PKA End of Operation flag + 17 + 1 + + + + + VERR + VERR + PKA version register + 0x1FF4 + 0x20 + read-only + 0x00000010 + + + MINREV + Minor revision + 0 + 4 + + + MAJREV + Major revision + 4 + 4 + + + + + IPIDR + IPIDR + PKA identification register + 0x1FF8 + 0x20 + read-only + 0x00170061 + + + ID + Identification Code + 0 + 32 + + + + + SIDR + SIDR + PKA size ID register + 0x1FFC + 0x20 + read-only + 0xA3C5DD08 + + + SID + Side Identification Code + 0 + 32 + + + + + + + IPCC + IPCC + IPCC + 0x58000C00 + + 0x0 + 0x400 + registers + + + IPCC_C1_RX_IT + IPCC CPU1 RX occupied interrupt + 44 + + + IPCC_C1_TX_IT + IPCC CPU1 TX free interrupt + 45 + + + + C1CR + C1CR + Control register CPU1 + 0x0 + 0x20 + read-write + 0x00000000 + + + TXFIE + processor 1 Transmit channel free interrupt enable + 16 + 1 + + + RXOIE + processor 1 Receive channel occupied interrupt enable + 0 + 1 + + + + + C1MR + C1MR + Mask register CPU1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + CH6FM + processor 1 Transmit channel 6 free interrupt mask + 21 + 1 + + + CH5FM + processor 1 Transmit channel 5 free interrupt mask + 20 + 1 + + + CH4FM + processor 1 Transmit channel 4 free interrupt mask + 19 + 1 + + + CH3FM + processor 1 Transmit channel 3 free interrupt mask + 18 + 1 + + + CH2FM + processor 1 Transmit channel 2 free interrupt mask + 17 + 1 + + + CH1FM + processor 1 Transmit channel 1 free interrupt mask + 16 + 1 + + + CH6OM + processor 1 Receive channel 6 occupied interrupt enable + 5 + 1 + + + CH5OM + processor 1 Receive channel 5 occupied interrupt enable + 4 + 1 + + + CH4OM + processor 1 Receive channel 4 occupied interrupt enable + 3 + 1 + + + CH3OM + processor 1 Receive channel 3 occupied interrupt enable + 2 + 1 + + + CH2OM + processor 1 Receive channel 2 occupied interrupt enable + 1 + 1 + + + CH1OM + processor 1 Receive channel 1 occupied interrupt enable + 0 + 1 + + + + + C1SCR + C1SCR + Status Set or Clear register CPU1 + 0x8 + 0x20 + write-only + 0x00000000 + + + CH6S + processor 1 Transmit channel 6 status set + 21 + 1 + + + CH5S + processor 1 Transmit channel 5 status set + 20 + 1 + + + CH4S + processor 1 Transmit channel 4 status set + 19 + 1 + + + CH3S + processor 1 Transmit channel 3 status set + 18 + 1 + + + CH2S + processor 1 Transmit channel 2 status set + 17 + 1 + + + CH1S + processor 1 Transmit channel 1 status set + 16 + 1 + + + CH6C + processor 1 Receive channel 6 status clear + 5 + 1 + + + CH5C + processor 1 Receive channel 5 status clear + 4 + 1 + + + CH4C + processor 1 Receive channel 4 status clear + 3 + 1 + + + CH3C + processor 1 Receive channel 3 status clear + 2 + 1 + + + CH2C + processor 1 Receive channel 2 status clear + 1 + 1 + + + CH1C + processor 1 Receive channel 1 status clear + 0 + 1 + + + + + C1TO2SR + C1TO2SR + CPU1 to CPU2 status register + 0xC + 0x20 + read-only + 0x00000000 + + + CH6F + processor 1 transmit to process 2 Receive channel 6 status flag + 5 + 1 + + + CH5F + processor 1 transmit to process 2 Receive channel 5 status flag + 4 + 1 + + + CH4F + processor 1 transmit to process 2 Receive channel 4 status flag + 3 + 1 + + + CH3F + processor 1 transmit to process 2 Receive channel 3 status flag + 2 + 1 + + + CH2F + processor 1 transmit to process 2 Receive channel 2 status flag + 1 + 1 + + + CH1F + processor 1 transmit to process 2 Receive channel 1 status flag + 0 + 1 + + + + + C2CR + C2CR + Control register CPU2 + 0x10 + 0x20 + read-write + 0x00000000 + + + TXFIE + processor 2 Transmit channel free interrupt enable + 16 + 1 + + + RXOIE + processor 2 Receive channel occupied interrupt enable + 0 + 1 + + + + + C2MR + C2MR + Mask register CPU2 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + CH6FM + processor 2 Transmit channel 6 free interrupt mask + 21 + 1 + + + CH5FM + processor 2 Transmit channel 5 free interrupt mask + 20 + 1 + + + CH4FM + processor 2 Transmit channel 4 free interrupt mask + 19 + 1 + + + CH3FM + processor 2 Transmit channel 3 free interrupt mask + 18 + 1 + + + CH2FM + processor 2 Transmit channel 2 free interrupt mask + 17 + 1 + + + CH1FM + processor 2 Transmit channel 1 free interrupt mask + 16 + 1 + + + CH6OM + processor 2 Receive channel 6 occupied interrupt enable + 5 + 1 + + + CH5OM + processor 2 Receive channel 5 occupied interrupt enable + 4 + 1 + + + CH4OM + processor 2 Receive channel 4 occupied interrupt enable + 3 + 1 + + + CH3OM + processor 2 Receive channel 3 occupied interrupt enable + 2 + 1 + + + CH2OM + processor 2 Receive channel 2 occupied interrupt enable + 1 + 1 + + + CH1OM + processor 2 Receive channel 1 occupied interrupt enable + 0 + 1 + + + + + C2SCR + C2SCR + Status Set or Clear register CPU2 + 0x18 + 0x20 + write-only + 0x00000000 + + + CH6S + processor 2 Transmit channel 6 status set + 21 + 1 + + + CH5S + processor 2 Transmit channel 5 status set + 20 + 1 + + + CH4S + processor 2 Transmit channel 4 status set + 19 + 1 + + + CH3S + processor 2 Transmit channel 3 status set + 18 + 1 + + + CH2S + processor 2 Transmit channel 2 status set + 17 + 1 + + + CH1S + processor 2 Transmit channel 1 status set + 16 + 1 + + + CH6C + processor 2 Receive channel 6 status clear + 5 + 1 + + + CH5C + processor 2 Receive channel 5 status clear + 4 + 1 + + + CH4C + processor 2 Receive channel 4 status clear + 3 + 1 + + + CH3C + processor 2 Receive channel 3 status clear + 2 + 1 + + + CH2C + processor 2 Receive channel 2 status clear + 1 + 1 + + + CH1C + processor 2 Receive channel 1 status clear + 0 + 1 + + + + + C2TOC1SR + C2TOC1SR + CPU2 to CPU1 status register + 0x1C + 0x20 + read-only + 0x00000000 + + + CH6F + processor 2 transmit to process 1 Receive channel 6 status flag + 5 + 1 + + + CH5F + processor 2 transmit to process 1 Receive channel 5 status flag + 4 + 1 + + + CH4F + processor 2 transmit to process 1 Receive channel 4 status flag + 3 + 1 + + + CH3F + processor 2 transmit to process 1 Receive channel 3 status flag + 2 + 1 + + + CH2F + processor 2 transmit to process 1 Receive channel 2 status flag + 1 + 1 + + + CH1F + processor 2 transmit to process 1 Receive channel 1 status flag + 0 + 1 + + + + + HWCFGR + HWCFGR + IPCC Hardware configuration register + 0x3F0 + 0x20 + read-only + 0x00000006 + + + CHANNELS + Number of channels per CPU supported by the IP, range 1 to 16 + 0 + 8 + + + + + VERR + VERR + IPCC version register + 0x3F4 + 0x20 + read-only + 0x00000010 + + + MAJREV + Major Revision + 4 + 4 + + + MINREV + Minor Revision + 0 + 4 + + + + + IPIDR + IPIDR + IPCC indentification register + 0x3F8 + 0x20 + read-only + 0x00100071 + + + IPID + Identification Code + 0 + 32 + + + + + SIDR + SIDR + IPCC size indentification register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size Identification Code + 0 + 32 + + + + + + + EXTI + External interrupt/event controller + EXTI + 0x58000800 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI[16] (C1IMR2[20]) + 1 + + + EXTI0 + EXTI line 0 interrupt through + EXTI[0] + 6 + + + EXTI1 + EXTI line 0 interrupt through + EXTI[1] + 7 + + + EXTI2 + EXTI line 0 interrupt through + EXTI[2] + 8 + + + EXTI3 + EXTI line 0 interrupt through + EXTI[3] + 9 + + + EXTI4 + EXTI line 0 interrupt through + EXTI[4] + 10 + + + C2SEV + CPU2 SEV through EXTI[40] + 21 + + + EXTI5_9 + EXTI line [9:5] interrupt through + EXTI[9:5] + 23 + + + EXTI10_15 + EXTI line [15:10] interrupt through + EXTI[15:10] + 40 + + + + RTSR1 + RTSR1 + rising trigger selection register + 0x0 + 0x20 + read-write + 0x00000000 + + + RT + Rising trigger event configuration bit of Configurable Event input + 0 + 22 + + + RT_31 + Rising trigger event configuration bit of Configurable Event input + 31 + 1 + + + + + FTSR1 + FTSR1 + falling trigger selection register + 0x4 + 0x20 + read-write + 0x00000000 + + + FT + Falling trigger event configuration bit of Configurable Event input + 0 + 22 + + + FT_31 + Falling trigger event configuration bit of Configurable Event input + 31 + 1 + + + + + SWIER1 + SWIER1 + software interrupt event register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWI + Software interrupt on event + 0 + 22 + + + SWI_31 + Software interrupt on event + 31 + 1 + + + + + PR1 + PR1 + EXTI pending register + 0xC + 0x20 + read-write + 0x00000000 + + + PIF + Configurable event inputs Pending bit + 0 + 22 + + + PIF_31 + Configurable event inputs Pending bit + 31 + 1 + + + + + RTSR2 + RTSR2 + rising trigger selection register + 0x20 + 0x20 + read-write + 0x00000000 + + + RT33 + Rising trigger event configuration bit of Configurable Event input + 1 + 1 + + + RT40_41 + Rising trigger event configuration bit of Configurable Event input + 8 + 2 + + + + + FTSR2 + FTSR2 + falling trigger selection register + 0x24 + 0x20 + read-write + 0x00000000 + + + FT33 + Falling trigger event configuration bit of Configurable Event input + 1 + 1 + + + FT40_41 + Falling trigger event configuration bit of Configurable Event input + 8 + 2 + + + + + SWIER2 + SWIER2 + software interrupt event register + 0x28 + 0x20 + read-write + 0x00000000 + + + SWI33 + Software interrupt on event + 1 + 1 + + + SWI40_41 + Software interrupt on event + 8 + 2 + + + + + PR2 + PR2 + pending register + 0x2C + 0x20 + read-write + 0x00000000 + + + PIF33 + Configurable event inputs x+32 Pending bit. + 1 + 1 + + + PIF40_41 + Configurable event inputs x+32 Pending bit. + 8 + 2 + + + + + C1IMR1 + C1IMR1 + CPUm wakeup with interrupt mask register + 0x80 + 0x20 + read-write + 0x7FC00000 + + + IM + CPU(m) wakeup with interrupt Mask on Event input + 0 + 32 + + + + + C2IMR1 + C2IMR1 + CPUm wakeup with interrupt mask register + 0xC0 + 0x20 + read-write + 0x7FC00000 + + + IM + CPU(m) wakeup with interrupt Mask on Event input + 0 + 32 + + + + + C1EMR1 + C1EMR1 + CPUm wakeup with event mask register + 0x84 + 0x20 + read-write + 0x00000000 + + + EM0_15 + CPU(m) Wakeup with event generation Mask on Event input + 0 + 16 + + + EM17_21 + CPU(m) Wakeup with event generation Mask on Event input + 17 + 5 + + + + + C2EMR1 + C2EMR1 + CPUm wakeup with event mask register + 0xC4 + 0x20 + read-write + 0x00000000 + + + EM0_15 + CPU(m) Wakeup with event generation Mask on Event input + 0 + 16 + + + EM17_21 + CPU(m) Wakeup with event generation Mask on Event input + 17 + 5 + + + + + C1IMR2 + C1IMR2 + CPUm wakeup with interrupt mask register + 0x90 + 0x20 + read-write + 0x0001FCFD + + + IM + CPUm Wakeup with interrupt Mask on Event input + 0 + 17 + + + + + C2IMR2 + C2IMR2 + CPUm wakeup with interrupt mask register + 0xD0 + 0x20 + read-write + 0x0001FCFD + + + IM + CPUm Wakeup with interrupt Mask on Event input + 0 + 17 + + + + + C1EMR2 + C1EMR2 + CPUm wakeup with event mask register + 0x94 + 0x20 + read-write + 0x00000000 + + + EM + CPU(m) Wakeup with event generation Mask on Event input + 8 + 2 + + + + + C2EMR2 + C2EMR2 + CPUm wakeup with event mask register + 0xD4 + 0x20 + read-write + 0x00000000 + + + EM + CPU(m) Wakeup with event generation Mask on Event input + 8 + 2 + + + + + HWCFGR5 + HWCFGR5 + Hardware configuration registers + 0x3E0 + 0x20 + read-only + 0x003EFFFF + + + CPUEVENT + HW configuration CPU event generation + 0 + 32 + + + + + HWCFGR6 + HWCFGR6 + Hardware configuration registers + 0x3DC + 0x20 + read-only + 0x00000300 + + + CPUEVENT + HW configuration CPU event generation + 0 + 32 + + + + + HWCFGR7 + HWCFGR7 + EXTI Hardware configuration registers + 0x3D8 + 0x20 + read-only + 0x00000000 + + + CPUEVENT + HW configuration CPU event generation + 0 + 32 + + + + + HWCFGR2 + HWCFGR2 + Hardware configuration registers + 0x3EC + 0x20 + read-only + 0x803FFFFF + + + EVENT_TRG + HW configuration event trigger type + 0 + 32 + + + + + HWCFGR3 + HWCFGR3 + Hardware configuration registers + 0x3E8 + 0x20 + read-only + 0x00000302 + + + EVENT_TRG + HW configuration event trigger type + 0 + 32 + + + + + HWCFGR4 + HWCFGR4 + Hardware configuration registers + 0x3E4 + 0x20 + read-only + 0x00000000 + + + EVENT_TRG + HW configuration event trigger type + 0 + 32 + + + + + HWCFGR1 + HWCFGR1 + Hardware configuration register 1 + 0x3F0 + 0x20 + read-only + 0x00003130 + + + NBEVENTS + HW configuration number of event + 0 + 8 + + + NBCPUS + HW configuration number of CPUs + 8 + 4 + + + CPUEVTEN + HW configuration of CPU(m) event output enable + 12 + 4 + + + + + VERR + VERR + EXTI IP Version register + 0x3F4 + 0x20 + read-only + 0X00000020 + + + MINREV + Minor Revision number + 0 + 4 + + + MAJREV + Major Revision number + 4 + 4 + + + + + IPIDR + IPIDR + Identification register + 0x3F8 + 0x20 + read-only + 0x000E0001 + + + IPID + IP Identification + 0 + 32 + + + + + SIDR + SIDR + Size ID register + 0x3FC + 0x20 + read-only + 0xA3C5DD01 + + + SID + Size Identification + 0 + 32 + + + + + + + CRS + Clock recovery system + CRS + 0x40006000 + + 0x0 + 0x400 + registers + + + CRS_IT + CRS interrupt + 42 + + + + CR + CR + CRS control register + 0x0 + 0x20 + read-write + 0x00002000 + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + + + CEN + Frequency error counter enable + 5 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + SWSYNC + Automatic trimming enable + 7 + 1 + + + TRIM + HSI48 oscillator smooth trimming + 8 + 6 + + + + + CFGR + CFGR + CRS configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value + 0 + 16 + + + FELIM + Frequency error limit + 16 + 8 + + + SYNCDIV + SYNCDIV + 24 + 3 + + + SYNCSRC + SYNC signal source selection + 28 + 2 + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + ERRF + Error flag + 2 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow + 10 + 1 + + + FEDIR + Frequency error direction + 15 + 1 + + + FECAP + Frequency error capture + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + SYNCWARNC + warning clear flag + 1 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + + + + + USB + Universal serial bus full-speed device interface + USB + 0x40006800 + + 0x0 + 0x800 + registers + + + USB_HP + USB high priority interrupt + 19 + + + USB_LP + USB low priority interrupt (including USB + wakeup) + 20 + + + + EP0R + EP0R + endpoint 0 register + 0x0 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP1R + EP1R + endpoint 1 register + 0x4 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP2R + EP2R + endpoint 2 register + 0x8 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP3R + EP3R + endpoint 3 register + 0xC + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP4R + EP4R + endpoint 4 register + 0x10 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP5R + EP5R + endpoint 5 register + 0x14 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP6R + EP6R + endpoint 6 register + 0x18 + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + EP7R + EP7R + endpoint 7 register + 0x1C + 0x10 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission transfers + 6 + 1 + + + CTR_TX + Correct Transfer for transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction completed + 11 + 1 + + + STAT_RX + Status bits, for reception transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception transfers + 14 + 1 + + + CTR_RX + Correct transfer for reception + 15 + 1 + + + + + CNTR + CNTR + control register + 0x40 + 0x10 + read-write + 0x00000003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + L1RESUME + LPM L1 Resume request + 5 + 1 + + + L1REQM + LPM L1 state request interrupt mask + 7 + 1 + + + ESOFM + Expected start of frame interrupt mask + 8 + 1 + + + SOFM + Start of frame interrupt mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x10 + 0x00000000 + + + EP_ID + Endpoint Identifier + 0 + 4 + read-only + + + DIR + Direction of transaction + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + 7 + 1 + read-write + + + ESOF + Expected start frame + 8 + 1 + read-write + + + SOF + start of frame + 9 + 1 + read-write + + + RESET + reset request + 10 + 1 + read-write + + + SUSP + Suspend mode request + 11 + 1 + read-write + + + WKUP + Wakeup + 12 + 1 + read-write + + + ERR + Error + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / underrun + 14 + 1 + read-write + + + CTR + Correct transfer + 15 + 1 + read-only + + + + + FNR + FNR + frame number register + 0x48 + 0x10 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x10 + read-write + 0x0000 + + + ADD + Device address + 0 + 7 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x10 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + COUNT0_TX + COUNT0_TX + Transmission byte count 0 + 0x52 + 0x10 + read-write + 0x0000 + + + COUNT0_TX + Transmission byte count + 0 + 10 + + + + + COUNT1_TX + COUNT1_TX + Transmission byte count 0 + 0x5A + 0x10 + read-write + 0x0000 + + + COUNT1_TX + Transmission byte count + 0 + 10 + + + + + COUNT2_TX + COUNT2_TX + Transmission byte count 0 + 0x62 + 0x10 + read-write + 0x0000 + + + COUNT2_TX + Transmission byte count + 0 + 10 + + + + + COUNT3_TX + COUNT3_TX + Transmission byte count 0 + 0x6A + 0x10 + read-write + 0x0000 + + + COUNT3_TX + Transmission byte count + 0 + 10 + + + + + COUNT4_TX + COUNT4_TX + Transmission byte count 0 + 0x72 + 0x10 + read-write + 0x0000 + + + COUNT4_TX + Transmission byte count + 0 + 10 + + + + + COUNT5_TX + COUNT5_TX + Transmission byte count 0 + 0x7A + 0x10 + read-write + 0x0000 + + + COUNT5_TX + Transmission byte count + 0 + 10 + + + + + COUNT6_TX + COUNT6_TX + Transmission byte count 0 + 0x82 + 0x10 + read-write + 0x0000 + + + COUNT6_TX + Transmission byte count + 0 + 10 + + + + + COUNT7_TX + COUNT7_TX + Transmission byte count 0 + 0x8A + 0x10 + read-write + 0x0000 + + + COUNT7_TX + Transmission byte count + 0 + 10 + + + + + ADDR0_RX + ADDR0_RX + Reception buffer address 0 + 0x54 + 0x10 + read-write + 0x0000 + + + ADDR0_RX + Reception buffer address + 1 + 15 + + + + + ADDR1_RX + ADDR1_RX + Reception buffer address 0 + 0x5C + 0x10 + read-write + 0x0000 + + + ADDR1_RX + Reception buffer address + 1 + 15 + + + + + ADDR2_RX + ADDR2_RX + Reception buffer address 0 + 0x64 + 0x10 + read-write + 0x0000 + + + ADDR2_RX + Reception buffer address + 1 + 15 + + + + + ADDR3_RX + ADDR3_RX + Reception buffer address 0 + 0x6C + 0x10 + read-write + 0x0000 + + + ADDR3_RX + Reception buffer address + 1 + 15 + + + + + ADDR4_RX + ADDR4_RX + Reception buffer address 0 + 0x74 + 0x10 + read-write + 0x0000 + + + ADDR4_RX + Reception buffer address + 1 + 15 + + + + + ADDR5_RX + ADDR5_RX + Reception buffer address 0 + 0x7C + 0x10 + read-write + 0x0000 + + + ADDR5_RX + Reception buffer address + 1 + 15 + + + + + ADDR6_RX + ADDR6_RX + Reception buffer address 0 + 0x84 + 0x10 + read-write + 0x0000 + + + ADDR6_RX + Reception buffer address + 1 + 15 + + + + + ADDR7_RX + ADDR7_RX + Reception buffer address 0 + 0x8C + 0x10 + read-write + 0x0000 + + + ADDR7_RX + Reception buffer address + 1 + 15 + + + + + COUNT0_RX + COUNT0_RX + Reception byte count 0 + 0x56 + 0x10 + 0x0000 + + + COUNT0_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT1_RX + COUNT1_RX + Reception byte count 0 + 0x5E + 0x10 + 0x0000 + + + COUNT1_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT2_RX + COUNT2_RX + Reception byte count 0 + 0x66 + 0x10 + 0x0000 + + + COUNT2_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT3_RX + COUNT3_RX + Reception byte count 0 + 0x6E + 0x10 + 0x0000 + + + COUNT3_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT4_RX + COUNT4_RX + Reception byte count 0 + 0x76 + 0x10 + 0x0000 + + + COUNT4_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT5_RX + COUNT5_RX + Reception byte count 0 + 0x7E + 0x10 + 0x0000 + + + COUNT5_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT6_RX + COUNT6_RX + Reception byte count 0 + 0x86 + 0x10 + 0x0000 + + + COUNT6_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + COUNT7_RX + COUNT7_RX + Reception byte count 0 + 0x8E + 0x10 + 0x0000 + + + COUNT7_RX + Reception byte count + 0 + 10 + read-only + + + NUM_BLOCK + Number of blocks + 10 + 5 + read-write + + + BL_SIZE + Block size + 15 + 1 + read-write + + + + + LPMCSR + LPMCSR + control and status register + ADDR0_RX + 0x54 + 0x10 + 0x0000 + + + LPMEN + LPM support enable + 0 + 1 + read-write + + + LPMACK + LPM Token acknowledge enable + 1 + 1 + read-write + + + REMWAKE + RemoteWake value + 3 + 1 + read-write + + + BESL + BESL value + 4 + 4 + read-only + + + + + BCDR + BCDR + Battery charging detector( + 0x58 + 0x10 + 0x0000 + + + BCDEN + Battery charging detector (BCD) enable + 0 + 1 + read-write + + + DCDEN + Data contact detection (DCD) mode enable + 1 + 1 + read-write + + + PDEN + Primary detection (PD) mode enable + 2 + 1 + read-write + + + SDEN + Secondary detection (SD) mode enable + 3 + 1 + read-write + + + DCDET + Data contact detection (DCD) status + 4 + 1 + read-only + + + PDET + Primary detection (PD) status + 5 + 1 + read-only + + + SDET + Secondary detection (SD) status + 6 + 1 + read-only + + + PS2DET + DM pull-up detection status + 7 + 1 + read-only + + + DPPU + DP pull-up control + 15 + 1 + read-write + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler 4 + 0 + 8 + + + PRI_5 + Priority of system handler 5 + 8 + 8 + + + PRI_6 + Priority of system handler 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler 14 + 16 + 8 + + + PRI_15 + Priority of system handler 15 + 24 + 8 + + + + + SHCRS + SHCRS + System handler control and state register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active bit + 10 + 1 + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage fault + 18 + 1 + + + NOCP + No coprocessor usage fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable bit + 28 + 1 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 54 + + + + FPCCR + FPCCR + Floating-point context control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception bit + 0 + 1 + + + DZC + Division by zero cumulative exception bit. + 1 + 1 + + + OFC + Overflow cumulative exception bit + 2 + 1 + + + UFC + Underflow cumulative exception bit + 3 + 1 + + + IXC + Inexact cumulative exception bit + 4 + 1 + + + IDC + Input denormal cumulative exception bit. + 7 + 1 + + + RMode + Rounding Mode control field + 22 + 2 + + + FZ + Flush-to-zero mode control bit: + 24 + 1 + + + DN + Default NaN mode control bit + 25 + 1 + + + AHP + Alternative half-precision control bit + 26 + 1 + + + V + Overflow condition code flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code flag + 31 + 1 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0x0 + 0x351 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + NVIC_STIR + Nested vectored interrupt controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt ID + 0 + 9 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + +