Cora port issues

[iohe]

Got a Cora z7-10 from digilent, i am working to add support, in order to learn more on riscv, fpga topics.
It has XC7Z010-1CLG400, 512MB RAM, 50 Mhz PS Clock, that translates to similar settings to ZedBoard but with lower fpga resources and following changes:
RISCV_CORE_CONFIG = ZynqSmallFPGAConfig.
I keep RISCV_CORE_ARCH = RV64IMAFD.

Command ./fesvr pk hello does not output anything.
Also noticed defaults in fpga/system_bd.tcl for clocking are for RV64IMA, instead of RV64IMAFD, for ZedBoard. Is this expected? (even if i change to RV64IMAFD, i still do not see output on hello command).

What would be next steps ?