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Hello!
I used "OpenRISC SoC Practical Session Instructions" to get my very first OpenRISC experience.
All steps were OK, but this one fails: fusesoc sim mor1kx-generic --elf-load hello.elf
I got some warnings like: WARNING: ::elf-loader:0 : plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters
And finally I ran into errors: iverilog -sorpsoc_tb -c mor1kx-generic_0.scr -o mor1kx-generic_0 -DSIM
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_cpu_cappuccino.v:1132: sorry: constant user functions are not currently supported: calc_rf_addr_width().
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:87: sorry: constant user functions are not currently supported: calc_rf_addr_width().
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:313: error: identifier RF_ADDR_WIDTH is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:331: error: identifier RF_ADDR_WIDTH is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:352: error: identifier RF_ADDR_WIDTH is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.rfspr_gen.
5 error(s) during elaboration.
Makefile:9: recipe for target 'mor1kx-generic_0' failed
make: *** [mor1kx-generic_0] Error 5
I use Ubuntu 16 x64. I did not install Altera Quartus as I plan to use simulation and then go to Xilinx ISE or Vivado.
Please help me to understand the reason.
Many thanks for any help!
With regards,
Maksim
The text was updated successfully, but these errors were encountered:
KotNitro
changed the title
Unable to run OpenRISC simultion
Unable to run OpenRISC simulation
Feb 4, 2018
@KotNitro@ecg173gh Sorry you are having these problems. ChipHack has moved on from using OpenRISC, to PicoRV32, at the same time adopting the Yosys tool flow. Part of this was that the course used to waste so much time on getting the Quartus tools running.
You might find it useful to reach out to @olofk who maintains Fusesoc, and may be able to advise.
Hello!
I used "OpenRISC SoC Practical Session Instructions" to get my very first OpenRISC experience.
All steps were OK, but this one fails:
fusesoc sim mor1kx-generic --elf-load hello.elf
I got some warnings like:
WARNING: ::elf-loader:0 : plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters
And finally I ran into errors:
iverilog -sorpsoc_tb -c mor1kx-generic_0.scr -o mor1kx-generic_0 -DSIM
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_cpu_cappuccino.v:1132: sorry: constant user functions are not currently supported: calc_rf_addr_width().
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:87: sorry: constant user functions are not currently supported: calc_rf_addr_width().
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:313: error: identifier
RF_ADDR_WIDTH
is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:331: error: identifier
RF_ADDR_WIDTH
is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:352: error: identifier
RF_ADDR_WIDTH
is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.rfspr_gen.5 error(s) during elaboration.
Makefile:9: recipe for target 'mor1kx-generic_0' failed
make: *** [mor1kx-generic_0] Error 5
I use Ubuntu 16 x64. I did not install Altera Quartus as I plan to use simulation and then go to Xilinx ISE or Vivado.
Please help me to understand the reason.
Many thanks for any help!
With regards,
Maksim
The text was updated successfully, but these errors were encountered: