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RISE RP005 QEMU weekly report 2024-10-02

Work completed since last report

SiFive function performance report.

  • WP2

    • Complete SiFive library function set
      • added strcat.
      • work in progress on the remaining 8 functions.
    • Single instruction benchmarking relevant to SiFive library functions
      • on hold.
    • Resume work on AArch64 comparison.
      • working on the single instruction comparison between a Aarch64 vector load and vle8.v.
      • on hold to prioritize the separation of the patches.
  • Other

    • Separate Embecosm's and Max's patches:
      • work in progress. This is a substantial effort because all the changes since July have been assumed to build on Max's work, and hence we need to write code to allow the patch to work standalone.
    • Updated small load/store loop optimization upstream with user mode condition.

Work planned for the coming week

  • WP2

    • Complete SiFive library function set.
    • Single instruction benchmarking relevant to SiFive library functions.
    • Continue to work on AArch64 comparison.
  • Other:

    • Max: share patches applied to our benchmarking scripts.
    • Max: run SPECCPU 2017 results again with VLEN=128 and LMUL=1.

Changes since start of project

It is useful to keep an idea of what we have achieved since 1 May 2024. We use ns/instruction as our metric.

Metric Start Now Speedup Notes
memcpy worst case 2%
memcpy best case 6,869%
SPEC CPU 2017 average 13.3 11.3 15%
SPEC CPU 2017 best case 12.0 7.4 38% 628.pop2_s

Percentage changes relative to "now". SPEC CPU 2017 results are from August, since we have stopped measuring this.

Planned absences

  • Jeremy Bennett will be on vacation 12-19 October
  • Jeremy Bennett will be at the RISC-V NA Summit 21-24 October
  • Paolo Savini will be at the LLVM Developers' Meeting 22-24 October