From fde9d2e4ad3c1a522554935bc12d8c7dd4988a2c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Sep 2024 10:12:33 +0200 Subject: [PATCH 1/3] build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks. Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround. --- litex/build/efinix/efinity.py | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/litex/build/efinix/efinity.py b/litex/build/efinix/efinity.py index 01ebb6ac21..c0643478e1 100644 --- a/litex/build/efinix/efinity.py +++ b/litex/build/efinix/efinity.py @@ -222,9 +222,33 @@ def _build_iface_gpio(self): return "\n".join(conf) + def resolve_iface_signal_names(self): + # Iterate over each block + for block in self.platform.toolchain.ifacewriter.blocks: + + # Iterate over each key-value pair in the block + for key, value in block.items(): + + # Only process specific keys, skip others. + if key not in ["name", "in_clk_pin", "out_clk_pin"]: + continue + + # If the value is a ClockSignal, resolve its name + if isinstance(value, ClockSignal): + clock_domain = value.cd + signal_name = self._vns.get_name(self._vns.clock_domains[clock_domain].clk) + block[key] = signal_name # Replace with the resolved name + + # If the value is a Signal, directly resolve its name + elif isinstance(value, Signal): + signal_name = self._vns.get_name(value) + block[key] = signal_name # Replace with the resolved name + def build_io_constraints(self): pythonpath = "" + self.resolve_iface_signal_names() + header = self.ifacewriter.header(self._build_name, self.platform.device) gen = self.ifacewriter.generate(self.platform.device) #TODO : move this to ifacewriter From a3a55fc8fb30aef1f50d4dc13dec191ff185b3e6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Sep 2024 10:14:42 +0200 Subject: [PATCH 2/3] build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names. --- litex/build/efinix/common.py | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py index 5b8030e022..b5c0b59af3 100644 --- a/litex/build/efinix/common.py +++ b/litex/build/efinix/common.py @@ -33,6 +33,16 @@ r"\g<0>" + colorama.Style.RESET_ALL), ] +# Helpers ------------------------------------------------------------------------------------------ + +def _to_signal(obj): + if isinstance(obj, str): + return ClockSignal(obj) + elif isinstance(obj, Signal): + return obj + else: + raise ValueError + # Efinix AsyncResetSynchronizer -------------------------------------------------------------------- class EfinixAsyncResetSynchronizerImpl(Module): @@ -109,7 +119,7 @@ def __init__(self, platform, i, o): "size" : 1, "location" : platform.get_pin_location(o)[0], "properties" : platform.get_pin_properties(o), - "name" : i.name_override, # FIXME + "name" : _to_signal(i), "mode" : "OUTPUT_CLK", } platform.toolchain.ifacewriter.blocks.append(block) @@ -290,9 +300,9 @@ def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk): "properties" : io_prop, "size" : 1, "in_reg" : "DDIO_RESYNC", - "in_clk_pin" : clk.name_override, # FIXME. + "in_clk_pin" : _to_signal(clk), "out_reg" : "DDIO_RESYNC", - "out_clk_pin" : clk.name_override, # FIXME. + "out_clk_pin" : _to_signal(clk), "oe_reg" : "REG", "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") @@ -327,9 +337,9 @@ def __init__(self, platform, io, o, oe, i, clk): "properties" : io_prop, "size" : 1, "in_reg" : "REG", - "in_clk_pin" : clk.name_override, # FIXME. + "in_clk_pin" : _to_signal(clk), "out_reg" : "REG", - "out_clk_pin" : clk.name_override, # FIXME. + "out_clk_pin" : _to_signal(clk), "oe_reg" : "REG", "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") @@ -361,7 +371,7 @@ def __init__(self, platform, i, o, clk): "properties" : io_prop, "size" : 1, "out_reg" : "REG", - "out_clk_pin" : clk.name_override, # FIXME. + "out_clk_pin" : _to_signal(clk), "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } @@ -395,7 +405,7 @@ def __init__(self, platform, i1, i2, o, clk): "properties" : io_prop, "size" : 1, "out_reg" : "DDIO_RESYNC", - "out_clk_pin" : clk.name_override, # FIXME. + "out_clk_pin" : _to_signal(clk), "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } @@ -426,7 +436,7 @@ def __init__(self, platform, i, o1, o2, clk): "properties" : io_prop, "size" : 1, "in_reg" : "DDIO_RESYNC", - "in_clk_pin" : clk.name_override, # FIXME. + "in_clk_pin" : _to_signal(clk), "is_inclk_inverted" : False } platform.toolchain.ifacewriter.blocks.append(block) From 39d292a3c7b56bb5caa5e3c80017d60fd0ce25d7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Sep 2024 10:37:54 +0200 Subject: [PATCH 3/3] build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names. --- litex/build/efinix/common.py | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py index b5c0b59af3..c6e997a772 100644 --- a/litex/build/efinix/common.py +++ b/litex/build/efinix/common.py @@ -35,13 +35,8 @@ # Helpers ------------------------------------------------------------------------------------------ -def _to_signal(obj): - if isinstance(obj, str): - return ClockSignal(obj) - elif isinstance(obj, Signal): - return obj - else: - raise ValueError +def assert_is_signal_or_clocksignal(obj): + assert isinstance(obj, (ClockSignal, Signal)), f"Object {obj} is not a ClockSignal or Signal" # Efinix AsyncResetSynchronizer -------------------------------------------------------------------- @@ -114,12 +109,13 @@ def lower(dr): class EfinixClkOutputImpl(Module): def __init__(self, platform, i, o): + assert_is_signal_or_clocksignal(i) block = { "type" : "GPIO", "size" : 1, "location" : platform.get_pin_location(o)[0], "properties" : platform.get_pin_properties(o), - "name" : _to_signal(i), + "name" : i, "mode" : "OUTPUT_CLK", } platform.toolchain.ifacewriter.blocks.append(block) @@ -278,6 +274,7 @@ def lower(dr): class EfinixDDRTristateImpl(Module): def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk): assert oe1 == oe2 + assert_is_signal_or_clocksignal(clk) io_name = platform.get_pin_name(io) io_pad = platform.get_pin_location(io) io_prop = platform.get_pin_properties(io) @@ -300,9 +297,9 @@ def __init__(self, platform, io, o1, o2, oe1, oe2, i1, i2, clk): "properties" : io_prop, "size" : 1, "in_reg" : "DDIO_RESYNC", - "in_clk_pin" : _to_signal(clk), + "in_clk_pin" : clk, "out_reg" : "DDIO_RESYNC", - "out_clk_pin" : _to_signal(clk), + "out_clk_pin" : clk, "oe_reg" : "REG", "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") @@ -319,6 +316,7 @@ def lower(dr): class EfinixSDRTristateImpl(EfinixDDRTristateImpl): def __init__(self, platform, io, o, oe, i, clk): + assert_is_signal_or_clocksignal(clk) io_name = platform.get_pin_name(io) io_pad = platform.get_pin_location(io) io_prop = platform.get_pin_properties(io) @@ -337,9 +335,9 @@ def __init__(self, platform, io, o, oe, i, clk): "properties" : io_prop, "size" : 1, "in_reg" : "REG", - "in_clk_pin" : _to_signal(clk), + "in_clk_pin" : clk, "out_reg" : "REG", - "out_clk_pin" : _to_signal(clk), + "out_clk_pin" : clk, "oe_reg" : "REG", "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") @@ -357,6 +355,7 @@ def lower(dr): class EfinixSDROutputImpl(Module): def __init__(self, platform, i, o, clk): + assert_is_signal_or_clocksignal(clk) io_name = platform.get_pin_name(o) io_pad = platform.get_pin_location(o) io_prop = platform.get_pin_properties(o) @@ -371,7 +370,7 @@ def __init__(self, platform, i, o, clk): "properties" : io_prop, "size" : 1, "out_reg" : "REG", - "out_clk_pin" : _to_signal(clk), + "out_clk_pin" : clk, "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } @@ -389,6 +388,7 @@ def lower(dr): class EfinixDDROutputImpl(Module): def __init__(self, platform, i1, i2, o, clk): + assert_is_signal_or_clocksignal(clk) io_name = platform.get_pin_name(o) io_pad = platform.get_pin_location(o) io_prop = platform.get_pin_properties(o) @@ -405,7 +405,7 @@ def __init__(self, platform, i1, i2, o, clk): "properties" : io_prop, "size" : 1, "out_reg" : "DDIO_RESYNC", - "out_clk_pin" : _to_signal(clk), + "out_clk_pin" : clk, "is_inclk_inverted" : False, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } @@ -421,6 +421,7 @@ def lower(dr): class EfinixDDRInputImpl(Module): def __init__(self, platform, i, o1, o2, clk): + assert_is_signal_or_clocksignal(clk) io_name = platform.get_pin_name(i) io_pad = platform.get_pin_location(i) io_prop = platform.get_pin_properties(i) @@ -436,7 +437,7 @@ def __init__(self, platform, i, o1, o2, clk): "properties" : io_prop, "size" : 1, "in_reg" : "DDIO_RESYNC", - "in_clk_pin" : _to_signal(clk), + "in_clk_pin" : clk, "is_inclk_inverted" : False } platform.toolchain.ifacewriter.blocks.append(block)