From b86d76baed3eafbfbcfb4da2353ba6d1052d3c6b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Sep 2024 08:53:57 +0200 Subject: [PATCH] build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations. --- CHANGES.md | 1 + litex/build/sim/core/veril.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/CHANGES.md b/CHANGES.md index e15f1288d6..e59eaf166b 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -11,6 +11,7 @@ - soc/cores/clock/colognechip : Fixed and reworked locked signal handling. - litesdcard : Fixed data_i sampling (https://github.com/enjoy-digital/litesdcard/pull/34). - litespi/mmap : Fixed dummy bits (https://github.com/litex-hub/litespi/pull/71). + - sim/verilator : Fixed .fst empty dump with short simulation. [> Added -------- diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp index 2ea9a34823..1e79b6d9d3 100644 --- a/litex/build/sim/core/veril.cpp +++ b/litex/build/sim/core/veril.cpp @@ -78,6 +78,7 @@ extern "C" void litex_sim_tracer_dump() extern "C" int litex_sim_got_finish() { + tfp->flush(); return Verilated::gotFinish(); }