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barvinn.core
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barvinn.core
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CAPI=2:
name : ::barvinn:0
description: A Barrel RISC-V Neural Network Accelerator
filesets:
rtl:
file_type: systemVerilogSource
files:
- deps/common_cells/src/cf_math_pkg.sv
- deps/apb/include/apb/assign.svh: {is_include_file: True}
- deps/apb/include/apb/typedef.svh: {is_include_file: True}
- deps/apb/src/apb_test.sv
- deps/apb/src/apb_pkg.sv
- deps/apb/src/apb_intf.sv
- deps/tech_cells_generic/src/rtl/tc_sram.sv
- deps/common_cells/src/onehot_to_bin.sv
- deps/pito_riscv/verification/lib/rv32/rv32_defines.svh: {is_include_file: true}
- deps/pito_riscv/verification/lib/rv32/rv32_pkg.sv
- deps/pito_riscv/verification/lib/pito/pito_pkg.sv
- deps/pito_riscv/verification/lib/pito/pito_intf.sv
- deps/pito_riscv/vsrc/rv32_imm_gen.sv
- deps/pito_riscv/vsrc/rv32_decoder.sv
- deps/pito_riscv/vsrc/rv32_data_memory.sv
- deps/pito_riscv/vsrc/rv32_instruction_memory.sv
- deps/pito_riscv/vsrc/rv32_alu.sv
- deps/pito_riscv/vsrc/rv32_regfile.sv
- deps/pito_riscv/vsrc/rv32_barrel_regfiles.sv
- deps/pito_riscv/vsrc/rv32_core.sv
- deps/pito_riscv/vsrc/rv32_next_pc.sv
- deps/pito_riscv/vsrc/rv32_csr.sv
- deps/pito_riscv/vsrc/rv32_barrel_csrfiles.sv
- deps/pito_riscv/vsrc/pito_uart.sv
- deps/pito_riscv/vsrc/pito_soc.sv
- deps/MVU/verification/lib/mvu/mvu_pkg.sv
- deps/MVU/verification/lib/mvu/mvu_intf.sv
- deps/MVU/verilog/bram64k.v: {file_type : verilogSource}
- deps/MVU/verilog/bank64k.v: {file_type : verilogSource}
- deps/MVU/verilog/bram2m.v: {file_type : verilogSource}
- deps/MVU/verilog/cdru.v: {file_type : verilogSource}
- deps/MVU/verilog/cdwu.v: {file_type : verilogSource}
- deps/MVU/verilog/maxpool.v: {file_type : verilogSource}
- deps/MVU/verilog/mvp.v: {file_type : verilogSource}
- deps/MVU/verilog/mvu.v: {file_type : verilogSource}
- deps/MVU/verilog/shacc.v: {file_type : verilogSource}
- deps/MVU/verilog/vvp.v: {file_type : verilogSource}
- deps/MVU/verilog/interconn.v: {file_type : verilogSource}
- deps/MVU/verilog/quantser.v: {file_type : verilogSource}
- deps/MVU/verilog/quantser_ctrl.v: {file_type : verilogSource}
- deps/MVU/verilog/outagu.v: {file_type : verilogSource}
- deps/MVU/verilog/zigzagu.v: {file_type : verilogSource}
- deps/MVU/verilog/controller.v: {file_type : verilogSource}
- deps/MVU/verilog/shiftreg.v: {file_type : verilogSource}
- deps/MVU/verilog/fixedpointscaler.v: {file_type : verilogSource}
- deps/MVU/verilog/ram_simple2port.v: {file_type : verilogSource}
- deps/MVU/verilog/inagu.sv
- deps/MVU/verilog/agu.sv
- deps/MVU/verilog/mvutop.sv
- deps/MVU/verilog/mvutop_wrapper.sv
- vsrc/data_transposer.sv
- vsrc/barvinn.sv
synth_xilinx:
file_type: xci
files:
- deps/MVU/ip/build/xilinx/bram2m_xilinx/bram2m_xilinx.xci
- deps/MVU/ip/build/xilinx/bram64k_64x1024_xilinx/bram64k_64x1024_xilinx.xci
- deps/MVU/mvu.xdc:
file_type: xdc
tb:
file_type: systemVerilogSource
files:
- deps/pito_riscv/verification/lib/rv32/rv32_defines.svh:
is_include_file: true
- deps/pito_riscv/verification/lib/rv32/rv32_pkg.sv
- deps/pito_riscv/verification/lib/pito/pito_pkg.sv
- deps/pito_riscv/verification/lib/utils/utils.sv
- deps/pito_riscv/verification/lib/rv32/rv32_utils.sv
- deps/pito_riscv/verification/lib/pito/pito_intf.sv
- deps/pito_riscv/verification/lib/pito/pito_monitor.sv:
is_include_file: true
- deps/pito_riscv/verification/lib/testbench/testbench_config.sv
- deps/MVU/verification/lib/testbench/testbench_pkg.sv
- deps/MVU/verification/lib/mvu/mvu_pkg.sv
- deps/MVU/verification/lib/mvu/mvu_intf.sv
- deps/MVU/verification/lib/testbench/testbench_config.sv
- verification/lib/barvinn/barvinn_intf.sv:
is_include_file: true
- verification/lib/testbench/testbench_base.sv
- verification/lib/testbench/testbench_config.sv
- verification/lib/testbench/testbench_macros.svh:
is_include_file: true
- verification/tests/conv/conv_tester.sv:
is_include_file: true
- verification/lib/testbench/testbench_top.sv
targets:
sim:
default_tool: xsim
filesets:
- rtl
- tb
description: Simulate the design
tools:
xsim:
xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, -L, blk_mem_gen_v8_4_3, --timescale, 1ns/1ps, --define, SIMULATION_MODE]
parameters: [XILINX, firmware, rodata]
toplevel: testbench_top
synth:
description: Synthesize the design for an FPGA board
filesets:
- rtl
- synth_xilinx
default_tool: vivado
tools:
vivado:
part: xcvu9p-flgb2104-2-e
pnr: none
flatten_hierarchy: none
parameters: [XILINX]
toplevel: [barvinn]
parameters:
XILINX:
datatype : int
default : 1
paramtype : vlogdefine
firmware:
datatype : file
default : /users/hemmat/MyRepos/BARVINN/csrc/conv/build/conv_text.hex
paramtype : plusarg
rodata:
datatype : file
default : /users/hemmat/MyRepos/BARVINN/csrc/conv/build/conv_data.hex
paramtype : plusarg