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cpu.cc
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cpu.cc
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/* MIPS R3000 CPU emulation modified to simulate traditional 5-stage pipeline, memory access stall (due to e.g., cache miss)
Original work Copyright 2001, 2002, 2003, 2004 Brian R. Gaeke.
Modified work Copyright (c) 2021 Amano laboratory, Keio University.
Modifier: Takuya Kojima
This file is part of CubeSim, a cycle accurate simulator for 3-D stacked system.
It is derived from a source code of VMIPS project under GPLv2.
CubeSim is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
CubeSim is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with CubeSim. If not, see <https://www.gnu.org/licenses/>.
*/
#include <string.h>
#include "cpu.h"
#include "cpzero.h"
#include "debug.h"
#include "fpu.h"
#include "mapper.h"
#include "vmips.h"
#include "options.h"
#include "excnames.h"
#include "cpzeroreg.h"
#include "error.h"
#include "remotegdb.h"
#include "fileutils.h"
#include "stub-dis.h"
#include <cstring>
#include "state.h"
#include "cache.h"
#include "ISA.h"
/* states of the delay-slot state machine -- see CPU::step() */
static const int NORMAL = 0, DELAYING = 1, DELAYSLOT = 2;
/* certain fixed register numbers which are handy to know */
static const int reg_zero = 0; /* always zero */
static const int reg_sp = 29; /* stack pointer */
static const int reg_ra = 31; /* return address */
/* pointer to CPU method returning void and taking two uint32's */
typedef void (CPU::*emulate_funptr)(uint32, uint32);
static const char *strdelaystate(const int state) {
static const char *const statestr[] = {
"NORMAL", "DELAYING", "DELAYSLOT"
};
return statestr[state];
}
PipelineRegs::PipelineRegs(uint32 pc_, uint32 instr_):
pc(pc_), instr(instr_)
{
alu_src_a = &(this->shamt);
alu_src_b = &(this->shamt);
w_reg_data = w_mem_data = lwrl_reg_prev = NULL;
mem_read_op = delay_slot = false;
src_a = src_b = dst = NONE_REG;
result = r_mem_data = imm = shamt = 0;
}
PipelineRegs::~PipelineRegs()
{
excBuf.clear();
}
CPU::CPU (Mapper &m, IntCtrl &i, int cpuid)
: tracing (false), last_epc (0), last_prio (0), mem (&m),
cpzero (new CPZero (this, &i, cpuid)), fpu (0), delay_state (NORMAL),
mul_div_remain(0), suspend(false), icache(NULL), dcache(NULL)
{
opt_fpu = machine->opt->option("fpu")->flag;
if (opt_fpu)
fpu = new FPU (this);
reg[reg_zero] = 0;
opt_excmsg = machine->opt->option("excmsg")->flag;
opt_reportirq = machine->opt->option("reportirq")->flag;
opt_excpriomsg = machine->opt->option("excpriomsg")->flag;
opt_haltbreak = machine->opt->option("haltbreak")->flag,
opt_haltibe = machine->opt->option("haltibe")->flag;
opt_instdump = machine->opt->option("instdump")->flag;
opt_tracing = machine->opt->option("tracing")->flag;
opt_tracesize = machine->opt->option("tracesize")->num;
opt_tracestartpc = machine->opt->option("tracestartpc")->num;
opt_traceendpc = machine->opt->option("traceendpc")->num;
opt_bigendian = machine->opt->option("bigendian")->flag;
if (opt_tracing)
open_trace_file ();
/* Caches are 2way-set associative, physically indexed, physically tagged,
* with 1-word lines. */
opt_icacheway = machine->opt->option("icacheway")->num;
opt_dcacheway = machine->opt->option("dcacheway")->num;
opt_icachebnum = machine->opt->option("icachebnum")->num;
opt_dcachebnum = machine->opt->option("dcachebnum")->num;
opt_icachebsize = machine->opt->option("icachebsize")->num;
opt_dcachebsize = machine->opt->option("dcachebsize")->num;
mem_bandwidth = machine->opt->option("mem_bandwidth")->num;
exception_pending = false;
volatilize_pipeline();
}
CPU::~CPU ()
{
if (opt_tracing)
close_trace_file ();
if (icache) delete icache;
if (dcache) delete dcache;
for (int i = 0; i < PIPELINE_STAGES; i++) {
if (PL_REGS[i]) delete PL_REGS[i];
}
}
void
CPU::reset(void)
{
#ifdef INTENTIONAL_CONFUSION
int r;
for (r = 0; r < 32; r++) {
reg[r] = random();
}
#endif /* INTENTIONAL_CONFUSION */
reg[reg_zero] = 0;
pc = 0xbfc00000 - 4; //+4 later
cpzero->reset();
//generate cache
icache = new Cache(mem, opt_icachebnum, opt_icachebsize, opt_icacheway); /* 64Byte * 64Block * 2way = 8KB*/
dcache = new Cache(mem, opt_dcachebnum, opt_dcachebsize, opt_dcacheway);
//fill NOP for each Pipeline stage
volatilize_pipeline();
}
void CPU::volatilize_pipeline()
{
for (int i = 0; i < PIPELINE_STAGES; i++) {
PL_REGS[i] = new PipelineRegs(pc + 4, NOP_INSTR);
}
late_preg = new PipelineRegs(pc + 4, NOP_INSTR);
late_late_preg = new PipelineRegs(pc + 4, NOP_INSTR);
}
void
CPU::dump_regs(FILE *f)
{
int i;
fprintf(f,"Reg Dump: [ PC=%08x LastInstr=%08x HI=%08x LO=%08x\n",
PL_REGS[WB_STAGE]->pc,PL_REGS[WB_STAGE]->instr,hi,lo);
// fprintf(f," DelayState=%s DelayPC=%08x NextEPC=%08x\n",
// strdelaystate(delay_state), delay_pc, next_epc);
for (i = 0; i < 32; i++) {
fprintf(f," R%02d=%08x ",i,reg[i]);
if (i % 5 == 4) {
fputc('\n',f);
} else if (i == 31) {
fprintf(f, " ]\n");
}
}
}
void
CPU::dump_stack(FILE *f)
{
uint32 stackphys;
if (cpzero->debug_tlb_translate(reg[reg_sp], &stackphys)) {
mem->dump_stack(f, stackphys);
} else {
fprintf(f, "Stack: (not mapped in TLB)\n");
}
}
void
CPU::dump_mem(FILE *f, uint32 addr)
{
uint32 phys;
fprintf(f, "0x%08x: ", addr);
if (cpzero->debug_tlb_translate(addr, &phys)) {
mem->dump_mem(f, phys);
} else {
fprintf(f, "(not mapped in TLB)");
}
fprintf(f, "\n");
}
/* Disassemble a word at addr and print the result to f.
* FIXME: currently, f must be stderr, for the disassembler.
*/
void
CPU::dis_mem(FILE *f, uint32 addr)
{
uint32 phys;
uint32 instr;
if (cpzero->debug_tlb_translate(addr, &phys)) {
fprintf(f,"PC=0x%08x [%08x] %s",addr,phys,(addr==PL_REGS[WB_STAGE]->pc?"=>":" "));
instr = mem->fetch_word(phys,INSTFETCH, this);
fprintf(f,"%08x ",instr);
machine->disasm->disassemble(addr,instr);
} else {
fprintf(f,"PC=0x%08x [%08x] %s",addr,phys,(addr==PL_REGS[WB_STAGE]->pc?"=>":" "));
fprintf(f, "(not mapped in TLB)\n");
}
}
void
CPU::cpzero_dump_regs_and_tlb(FILE *f)
{
cpzero->dump_regs_and_tlb(f);
}
/* exception handling */
static const char *strexccode(const uint16 excCode) {
static const char *const exception_strs[] =
{
/* 0 */ "Interrupt",
/* 1 */ "TLB modification exception",
/* 2 */ "TLB exception (load or instr fetch)",
/* 3 */ "TLB exception (store)",
/* 4 */ "Address error exception (load or instr fetch)",
/* 5 */ "Address error exception (store)",
/* 6 */ "Instruction bus error",
/* 7 */ "Data (load or store) bus error",
/* 8 */ "SYSCALL exception",
/* 9 */ "Breakpoint32 exception (BREAK instr)",
/* 10 */ "Reserved instr exception",
/* 11 */ "Coprocessor Unusable",
/* 12 */ "Arithmetic Overflow",
/* 13 */ "Trap (R4k/R6k only)",
/* 14 */ "LDCz or SDCz to uncached address (R6k)",
/* 14 */ "Virtual Coherency Exception (instr) (R4k)",
/* 15 */ "Machine check exception (R6k)",
/* 15 */ "Floating-point32 exception (R4k)",
/* 16 */ "Exception 16 (reserved)",
/* 17 */ "Exception 17 (reserved)",
/* 18 */ "Exception 18 (reserved)",
/* 19 */ "Exception 19 (reserved)",
/* 20 */ "Exception 20 (reserved)",
/* 21 */ "Exception 21 (reserved)",
/* 22 */ "Exception 22 (reserved)",
/* 23 */ "Reference to WatchHi/WatchLo address detected (R4k)",
/* 24 */ "Exception 24 (reserved)",
/* 25 */ "Exception 25 (reserved)",
/* 26 */ "Exception 26 (reserved)",
/* 27 */ "Exception 27 (reserved)",
/* 28 */ "Exception 28 (reserved)",
/* 29 */ "Exception 29 (reserved)",
/* 30 */ "Exception 30 (reserved)",
/* 31 */ "Virtual Coherency Exception (data) (R4k)"
};
return exception_strs[excCode];
}
static const char *strmemmode(const int memmode) {
static const char *const memmode_strs[] =
{
"instruction fetch", /* INSTFETCH */
"data load", /* DATALOAD */
"data store", /* DATASTORE */
"not applicable" /* ANY */
};
return memmode_strs[memmode];
}
int
CPU::exception_priority(uint16 excCode, int mode) const
{
/* See doc/excprio for an explanation of this table. */
static const struct excPriority prio[] = {
{1, AdEL, INSTFETCH},
{2, TLBL, INSTFETCH}, {2, TLBS, INSTFETCH},
{3, IBE, ANY},
{4, Ov, ANY}, {4, Tr, ANY}, {4, Sys, ANY},
{4, Bp, ANY}, {4, RI, ANY}, {4, CpU, ANY},
{5, AdEL, DATALOAD}, {5, AdES, ANY},
{6, TLBL, DATALOAD}, {6, TLBS, DATALOAD},
{6, TLBL, DATASTORE}, {6, TLBS, DATASTORE},
{7, Mod, ANY},
{8, DBE, ANY},
{9, Int, ANY},
{0, ANY, ANY} /* catch-all */
};
const struct excPriority *p;
for (p = prio; p->priority != 0; p++) {
if (excCode == p->excCode || p->excCode == ANY) {
if (mode == p->mode || p->mode == ANY) {
return p->priority;
} else if (opt_excpriomsg) {
fprintf(stderr,
"exception code matches but mode %d != table %d\n",
mode,p->mode);
}
} else if (opt_excpriomsg) {
fprintf(stderr, "exception code %d != table %d\n", excCode,
p->excCode);
}
}
return 0;
}
void
CPU::exception(uint16 excCode, int mode /* = ANY */, int coprocno /* = -1 */)
{
//just buffer exception signal in this method
//handling buffered signals in exe_handle()
exc_signal = new ExcInfo();
exc_signal->excCode = excCode;
exc_signal->mode = mode;
exc_signal->coprocno = coprocno;
exception_pending = true;
}
void CPU::exc_handle(PipelineRegs *preg)
{
int prio;
int max_prio;
uint16 excCode;
int mode;
int coprocno;
uint32 base, vector, epc;
if (preg->excBuf.size() == 0) {
return;
}
/* Prioritize exception -- if the last exception to occur _also_ was
* caused by this EPC, only report this exception if it has a higher
* priority. Otherwise, exception handling terminates here,
* because only one exception will be reported per instruction
* (as per MIPS RISC Architecture, p. 6-35). Note that this only
* applies IFF the previous exception was caught during the current
* _execution_ of the instruction at this EPC, so we check that
* EXCEPTION_PENDING is true before aborting exception handling.
* (This flag is reset by each call to step().)
*/
max_prio = -1;
if (opt_excpriomsg & (preg->excBuf.size() > 1)) {
fprintf(stderr,
"(Ignoring additional lower priority exception...)\n");
}
//get highest priority of excCode
for (int i = 0; i < preg->excBuf.size(); i++) {
prio = exception_priority((preg->excBuf[i])->excCode, (preg->excBuf[i])->mode);
if (prio > max_prio) {
//update
excCode = (preg->excBuf[i])->excCode;
mode = (preg->excBuf[i])->mode;
coprocno = (preg->excBuf[i])->coprocno;
}
}
if (opt_haltbreak) {
if (excCode == Bp) {
fprintf(stderr,"* BREAK instruction reached -- HALTING *\n");
machine->halt();
}
}
if (opt_haltibe) {
if (excCode == IBE) {
fprintf(stderr,"* Instruction bus error occurred -- HALTING *\n");
machine->halt();
}
}
/* step() ensures that next_epc will always contain the correct
* ne whenever exception() is called.
*/
if (preg->delay_slot) {
epc = preg->pc - 4;
} else {
epc = preg->pc;
}
/* reset cache status */
icache->reset_stat();
dcache->reset_stat();
mem->release_bus(this);
/* Set processor to Kernel mode, disable interrupts, and save
* exception PC.
*/
cpzero->enter_exception(epc,excCode,coprocno,false);
/* Calculate the exception handler address; this is of the form BASE +
* VECTOR. The BASE is determined by whether we're using boot-time
* exception vectors, according to the BEV bit in the CP0 Status register.
*/
if (cpzero->use_boot_excp_address()) {
base = 0xbfc00100;
} else {
base = 0x80000000;
}
/* Do we have a User TLB Miss exception? If so, jump to the
* User TLB Miss exception vector, otherwise jump to the
* common exception vector.
*/
if ((excCode == TLBL || excCode == TLBS) && (cpzero->tlb_miss_user)) {
vector = 0x000;
} else {
vector = 0x080;
}
if (opt_excmsg && (excCode != Int || opt_reportirq)) {
fprintf(stderr,"Exception %d (%s) triggered, EPC=%08x\n", excCode,
strexccode(excCode), epc);
fprintf(stderr,
"Priority is %d; mem access mode is %s\n",
prio, strmemmode(mode));
if (excCode == Int) {
uint32 status, bad, cause;
cpzero->read_debug_info(&status, &bad, &cause);
fprintf (stderr, " Interrupt cause = %x, status = %x\n", cause, status);
}
//PC error
// fprintf(stderr,
// "** PC address translation caused the exception! **\n");
}
if (opt_tracing) {
if (tracing) {
current_trace.exception_happened = true;
current_trace.last_exception_code = excCode;
}
}
pc = base + vector - 4; //+4 later
volatilize_pipeline();
}
void
CPU::open_trace_file ()
{
char tracefilename[80];
for (unsigned i = 0; ; ++i) {
sprintf (tracefilename, "traceout%d.txt", i);
if (!can_read_file (tracefilename))
break;
}
traceout = fopen (tracefilename, "w");
}
void
CPU::close_trace_file ()
{
fclose (traceout);
}
void
CPU::write_trace_to_file ()
{
for (Trace::record_iterator ri = current_trace.rbegin (), re =
current_trace.rend (); ri != re; ++ri) {
Trace::Record &tr = *ri;
fprintf (traceout, "(TraceRec (PC #x%08x) (Insn #x%08x) ", tr.pc, tr.instr);
if (! tr.inputs.empty ()) {
fprintf (traceout, "(Inputs (");
for (std::vector<Trace::Operand>::iterator oi = tr.inputs.begin (),
oe = tr.inputs.end (); oi != oe; ++oi) {
Trace::Operand &op = *oi;
if (op.regno != -1) {
fprintf (traceout, "(%s %d #x%08x) ", op.tag, op.regno, op.val);
} else {
fprintf (traceout, "(%s #x%08x) ", op.tag, op.val);
}
}
fprintf (traceout, "))");
}
if (!tr.outputs.empty ()) {
fprintf (traceout, "(Outputs (");
for (std::vector<Trace::Operand>::iterator oi = tr.outputs.begin (),
oe = tr.outputs.end (); oi != oe; ++oi) {
Trace::Operand &op = *oi;
if (op.regno != -1) {
fprintf (traceout, "(%s %d #x%08x) ", op.tag, op.regno, op.val);
} else {
fprintf (traceout, "(%s #x%08x) ", op.tag, op.val);
}
}
fprintf (traceout, "))");
}
fprintf (traceout, ")\n");
}
// print lastchanges
fprintf (traceout, "(LastChanges (");
for (unsigned i = 0; i < 32; ++i) {
if (current_trace.last_change_for_reg.find (i) !=
current_trace.last_change_for_reg.end ()) {
last_change &lc = current_trace.last_change_for_reg[i];
fprintf (traceout,
"(Reg %d PC %x Instr %x OldValue %x CurValue %x) ",
i, lc.pc, lc.instr, lc.old_value, reg[i]);
}
}
fprintf (traceout, "))\n");
}
void
CPU::flush_trace()
{
if (!opt_tracing) return;
write_trace_to_file ();
current_trace.clear ();
}
void
CPU::start_tracing()
{
if (!opt_tracing) return;
tracing = true;
current_trace.clear ();
}
void
CPU::write_trace_instr_inputs (uint32 instr)
{
// rs,rt: add,addu,and,beq,bne,div,divu,mult,multu,nor,or,sb,sh,sllv,slt,
// sltu,srav,srlv,sub,subu,sw,swl,swr,xor
// rs: addi,addiu,andi,bgez,bgezal,bgtz,blez,bltz,bltzal,jal,jr,lb,lbu,
// lh,lhu,lw,lwl,lwr,mthi,mtlo,ori,slti,sltiu,xori
// hi: mfhi
// lo: mflo
// rt: mtc0
// rt,shamt: sll,sra,srl
// NOT HANDLED: syscall,break,jalr,cpone,cpthree,cptwo,cpzero,
// j,lui,lwc1,lwc2,lwc3,mtc0,swc1,swc2,swc3
switch(opcode(instr))
{
case 0:
switch(funct(instr))
{
case 4: //sllv
case 6: //srlv
case 7: //srav
case 24: //mult
case 25: //multu
case 26: //div
case 27: //divu
case 32: //add
case 33: //addu
case 34: //sub
case 35: //subu
case 36: //and
case 37: //or
case 38: //xor
case 39: //nor
case 42: //slt
case 43: //sltu
current_trace_record.inputs_push_back_op("rs",
rs(instr), reg[rs(instr)]);
current_trace_record.inputs_push_back_op("rt",
rt(instr), reg[rt(instr)]);
break;
case 0: //sll
case 2: //srl
case 3: //sra
current_trace_record.inputs_push_back_op("rt",
rt(instr), reg[rt(instr)]);
break;
case 8: //jr
case 17: //mthi
case 19: //mtlo
current_trace_record.inputs_push_back_op("rs",
rs(instr), reg[rs(instr)]);
break;
case 16: //mfhi
current_trace_record.inputs_push_back_op("hi",
hi);
break;
case 18: //mflo
current_trace_record.inputs_push_back_op("lo",
lo);
break;
}
break;
case 1:
switch(rt(instr)) {
case 0: //bltz
case 1: //bgez
case 16: //bltzal
case 17: //bgezal
current_trace_record.inputs_push_back_op("rs",
rs(instr), reg[rs(instr)]);
break;
}
break;
case 3: //jal
case 6: //blez
case 7: //bgtz
case 8: //addi
case 9: //addiu
case 12: //andi
case 32: //lb
case 33: //lh
case 35: //lw
case 36: //lbu
case 37: //lhu
case 40: //sb
case 41: //sh
case 42: //swl
case 43: //sw
case 46: //swr
current_trace_record.inputs_push_back_op("rs",
rs(instr), reg[rs(instr)]);
current_trace_record.inputs_push_back_op("rt",
rt(instr), reg[rt(instr)]);
break;
case 4: //beq
case 5: //bne
case 10: //slti
case 11: //sltiu
case 13: //ori
case 14: //xori
case 34: //lwl
case 38: //lwr
current_trace_record.inputs_push_back_op("rs",
rs(instr), reg[rs(instr)]);
break;
}
}
void
CPU::write_trace_instr_outputs (uint32 instr)
{
// hi,lo: div,divu,mult,multu
// hi: mthi
// lo: mtlo
// rt: addi,addiu,andi,lb,lbu,lh,lhu,lui,lw,lwl,lwr,mfc0,ori,slti,sltiu,
// xori
// rd: add,addu,and,jalr,mfhi,mflo,nor,or,sllv,slt,sltu,sll,sra,srav,srl,
// srlv,sub,subu,xor
// r31: jal
// NOT HANDLED: syscall,break,jalr,cpone,cpthree,cptwo,cpzero,j,lwc1,lwc2,
// lwc3,mtc0,swc1,swc2,swc3,jr,jalr,mfc0,bgtz,blez,sb,sh,sw,
// swl,swr,beq,bne
switch(opcode(instr))
{
case 0:
switch(funct(instr))
{
case 26: //div
case 27: //divu
case 24: //mult
case 25: //multu
current_trace_record.outputs_push_back_op("lo",
lo);
current_trace_record.outputs_push_back_op("hi",
hi);
break;
case 17: //mthi
current_trace_record.outputs_push_back_op("hi",
hi);
break;
case 19: //mtlo
current_trace_record.outputs_push_back_op("lo",
lo);
break;
case 32: //add
case 33: //addu
case 36: //and
case 39: //nor
case 37: //or
case 4: //sllv
case 42: //slt
case 43: //sltu
case 7: //srav
case 6: //srlv
case 34: //sub
case 35: //subu
case 38: //xor
case 0: //sll
case 3: //sra
case 2: //srl
case 16: //mfhi
case 18: //mflo
current_trace_record.outputs_push_back_op("rd",
rd(instr),reg[rd(instr)]);
break;
}
break;
case 8: //addi
case 9: //addiu
case 12: //andi
case 32: //lb
case 36: //lbu
case 33: //lh
case 37: //lhu
case 35: //lw
case 34: //lwl
case 38: //lwr
case 13: //ori
case 10: //slti
case 11: //sltiu
case 14: //xori
case 15: //lui
current_trace_record.outputs_push_back_op("rt",rt(instr),
reg[rt(instr)]);
break;
case 3: //jal
current_trace_record.outputs_push_back_op("ra",
reg[reg_ra]);
break;
}
}
void
CPU::write_trace_record_1(uint32 pc, uint32 instr)
{
current_trace_record.clear ();
current_trace_record.pc = pc;
current_trace_record.instr = instr;
write_trace_instr_inputs (instr);
std::copy (®[0], ®[32], ¤t_trace_record.saved_reg[0]);
}
void
CPU::write_trace_record_2 (uint32 pc, uint32 instr)
{
write_trace_instr_outputs (instr);
// which insn was the last to change each reg?
for (unsigned i = 0; i < 32; ++i) {
if (current_trace_record.saved_reg[i] != reg[i]) {
current_trace.last_change_for_reg[i] = last_change::make (pc, instr,
current_trace_record.saved_reg[i]);
}
}
current_trace.push_back_record (current_trace_record);
if (current_trace.record_size () > opt_tracesize)
flush_trace ();
}
void
CPU::stop_tracing()
{
tracing = false;
}
void CPU::fetch(bool& fetch_miss, bool data_miss)
{
bool cacheable;
uint32 real_pc;
uint32 fetch_instr;
Cache *cache = cpzero->caches_swapped() ? dcache : icache;
fetch_miss = true;
if (pc % 4 != 0) {
//Addr Error
exception(AdEL);
} else {
real_pc = cpzero->address_trans(pc,INSTFETCH,&cacheable, this);
}
if (exception_pending) {
PL_REGS[IF_STAGE] = new PipelineRegs(pc, NOP_INSTR);
PL_REGS[IF_STAGE]->excBuf.emplace_back(exc_signal);
//reset signal
exception_pending = false;
} else {
// Fetch next instruction.
if (cacheable) {
fetch_miss = !cache->ready(real_pc);
if (fetch_miss & !data_miss) {
cache->request_block(real_pc, INSTFETCH, this);
}
} else {
if (mem->acquire_bus(this)) {
fetch_miss = !mem->ready(real_pc,INSTFETCH,this);
if (fetch_miss & !data_miss) {
mem->request_word(real_pc,INSTFETCH,this);
}
}
}
// in case of no stall
if (!fetch_miss) {
if (cacheable) {
fetch_instr = cache->fetch_word(real_pc,INSTFETCH, this);
} else {
fetch_instr = mem->fetch_word(real_pc,INSTFETCH,this);
mem->release_bus(this);
}
PL_REGS[IF_STAGE] = new PipelineRegs(pc, fetch_instr);
// Disassemble the instruction, if the user requested it.
if (opt_instdump) {
fprintf(stderr,"PC=0x%08x [%08x]\t%08x ",pc,real_pc,fetch_instr);
machine->disasm->disassemble(pc,fetch_instr);
}
//check exception
if (exception_pending) {
PL_REGS[IF_STAGE] = new PipelineRegs(pc, NOP_INSTR);
PL_REGS[IF_STAGE]->excBuf.emplace_back(exc_signal);
//reset signal
exception_pending = false;
}
}
}
}
void CPU::pre_decode(bool& data_hazard)
{
PipelineRegs *preg = PL_REGS[ID_STAGE];
uint32 dec_instr = preg->instr;
uint16 dec_opcode = opcode(dec_instr);
// check if it is Reserved Instr
//decode first source
switch (dec_opcode) {
case OP_SPECIAL:
if (RI_special_flag[funct(dec_instr)]) {
exception(RI);
preg->instr = NOP_INSTR;
}
break;
case OP_CACHE:
if (RI_cache_op_flag[rt(dec_instr)]) {
exception(RI);
preg->instr = NOP_INSTR;
}
default:
if (RI_flag[dec_opcode]) {
exception(RI);
preg->instr = NOP_INSTR;
}
}
//decode first source
switch (dec_opcode) {
case OP_SPECIAL:
preg->src_a = firstSrcDecSpecialTable[funct(dec_instr)](dec_instr);
break;
case OP_BCOND:
preg->src_a = firstSrcDecBcondTable[rt(dec_instr)](dec_instr);
break;
case OP_COP0:
case OP_COP1:
case OP_COP2:
case OP_COP3:
preg->src_a = rs(dec_instr) == COP_OP_MTC ? rt(dec_instr) : NONE_REG;
break;
default:
preg->src_a = firstSrcDecTable[dec_opcode](dec_instr);
}
//decode second source
switch (dec_opcode) {
case OP_SPECIAL:
preg->src_b = secondSrcDecSpecialTable[funct(dec_instr)](dec_instr);
break;
default:
preg->src_b = secondSrcDecTable[dec_opcode](dec_instr);
}
//decode destination
switch (dec_opcode) {
case OP_SPECIAL:
preg->dst = dstDecSpecialTable[funct(dec_instr)](dec_instr);
break;
case OP_COP0:
case OP_COP1:
case OP_COP2:
case OP_COP3:
preg->dst = rs(dec_instr) == COP_OP_MFC ? rt(dec_instr) : NONE_REG;
break;
case OP_BCOND:
preg->dst = (rt(dec_instr) == BCONDE_BLTZAL
|| rt(dec_instr) == BCONDE_BGEZAL) ? RA_REG : NONE_REG;
break;
default:
preg->dst = dstDecTable[dec_opcode](dec_instr);
}
if (preg->dst == 0) preg->dst = NONE_REG;
//decode value A
data_hazard = false;
if (preg->src_a != NONE_REG) {
//forwarding for A
if (preg->src_a == PL_REGS[EX_STAGE]->dst) {
if (PL_REGS[EX_STAGE]->mem_read_op) data_hazard = true;
preg->alu_src_a = PL_REGS[EX_STAGE]->w_reg_data;
} else if (preg->src_a == PL_REGS[MEM_STAGE]->dst) {
preg->alu_src_a = PL_REGS[MEM_STAGE]->w_reg_data;
} else if (preg->src_a == PL_REGS[WB_STAGE]->dst) {
preg->alu_src_a = PL_REGS[WB_STAGE]->w_reg_data;
} else {
preg->alu_src_a = ®[preg->src_a];
}
}
//decode shamt & imm
if (dec_opcode == OP_SPECIAL) {
if (shamt_flag[funct(dec_instr)]) {
preg->shamt = (uint32)shamt(dec_instr);
}
} else {
if (imm_flag[dec_opcode]) {
preg->imm = (uint32)immed(dec_instr);
} else if (s_imm_flag[dec_opcode]) {
preg->imm = (uint32)s_immed(dec_instr);
}
}
//decode value B
if (preg->src_b != NONE_REG) {
//forwarding for B
if (preg->src_b == PL_REGS[EX_STAGE]->dst) {
preg->alu_src_b = PL_REGS[EX_STAGE]->w_reg_data;
if (PL_REGS[EX_STAGE]->mem_read_op) data_hazard = true;
} else if (preg->src_b == PL_REGS[MEM_STAGE]->dst) {
preg->alu_src_b = PL_REGS[MEM_STAGE]->w_reg_data;
} else if (preg->src_b == PL_REGS[WB_STAGE]->dst) {
preg->alu_src_b = PL_REGS[WB_STAGE]->w_reg_data;
} else {
preg->alu_src_b = ®[preg->src_b];
}
} else {
if (dec_opcode == OP_SPECIAL) {
if (shamt_flag[funct(dec_instr)]) {
preg->alu_src_b = &(preg->shamt);
}
} else {
if (imm_flag[dec_opcode] || s_imm_flag[dec_opcode]) {
preg->alu_src_b = &(preg->imm);
}
}
}
//decode LWL/LWR
if (dec_opcode == OP_LWL || dec_opcode == OP_LWR) {
if (preg->dst == PL_REGS[EX_STAGE]->dst) {
//forwarding
preg->lwrl_reg_prev = PL_REGS[EX_STAGE]->w_reg_data;
} else {
preg->lwrl_reg_prev = ®[preg->dst];
}
}
//decode write reg data
if (preg->dst != NONE_REG) {
if (mem_read_flag[dec_opcode]) {
//load operation
preg->mem_read_op = true;
preg->w_reg_data = &(preg->r_mem_data);
} else {
preg->w_reg_data = &(preg->result);
}
}
//decode write mem data
if (mem_write_flag[dec_opcode]) {
if (rt(dec_instr) == PL_REGS[EX_STAGE]->dst) {
//fowrding
preg->w_mem_data = PL_REGS[EX_STAGE]->w_reg_data;
} else {
preg->w_mem_data = ®[rt(dec_instr)];
}
}
//store exception
if (exception_pending) {
preg->excBuf.emplace_back(exc_signal);
//reset signal
exception_pending = false;
}
}
void CPU::decode()
{
static alu_funcpr execTable[64] = {
&CPU::funct_ctrl, &CPU::bcond_exec, &CPU::j_exec, &CPU::jal_exec, &CPU::beq_exec, &CPU::bne_exec, &CPU::blez_exec, &CPU::bgtz_exec,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
&CPU::cpzero_exec, &CPU::cpone_exec, &CPU::cptwo_exec, &CPU::cpthree_exec, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
};
/* To forward from ex_stage & mem_stage to this for control OPs