diff --git a/src/common/lpspi/bus.rs b/src/common/lpspi/bus.rs
index 27d0548e..147c17a8 100644
--- a/src/common/lpspi/bus.rs
+++ b/src/common/lpspi/bus.rs
@@ -230,6 +230,8 @@ impl<'a, const N: u8> Lpspi<'a, N> {
                     tx_buffer[i] = data.add(i).read();
                 }
             }
+
+            ral::write_reg!(ral::lpspi, self.lpspi(), TDR, u32::from_be_bytes(tx_buffer));
         }
     }
 
@@ -256,8 +258,8 @@ impl<'a, const N: u8> Lpspi<'a, N> {
 
         self.clear_fifos();
 
-        let _read_task = async { assert!(!sequence.contains_read_actions()) };
-        let _write_task = async {
+        let read_task = async { assert!(!sequence.contains_read_actions()) };
+        let write_task = async {
             unsafe {
                 let has_phase_1 = sequence.phase1.is_some();
                 let has_phase_2 = sequence.phase2.is_some();
@@ -315,7 +317,9 @@ impl<'a, const N: u8> Lpspi<'a, N> {
             }
         };
 
-        Ok(())
+        futures::join!(read_task, write_task);
+
+        self.check_errors()
     }
 
     /// Perform a sequence of transfer actions while continuously checking for errors.
diff --git a/src/common/lpspi/transfer_actions.rs b/src/common/lpspi/transfer_actions.rs
index a4428b30..1fec9a93 100644
--- a/src/common/lpspi/transfer_actions.rs
+++ b/src/common/lpspi/transfer_actions.rs
@@ -1,5 +1,6 @@
 use core::{marker::PhantomData, num::NonZeroUsize};
 
+#[derive(Debug)]
 pub(crate) struct DualDirectionActions {
     read_buf: *mut u8,
     write_buf: *const u8,
@@ -117,21 +118,25 @@ impl Iterator for SingleDirectionWriteActionIter {
     }
 }
 
+#[derive(Debug)]
 pub(crate) struct ReadActions {
     read_buf: *mut u8,
     len: [usize; 3],
 }
 
+#[derive(Debug)]
 pub(crate) struct WriteActions {
     write_buf: *const u8,
     len: [usize; 3],
 }
 
+#[derive(Debug)]
 pub(crate) struct MaybeWriteActions {
     write_buf: Option<*const u8>,
     len: [usize; 3],
 }
 
+#[derive(Debug)]
 pub(crate) enum SingleDirectionActions {
     Read(ReadActions),
     Write(WriteActions),
@@ -161,7 +166,7 @@ impl SingleDirectionActions {
 
 /// The order in which the bytes need
 /// to be transferred on the bus
-#[derive(Copy, Clone, PartialEq, Eq)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum ByteOrder {
     /// Bytes need to be transferred in the order
     /// that they are in
@@ -172,12 +177,13 @@ pub enum ByteOrder {
     HalfWordReversed,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub(crate) enum TransferDirection {
     Read,
     Write,
 }
 
+#[derive(Debug)]
 pub(crate) struct ActionSequence<'a> {
     pub(crate) phase1: Option<DualDirectionActions>,
     pub(crate) phase2: Option<SingleDirectionActions>,