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synth-sv.yml
34 workflow runs
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run-tests.sh: build project with tests synth-sv #9: Commit 0474d08 pushed by ssmolov
August 15, 2024 11:29 1m 30s master
master
August 15, 2024 11:29 1m 30s
rm tool-run.sh synth-sv #8: Commit 0389005 pushed by ssmolov
August 15, 2024 11:16 1m 33s master
master
August 15, 2024 11:16 1m 33s
run-tests.sh: fixed synth-sv #7: Commit 6a9fe0c pushed by ssmolov
August 15, 2024 11:16 1m 24s master
master
August 15, 2024 11:16 1m 24s
Merge pull request #47 from ispras/fix_dfcir_offset synth-sv #6: Commit 9439c8d pushed by ssmolov
August 15, 2024 10:53 1m 28s master
master
August 15, 2024 10:53 1m 28s
Fixed DFCIR OffsetOp printing synth-sv #5: Pull request #47 opened by Muxianesty
August 14, 2024 14:26 1m 31s fix_dfcir_offset
fix_dfcir_offset
August 14, 2024 14:26 1m 31s
Merge pull request #46 from ispras/check_verilog_ci synth-sv #4: Commit abb1719 pushed by ssmolov
August 14, 2024 10:59 2m 28s master
master
August 14, 2024 10:59 2m 28s
CI workflow for SystemVerilog syntax checking synth-sv #3: Pull request #46 synchronize by Muxianesty
August 14, 2024 10:56 2m 10s check_verilog_ci
check_verilog_ci
August 14, 2024 10:56 2m 10s
CI workflow for SystemVerilog syntax checking synth-sv #2: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:25 3m 15s check_verilog_ci
check_verilog_ci
August 14, 2024 08:25 3m 15s
CI workflow for SystemVerilog syntax checking synth-sv #1: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:22 2m 46s check_verilog_ci
check_verilog_ci
August 14, 2024 08:22 2m 46s