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comparator_gainlatch_LDS.net
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comparator_gainlatch_LDS.net
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* Z:\home\sbecht\ultra-efficient-adc\comparator_gainlatch_LDS.asc
M8 Dout Disable neg neg nfet l=1.8u w=3.6u
M6 N001 N001 posD posA pfet l=2.7u w=4.5u
M7 N003 N001 Dout posA pfet l=0.6u w=0.9u
M11 N003 Disable posD posA pfet l=2.7u w=4.5u
M1 N1 Cascode N002 posA pfet l=2.4u w=4.8u
M2 N1 Vm N2 posA pfet l=3.6u w=3.6u
M3 N3 Vp N1 posA pfet l=3.6u w=3.6u
M4 neg N3 Dout neg nfet l=2.7u w=2.4u
M5 N3 N3 neg neg nfet l=2.7u w=2.4u
M9 N002 Vbias posA posA pfet l=18u w=9u
M10 N001 Dout neg neg nfet l=1.8u w=3.6u
M12 neg N2 N001 neg nfet l=2.7u w=2.4u
M13 N2 N2 neg neg nfet l=2.7u w=2.4u
M18 Dout Disable neg neg nfet l=1.8u w=3.6u
M19 N001 N001 posD posA pfet l=2.7u w=4.5u
M20 N003 N001 Dout posA pfet l=0.6u w=0.9u
M21 N003 Disable posD posA pfet l=2.7u w=4.5u
M22 N1 Cascode N002 posA pfet l=2.4u w=4.8u
M23 N1 Vm N2 posA pfet l=3.6u w=3.6u
M24 N3 Vp N1 posA pfet l=3.6u w=3.6u
M25 neg N3 Dout neg nfet l=2.7u w=2.4u
M26 N3 N3 neg neg nfet l=2.7u w=2.4u
M27 N002 Vbias posA posA pfet l=18u w=9u
M28 N001 Dout neg neg nfet l=1.8u w=3.6u
M29 neg N2 N001 neg nfet l=2.7u w=2.4u
M30 N2 N2 neg neg nfet l=2.7u w=2.4u
.backanno
.end