From 9fb388407a747b605705e4d68a54fe4984fc1618 Mon Sep 17 00:00:00 2001
From: rniwase <rniwase@users.noreply.github.com>
Date: Sat, 14 Oct 2023 00:00:26 +0900
Subject: [PATCH] targets/xilinx_zcu102: Add litedram to the target.

---
 litex_boards/targets/xilinx_zcu102.py | 53 ++++++++++++++++++++++++---
 1 file changed, 48 insertions(+), 5 deletions(-)

diff --git a/litex_boards/targets/xilinx_zcu102.py b/litex_boards/targets/xilinx_zcu102.py
index 9e98f99ad..57aac75a2 100755
--- a/litex_boards/targets/xilinx_zcu102.py
+++ b/litex_boards/targets/xilinx_zcu102.py
@@ -4,6 +4,7 @@
 # This file is part of LiteX-Boards.
 #
 # Copyright (c) 2022 Joseph FAYE <joseph-wagane.faye@insa-rennes.fr>
+# Copyright (c) 2023 Ryohei Niwase <niwase@lila.cs.tsukuba.ac.jp>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
@@ -12,26 +13,68 @@
 
 from litex_boards.platforms import xilinx_zcu102
 
-from litex.build.io import CRG
-
+from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
-
 from litex.soc.cores.led import LedChaser
 
+from litedram.modules import MT40A256M16
+from litedram.phy import usddrphy
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(LiteXModule):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst       = Signal()
+        self.cd_sys    = ClockDomain()
+        self.cd_sys4x  = ClockDomain()
+        self.cd_pll4x  = ClockDomain()
+        self.cd_idelay = ClockDomain()
+
+        # # #
+
+        self.pll = pll = USMMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
+        pll.register_clkin(platform.request("clk125"), 125e6)
+        pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
+        pll.create_clkout(self.cd_idelay, 500e6)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
+
+        self.specials += [
+            Instance("BUFGCE_DIV",
+                p_BUFGCE_DIVIDE=4,
+                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
+            Instance("BUFGCE",
+                i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
+        ]
+
+        self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=125e6, with_ethernet=False, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, **kwargs):
         platform = xilinx_zcu102.Platform()
 
         # CRG --------------------------------------------------------------------------------------
-        self.crg = CRG(platform.request("clk125"))
+        self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU102", **kwargs)
 
+        # DDR4 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
+                memtype          = "DDR4",
+                sys_clk_freq     = sys_clk_freq,
+                iodelay_clk_freq = 500e6)
+            self.add_sdram("sdram",
+                phy           = self.ddrphy,
+                module        = MT40A256M16(sys_clk_freq, "1:4"),
+                size          = 0x20000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
+            )
+
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.leds = LedChaser(