Tang Nano 4K and 20K boards broken on vendor tools

[pepijndevos]

On the 20K I needed to add self.toolchain.options["use_mode_as_gpio"] = 1 and then stuff seemed to work, though I don't have the hardware currently so I'm hesitant to submit a PR until my AliExpress order arrives.

4K seems bitrotted? First I got errors that kB isn't defined. There is a capital K definition but I'm not sure if that would mix bits and bytes. But when running --with-hyperram there are further errors using V1.9.8:

*** GOWIN Tcl Command Line Console  *** 
current device: GW1NSR-4C  GW1NSR-LV4CQN48PC6/I5
add new file: "sipeed_tang_nano_4k.cst"
add new file: "sipeed_tang_nano_4k.sdc"
add new file: "/home/pepijn/code/apicula/env/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/picorv32.v"
add new file: "/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/home/pepijn/code/apicula/env/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/picorv32.v'
Analyzing Verilog file '/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v'
WARN  (EX3373) : Port 'IO_hpram_rwds' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":23)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":23)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":23)
WARN  (EX3373) : Port 'O_hpram_ck' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":24)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":24)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":24)
WARN  (EX3373) : Port 'O_hpram_ck_n' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":25)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":25)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":25)
WARN  (EX3373) : Port 'O_hpram_cs_n' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":26)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":26)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":26)
WARN  (EX3373) : Port 'O_hpram_reset_n' must not be declared to be an array("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":27)
ERROR (EX3657) : Size of an unpacked array must be a positive value("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":27)
ERROR (EX3588) : Single value range is not allowed in this mode of Verilog("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":27)
ERROR (EX3928) : Module 'sipeed_tang_nano_4k' is ignored due to previous errors("/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v":4227)
Verilog file '/home/pepijn/code/apicula/litex-boards/litex_boards/targets/build/sipeed_tang_nano_4k/gateware/sipeed_tang_nano_4k.v' ignored due to errors

So that requires further investigation... the problem seems to be that the IDE is very particular about if its magic pin names are single bit vectors or single bits.