From 0eabebfb05c9bb4c4bb4e635a1d4fd02d447d98d Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
Date: Thu, 10 Oct 2024 07:15:10 +0200
Subject: [PATCH] platforms/xilinx_zcu102.py: Add all SFP connectors

---
 litex_boards/platforms/xilinx_zcu102.py | 75 +++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/litex_boards/platforms/xilinx_zcu102.py b/litex_boards/platforms/xilinx_zcu102.py
index 8c898787a..16ccfc3fd 100644
--- a/litex_boards/platforms/xilinx_zcu102.py
+++ b/litex_boards/platforms/xilinx_zcu102.py
@@ -103,6 +103,81 @@
         Subsignal("reset_n", Pins("AH9"), IOStandard("LVCMOS18")),
         Misc("SLEW=FAST"),
     ),
+
+    # GTP RefClk common to all SFPs.
+    ("mgt_refclk", 0,
+        Subsignal("p", Pins("C8")),
+        Subsignal("n", Pins("C7")),
+    ),
+
+    # SFP.
+    # Right Top (GT Location: X1Y12).
+    ("sfp_tx_disable_n", 0, Pins("A12"), IOStandard("LVCMOS33")),
+    ("sfp", 0,
+        Subsignal("txp", Pins("E4")),
+        Subsignal("txn", Pins("E3")),
+        Subsignal("rxp", Pins("D2")),
+        Subsignal("rxn", Pins("D1")),
+    ),
+    ("sfp_tx", 0,
+        Subsignal("p", Pins("E4")),
+        Subsignal("n", Pins("E3")),
+    ),
+    ("sfp_rx", 0,
+        Subsignal("p", Pins("D2")),
+        Subsignal("n", Pins("D1")),
+    ),
+
+    # Right Bottom (GT Location: X1Y13).
+    ("sfp_tx_disable_n", 1, Pins("A13"), IOStandard("LVCMOS33")),
+    ("sfp", 1,
+        Subsignal("txp", Pins("D6")),
+        Subsignal("txn", Pins("D5")),
+        Subsignal("rxp", Pins("C4")),
+        Subsignal("rxn", Pins("C3")),
+    ),
+    ("sfp_tx", 1,
+        Subsignal("p", Pins("D6")),
+        Subsignal("n", Pins("D5")),
+    ),
+    ("sfp_rx", 1,
+        Subsignal("p", Pins("C4")),
+        Subsignal("n", Pins("C3")),
+    ),
+
+    # Left Top (GT Location: X1Y14).
+    ("sfp_tx_disable_n", 2, Pins("B13"), IOStandard("LVCMOS33")),
+    ("sfp", 2,
+        Subsignal("txp", Pins("B6")),
+        Subsignal("txn", Pins("B5")),
+        Subsignal("rxp", Pins("B2")),
+        Subsignal("rxn", Pins("B1")),
+    ),
+    ("sfp_tx", 2,
+        Subsignal("p", Pins("B6")),
+        Subsignal("n", Pins("B5")),
+    ),
+    ("sfp_rx", 2,
+        Subsignal("p", Pins("B2")),
+        Subsignal("n", Pins("B1")),
+    ),
+
+    # Left Bottom (GT Location: X1Y15).
+    ("sfp_tx_disable_n", 3, Pins("C13"), IOStandard("LVCMOS33")),
+    ("sfp", 3,
+        Subsignal("txp", Pins("A8")),
+        Subsignal("txn", Pins("A7")),
+        Subsignal("rxp", Pins("A4")),
+        Subsignal("rxn", Pins("A3")),
+    ),
+    ("sfp_tx", 3,
+        Subsignal("p", Pins("A8")),
+        Subsignal("n", Pins("A7")),
+    ),
+    ("sfp_rx", 3,
+        Subsignal("p", Pins("A4")),
+        Subsignal("n", Pins("A3")),
+    ),
 ]
 
 # Connectors ---------------------------------------------------------------------------------------