FPGA programming question

[schaferben]

Hello,

I am a little bit puzzled about the FPGA bitstream configuration ports. From the figure in

https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/testbench/

I can see that the FPGA needs three programming ports: prog_clk, prog_rst, and prog_input.

These ports allow to scan in the bitstream to configure the FPGA. When going through the basic examples I can see though that only prog_clk is generated. In this case how is the FPGA configured? Is the FPGA hardcoded? How can I generate the three configuration ports to program the FPGA with any external bitstream?

Thank you,
Ben

[tangxifan]

@schaferben I believe you are using the configuration chain as the configuration protocol.

• You can find details in the documentation: https://openfpga.readthedocs.io/en/master/manual/arch_lang/config_protocol/#configuration-chain-example
• When using the configuration chain, bitstream should be loaded through the ccff_head ports. You may refer to the following waveform. Please note that the prog_rst (pReset in the following figure) may not be required due to the nature of configuration chain

• If you customize the CCFF model in openfpga architecture example, you can select if you need any programming ports under a selected configuration protocol.

https://openfpga.readthedocs.io/en/master/manual/arch_lang/circuit_model_examples/#circuit-model-ccff-example

• If you would like to know how the bitstream should be downloaded. You may refer to the full testbench (.v) under your openfpga task (See tutorial). If you run iverilog, you can view the waveform through GTKwave.