V1.1.0 #545

tangxifan announced in Announcements

tangxifan
Feb 21, 2022
Maintainer

Release v1.1.0

This is NOT a long-term support version!!!

🔥 After ~4k commits since last release, OpenFPGA has experienced several major updates.

Bring VPR8 as a core engine
Fully rewrite the codebase to follow a modern user interface, especially openfpga has a shell-like interface
All the OpenFPGA commands now have documentation
All the OpenFPGA file formats now have documentation
Deploy regression tests for all the features
Built a library of FPGA architecture files to showcase OpenFPGA features
Reworked documentation for each tools, FPGA-Verilog/FPGA-Bitstream/FPGA-SDC

⌚ Sorry for not releasing it regularly. We are trying to it every quarter from now on.

What's Changed

Update README from Tim by @tangxifan in Update README from Tim #30
Update master with latest development version by @tangxifan in Update master with latest development version #31
Misc Updates on regression tests and clean-up flow run by @tangxifan in Misc Updates on regression tests and clean-up flow run #32
Remove legacy codes in FPGA-Verilog by @tangxifan in Remove legacy codes in FPGA-Verilog #33
Dev by @tangxifan in Dev #34
Fix tutorial configuration file by @skulis in Fix tutorial configuration file #36
Fix docker file (do not run make multi threaded) by @skulis in Fix docker file (do not run make multi threaded) #35
architecture fix for tutorial purpose by @AurelienUoU in architecture fix for tutorial purpose #38
Remove redundant net source addition in CBs and SBs by @tangxifan in Remove redundant net source addition in CBs and SBs #39
Dev by @AurelienUoU in Dev #40
bug fixed in SDC for CBs and SBs: remove useless module names by @AurelienUoU in bug fixed in SDC for CBs and SBs: remove useless module names #41
Dev by @AurelienUoU in Dev #43
Fix GUI support with cmake 3.16 by @srtemp in Fix GUI support with cmake 3.16 #44
Update dev to be even with master's documentation update by @LNIS-Projects in Update dev to be even with master's documentation update #45
Ganesh dev by @tangxifan in Ganesh dev #51
Porting Dev branch to master by @tangxifan in Porting Dev branch to master #53
Dev by @tangxifan in Dev #56
Bug fix in the line parser when dealing with empty inputs for Centos 8 which is strict on this by @tangxifan in Bug fix in the line parser when dealing with empty inputs for Centos 8 which is strict on this #57
Memory, runtime and netlist size optimization by @tangxifan in Memory, runtime and netlist size optimization #58
Runtime and memory improvement on bitstream database by @tangxifan in Runtime and memory improvement on bitstream database #59
Bug fix in reserve configuration blocks for bitstream manager to optimize memory usage by @tangxifan in Bug fix in reserve configuration blocks for bitstream manager to optimize memory usage #60
Remove obsolete codes and restructure compilation options by @tangxifan in Remove obsolete codes and restructure compilation options #61
Simplify fabric key where users just need to provide alias; start porting FPGA-SPICE by @tangxifan in Simplify fabric key where users just need to provide alias; start porting FPGA-SPICE #62
Improve runtime of fabric key loading; Documentation update for different file format of fabric keys by @tangxifan in Improve runtime of fabric key loading; Documentation update for different file format of fabric keys #63
using a unified string to replace multi net names to save memory of b… by @tangxifan in using a unified string to replace multi net names to save memory of b… #64
Updated Dockerfile for Ubuntu 18.04 by @samycharas in Updated Dockerfile for Ubuntu 18.04 #66
hotfix on treating the dangling ports in pb_graph for analysis SDC ge… by @tangxifan in hotfix on treating the dangling ports in pb_graph for analysis SDC ge… #67
Remove obsolete documentation and add technology binding by @tangxifan in Remove obsolete documentation and add technology binding #68
Bug fix in yosys-vpr flow using OpenFPGA shell; by @tangxifan in Bug fix in yosys-vpr flow using OpenFPGA shell; #69
Misc Updates by @tangxifan in Misc Updates #70
Fabric Bitstream file writer by @tangxifan in Fabric Bitstream file writer #72
Misc Updates by @tangxifan in Misc Updates #73
Update FPGA-Bitstream regression tests to track runtime of large devices and practical benchmarks by @tangxifan in Update FPGA-Bitstream regression tests to track runtime of large devices and practical benchmarks #74
Misc Updates by @tangxifan in Misc Updates #77
[Architecture Languange] Patch the default circuit model definition by @tangxifan in [Architecture Languange] Patch the default circuit model definition #79
Update documentation and debugging aid by @tangxifan in Update documentation and debugging aid #81
Enriched regression test for flexible routing multiplexer designs by @tangxifan in Enriched regression test for flexible routing multiplexer designs #83
Add compiler compatibility tests to Travis CI by @tangxifan in Add compiler compatibility tests to Travis CI #84
Support on flexible local routing architecture by @tangxifan in Support on flexible local routing architecture #85
Misc Updates by @tangxifan in Misc Updates #86
Transplant FPGA-SPICE to OpenFPGA by @tangxifan in Transplant FPGA-SPICE to OpenFPGA #87
Update issue templates by @tangxifan in Update issue templates #88
Regression test & architecture updates by @tangxifan in Regression test & architecture updates #89
Architecture and regression test update by @tangxifan in Architecture and regression test update #90
[Regression Tests] Remove deadlink by @tangxifan in [Regression Tests] Remove deadlink #91
Smart Configuration Support and Verilog Netlist Refactoring by @tangxifan in Smart Configuration Support and Verilog Netlist Refactoring #92
[Architecture] Reorganize the cell netlists and update architecture f… by @tangxifan in [Architecture] Reorganize the cell netlists and update architecture f… #93
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name by @tangxifan in [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name #94
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done… by @tangxifan in [OpenFPGA Tool] Add self-testing Verilog codes for configuration done… #96
Deprecated Code Removal by @tangxifan in Deprecated Code Removal #97
Support of multiple regions for configuration chain by @tangxifan in Support of multiple regions for configuration chain #98
Edits to enable basic run_fpga_flow.py by @lukefahr in Edits to enable basic run_fpga_flow.py #100
Documentation Update to Include Technical Features by @tangxifan in Documentation Update to Include Technical Features #101
Fixed blif formatting bug by @lukefahr in Fixed blif formatting bug #102
FLOW: fixed display flag by @lukefahr in FLOW: fixed display flag #104
Docs: Updated note to enable VPR's GUI by @lukefahr in Docs: Updated note to enable VPR's GUI #103
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates by @tangxifan in Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates #105
Documentation update by @tangxifan in Documentation update #106
Enable Customized Fabric Netlist Location in Verilog Testbench Generation by @tangxifan in Enable Customized Fabric Netlist Location in Verilog Testbench Generation #107
Add test cases for constant inputs of routing multiplexers by @tangxifan in Add test cases for constant inputs of routing multiplexers #108
Frontpage README Update with more links to documentation pages by @tangxifan in Frontpage README Update with more links to documentation pages #109
Bug fix in tutorial due to renamed regression tests by @tangxifan in Bug fix in tutorial due to renamed regression tests #111
Multi-region Memory Bank Configuration Protocol Support by @tangxifan in Multi-region Memory Bank Configuration Protocol Support #112
Multi-region support on Frame-based Configuration Protocol by @tangxifan in Multi-region support on Frame-based Configuration Protocol #113
Support I/O interfaces for Embedded FPGAs by @tangxifan in Support I/O interfaces for Embedded FPGAs #114
Refactor the codes for walking through io blocks by @tangxifan in Refactor the codes for walking through io blocks #115
Extended I/O Support for SoC I/O interface by @tangxifan in Extended I/O Support for SoC I/O interface #116
Update README.md by @olofk in Update README.md #117
Remove the restrictions on requiring two outputs for configurable memory circuits by @tangxifan in Remove the restrictions on requiring two outputs for configurable memory circuits #118
Support Global Port Definition for Physical Tile Ports by @tangxifan in Support Global Port Definition for Physical Tile Ports #122
Add Illustrative Example to Documentation to Explain the Difference on Global Port Definitions between Circuit Model and Tile Annotation by @tangxifan in Add Illustrative Example to Documentation to Explain the Difference on Global Port Definitions between Circuit Model and Tile Annotation #123
Add readthedoc Setting File by @tangxifan in Add readthedoc Setting File #124
Multiple Bug Fixes by @tangxifan in Multiple Bug Fixes #126
Bug fix for global clock port using physical tile pins by @tangxifan in Bug fix for global clock port using physical tile pins #127
Generate Signal Initialization in Verilog Testbenches rather than HDL netlists by @tangxifan in Generate Signal Initialization in Verilog Testbenches rather than HDL netlists #129
Fix for rr graph loading by VPR by @mkurc-ant in Fix for rr graph loading by VPR #130
Use GitHub Actions as CI by @tangxifan in Use GitHub Actions as CI #133
Improvements on Signal Initialization in Testbench Generation by @tangxifan in Improvements on Signal Initialization in Testbench Generation #131
Support on Native Fracturable LUT Design by @tangxifan in Support on Native Fracturable LUT Design #135
Update README with latest Github Action badge by @tangxifan in Update README with latest Github Action badge #139
Add a Test Case to CI which defines global reset port through tile port in VPR architecture by @tangxifan in Add a Test Case to CI which defines global reset port through tile port in VPR architecture #141
Critical Bug fix in the XML Syntax when Defining Default Values for A Global Tile Port by @tangxifan in Critical Bug fix in the XML Syntax when Defining Default Values for A Global Tile Port #143
Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches by @tangxifan in Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches #144
Bug fix in LUT circuit model documentation by @tangxifan in Bug fix in LUT circuit model documentation #146
Support I/O tiles in the center part of FPGA grid layout by @tangxifan in Support I/O tiles in the center part of FPGA grid layout #147
Organize Routing Multiplexer Verilog Netlist by @tangxifan in Organize Routing Multiplexer Verilog Netlist #148
Netlist/Module size Reduction for Routing Multiplexers by @tangxifan in Netlist/Module size Reduction for Routing Multiplexers #149
Misc Updates by @tangxifan in Misc Updates #150
Support Delay Customization in OpenFPGA Task Configuration File by @ganeshgore in Support Delay Customization in OpenFPGA Task Configuration File #134
Add pull request template by @tangxifan in Add pull request template #154
Bug fix on the incompatible sphinx bibtex version by @tangxifan in Bug fix on the incompatible sphinx bibtex version #158
Add default pull request template to the right position that Github requires by @tangxifan in Add default pull request template to the right position that Github requires #159
[Git] Add labeler for pull requests by @tangxifan in [Git] Add labeler for pull requests #160
Replace yosys by @sharmaln in Replace yosys #152
Bumping latest updates to yosys submodule by @sharmaln in Bumping latest updates to yosys submodule #162
Dead link patch to fontpage README by @tangxifan in Dead link patch to fontpage README #163
Adding a testcase to run yosys quicklogic flow by @sharmaln in Adding a testcase to run yosys quicklogic flow #156
Support on Using Scan-chain Flip-flop in Configuration Chain by @tangxifan in Support on Using Scan-chain Flip-flop in Configuration Chain #167
Bumping yosys submodule with the latest changes done in yosys repo re… by @sharmaln in Bumping yosys submodule with the latest changes done in yosys repo re… #168
Extended Support on Defining Global Ports from Physical Tile Ports by @tangxifan in Extended Support on Defining Global Ports from Physical Tile Ports #170
Basic Support on Multi-Clock Fabric Netlist Generation and Testbench Generation by @tangxifan in Basic Support on Multi-Clock Fabric Netlist Generation and Testbench Generation #172
Support Multiple Clock Definition in Testbench and SDC Generators by @tangxifan in Support Multiple Clock Definition in Testbench and SDC Generators #173
Support Design Constraints for Repack by @tangxifan in Support Design Constraints for Repack #174
Pin Constraint Support in Testbench Generation by @tangxifan in Pin Constraint Support in Testbench Generation #175
Bumping the latest changes in yosys sub-module related to yosys synth… by @sharmaln in Bumping the latest changes in yosys sub-module related to yosys synth… #177
Add OpenFPGA version display by @tangxifan in Add OpenFPGA version display #182
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches by @tangxifan in Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches #179
Support batch mode when executing OpenFPGA commands by @tangxifan in Support batch mode when executing OpenFPGA commands #184
Documentation Formatting by @tangxifan in Documentation Formatting #176
GitHub action optimizations by @yashton in GitHub action optimizations #164
Typo fix on documentation about option --generate_random_fabric_key by @tangxifan in Typo fix on documentation about option --generate_random_fabric_key #186
Update figures in documentation about OpenFPGA framework by @tangxifan in Update figures in documentation about OpenFPGA framework #189
[Docs] Added CI/CD docs by @ganeshgore in [Docs] Added CI/CD docs #190
Upgrade Python3 to python 3.8 by @ganeshgore in Upgrade Python3 to python 3.8 #191
Removing unused files from the repo by @ganeshgore in Removing unused files from the repo #192
Removing old dockerfile by @ganeshgore in Removing old dockerfile #194
Bumping the latest yosys changes related to soft_adder support by @sharmaln in Bumping the latest yosys changes related to soft_adder support #197
[Bugfix] failing docker build + push on master branch by @ganeshgore in [Bugfix] failing docker build + push on master branch #196
Version Echo of OpenFPGA Shell by @tangxifan in Version Echo of OpenFPGA Shell #199
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases by @AurelienUoU in Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases #200
Bug fix on Docker build and upload on master by @ganeshgore in Bug fix on Docker build and upload on master #202
[CICD] Checking master branch in change_detect by @ganeshgore in [CICD] Checking master branch in change_detect #205
Remove the hard requirement on signal activity file by @tangxifan in Remove the hard requirement on signal activity file #203
[CICD] Added SHA tag to docker build image by @ganeshgore in [CICD] Added SHA tag to docker build image #206
Checking complete flow of build.yml from non master branch by @ganeshgore in Checking complete flow of build.yml from non master branch #207
Bumping up yosys submodule as an option (-verilog) is added to write … by @sharmaln in Bumping up yosys submodule as an option (-verilog) is added to write … #208
Bumping up latest yosys changes related to adder tech mapping by @sharmaln in Bumping up latest yosys changes related to adder tech mapping #213
[Cleanup] Removed deadcode by @ganeshgore in [Cleanup] Removed deadcode #214
Support overloading LUT bitstream from attributes in .eblif file format by @tangxifan in Support overloading LUT bitstream from attributes in .eblif file format #212
Changed readthedocs.io dependencies link by @apond308 in Changed readthedocs.io dependencies link #215
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream by @tangxifan in Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream #217
Add tutorial videos to Documentation by @tangxifan in Add tutorial videos to Documentation #218
Documentation Patches on Supporting PDF builds by @tangxifan in Documentation Patches on Supporting PDF builds #219
Support SVG in Sphinx Latex building by @tangxifan in Support SVG in Sphinx Latex building #220
[Flow] ACE is optional during flow script, only runs when power estimation is on by @ganeshgore in [Flow] ACE is optional during flow script, only runs when power estimation is on #222
[Flow] Support multi-user environment for running task by @ganeshgore in [Flow] Support multi-user environment for running task #221
Bumping up latest checkins to yosys sub-module, related to adder_lut4… by @sharmaln in Bumping up latest checkins to yosys sub-module, related to adder_lut4… #234
[Docs] Added documentation for docker based run and shell shortcuts documentation by @ganeshgore in [Docs] Added documentation for docker based run and shell shortcuts documentation #224
Extended LUT Support: Now accept external LUT netlists with embedded custom logic by @tangxifan in Extended LUT Support: Now accept external LUT netlists with embedded custom logic #231
Reorganize tutorial documentation by @tangxifan in Reorganize tutorial documentation #235
Tpagarani dev by @tpagarani in Tpagarani dev #236
Move quicklogic regresssion tests to a dedicated CI run by @tangxifan in Move quicklogic regresssion tests to a dedicated CI run #237
Move regression test scripts from workflow to openfpga_flow by @tangxifan in Move regression test scripts from workflow to openfpga_flow #238
Standard-cell flow by @nachiket in Standard-cell flow #227
[Bugfix] Docker regression using master regression scripts by @ganeshgore in [Bugfix] Docker regression using master regression scripts #242
Deploy synthesizable verilog test to CI by @tangxifan in Deploy synthesizable verilog test to CI #244
Bug fix for truth table creation for wired LUT created by repacking by @tangxifan in Bug fix for truth table creation for wired LUT created by repacking #243
Adding quicklogic tests and updating the corresponding conf file to r… by @sharmaln in Adding quicklogic tests and updating the corresponding conf file to r… #241
Disabling verilog testbench generation for quicklogic tests by @sharmaln in Disabling verilog testbench generation for quicklogic tests #248
Throw fatal error when the number of configurable region is different between fabric key and architecture definition by @tangxifan in Throw fatal error when the number of configurable region is different between fabric key and architecture definition #245
Reorganize QuickLogic's Regression Tests by @tangxifan in Reorganize QuickLogic's Regression Tests #249
Modifying custom yosys script file name by @sharmaln in Modifying custom yosys script file name #253
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys by @sharmaln in Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys #254
Add QuickLogic LUT adder test case by @tangxifan in Add QuickLogic LUT adder test case #252
Bumping up latest yosys changes to yosys submodule by @sharmaln in Bumping up latest yosys changes to yosys submodule #256
Support `default_nettype in Verilog generator by @tangxifan in Support `default_nettype in Verilog generator #255
[CI/CD] Skipped container login if branch is not master by @ganeshgore in [CI/CD] Skipped container login if branch is not master #260
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically p… by @sharmaln in Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically p… #262
add shift register test case by @tpagarani in add shift register test case #265
update yosys submodule with ff and shift register mapping support for quicklogic architecture by @tpagarani in update yosys submodule with ff and shift register mapping support for quicklogic architecture #263
GSB dump enhancement by @mkurc-ant in GSB dump enhancement #257
[Task/Flow] Extended Yosys support in OpenFPGA task by @ganeshgore in [Task/Flow] Extended Yosys support in OpenFPGA task #266
Name grid module pins in Verilog netlist with architecture port defintion by @tangxifan in Name grid module pins in Verilog netlist with architecture port defintion #270
Yosys heterogeneous block support by @tangxifan in Yosys heterogeneous block support #272
Yosys heterogeneous block support on DSP block by @tangxifan in Yosys heterogeneous block support on DSP block #275
Support Verilog-to-Verification for heterogeneous FPGA by @tangxifan in Support Verilog-to-Verification for heterogeneous FPGA #277
Tutorials by @bbleaptrot in Tutorials #274
Patch the schematic of LUT circuit models to be consistent with netlists by @tangxifan in Patch the schematic of LUT circuit models to be consistent with netlists #271
Tutorials by @bbleaptrot in Tutorials #281
Update README.md by @tangxifan in Update README.md #283
Fabric bitstream writer supports multiple regions by @tangxifan in Fabric bitstream writer supports multiple regions #285
Update generate_fabric and generate_testbench test cases by @tangxifan in Update generate_fabric and generate_testbench test cases #286
Enriched FPGA-SDC regression tests by sweeping time units by @tangxifan in Enriched FPGA-SDC regression tests by sweeping time units #287
[WIP] Add opencore RTLs from IWLS 2005 benchmarks by @tangxifan in [WIP] Add opencore RTLs from IWLS 2005 benchmarks #290
Support DFF with asynchronous reset in tech mapping by @tangxifan in Support DFF with asynchronous reset in tech mapping #291
Verilog testbench generator now accepts pin constraints on non-clock global ports by @tangxifan in Verilog testbench generator now accepts pin constraints on non-clock global ports #292
Enable correct reset stimuli in testbench generators by @tangxifan in Enable correct reset stimuli in testbench generators #293
Tutorials by @bbleaptrot in Tutorials #284
Support customizable default path in bitstream generation for any interconnect inside pb_type by @tangxifan in Support customizable default path in bitstream generation for any interconnect inside pb_type #294
Patches on multi-clock support in repacking stage by @tangxifan in Patches on multi-clock support in repacking stage #295
Unlock flexible FF mapping and enable IWLS'2005 benchmark by @tangxifan in Unlock flexible FF mapping and enable IWLS'2005 benchmark #296
Enable constant net routing for VTR benchmarks by @tangxifan in Enable constant net routing for VTR benchmarks #297
Micro benchmarks addition and testing for FPGAs with DSP blocks by @tangxifan in Micro benchmarks addition and testing for FPGAs with DSP blocks #298
Update pull_request_template.md by @tangxifan in Update pull_request_template.md #302
Update bug_report.md by @tangxifan in Update bug_report.md #301
Updated compile.rst by @hitblunders in Updated compile.rst #299
Update PULL_REQUEST_TEMPLATE.md by @tangxifan in Update PULL_REQUEST_TEMPLATE.md #303
Tileable rr graph by @tangxifan in Tileable rr graph #304
Test addition for FPGA architecture with multi-width DSP blocks by @tangxifan in Test addition for FPGA architecture with multi-width DSP blocks #305
Output I/O mapping information to XML file by @tangxifan in Output I/O mapping information to XML file #307
Micro benchmarks for dual port BRAMs by @tangxifan in Micro benchmarks for dual port BRAMs #309
Introduce Micro benchmark: 1-bit Blinking by @tangxifan in Introduce Micro benchmark: 1-bit Blinking #310
Report bitstream distribution by @tangxifan in Report bitstream distribution #311
Documentation update on example circuit models for data memories by @tangxifan in Documentation update on example circuit models for data memories #314
Patch FPGA-SDC to consider time unit in global port timing constraints by @tangxifan in Patch FPGA-SDC to consider time unit in global port timing constraints #317
Preliminary support on full testbench generator using external bitstream file by @tangxifan in Preliminary support on full testbench generator using external bitstream file #320
Support fast configuration in bitstream writer and full testbench that reads external bitstream file by @tangxifan in Support fast configuration in bitstream writer and full testbench that reads external bitstream file #321
Support frame-based configuration protocol in bitstream writer and full testbench that reads external bitstream file by @tangxifan in Support frame-based configuration protocol in bitstream writer and full testbench that reads external bitstream file #323
Support memory bank configuration protocol in bitstream writer and full testbench that reads external bitstream file by @tangxifan in Support memory bank configuration protocol in bitstream writer and full testbench that reads external bitstream file #324
Support flatten configuration protocol in bitstream writer and full testbench that reads external bitstream file by @tangxifan in Support flatten configuration protocol in bitstream writer and full testbench that reads external bitstream file #325
Create new commands in place of the multi-functional write_verilog_testbench command by @tangxifan in Create new commands in place of the multi-functional write_verilog_testbench command #326
Support default_net_type customization in Verilog testbench generator by @tangxifan in Support default_net_type customization in Verilog testbench generator #328
Adding tutorial video and updating several pages to fix grammar and spelling by @bbleaptrot in Adding tutorial video and updating several pages to fix grammar and spelling #331
Update fix_device_route_chan_width_example_script.openfpga by @tangxifan in Update fix_device_route_chan_width_example_script.openfpga #334
Openfpga flow script outputs detailed error message when task directory is not found by @tangxifan in Openfpga flow script outputs detailed error message when task directory is not found #335
Support benchmarks with same top module names in openfpga flow script by @tangxifan in Support benchmarks with same top module names in openfpga flow script #338
Micro benchmark by @tangxifan in Micro benchmark #339
Write io mapping by @tangxifan in Write io mapping #337
Patch wrong paths in FPGA-SDC by @tangxifan in Patch wrong paths in FPGA-SDC #269
Signal initialization HDL codes will not be outputted unless specified in the command-line option by @tangxifan in Signal initialization HDL codes will not be outputted unless specified in the command-line option #340
Update Simulation Exchangeable Information Writer by @tangxifan in Update Simulation Exchangeable Information Writer #341
New option --embed_bitstream for Preconfigured fabric wrapper in place of --support_icarus_simulator by @tangxifan in New option --embed_bitstream for Preconfigured fabric wrapper in place of --support_icarus_simulator #342
Bug fix in Preconfigured Fabric Wrapper Generator by @tangxifan in Bug fix in Preconfigured Fabric Wrapper Generator #343
Remove the hardcoded factor when computing simulation timing by @tangxifan in Remove the hardcoded factor when computing simulation timing #345
Use force in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL by @tangxifan in Use force in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL #347
Deprecate pre-processing flags define_simulation.v and enable testbench generation without self checking by @tangxifan in Deprecate pre-processing flags define_simulation.v and enable testbench generation without self checking #348
More micro benchmarks on adder by @tangxifan in More micro benchmarks on adder #349
Bug fix on the reset stimuli generator by @tangxifan in Bug fix on the reset stimuli generator #353
added configuration benchmark files by @apond308 in added configuration benchmark files #327
[Flow] Allows benchmark specific Variable declaration by @ganeshgore in [Flow] Allows benchmark specific Variable declaration #354
[WIP] Support custom default value in Pin Constraint File by @tangxifan in [WIP] Support custom default value in Pin Constraint File #356
Testcase for benchmark specific variables by @ganeshgore in Testcase for benchmark specific variables #358
Add Test Cases for the Signal Polarity Support in Pin Constraint Files by @tangxifan in Add Test Cases for the Signal Polarity Support in Pin Constraint Files #359
Accept absolute project paths in the 'run_fpga_task.py' script by @WRansohoff in Accept absolute project paths in the 'run_fpga_task.py' script #366
Update compile.rst by @apond308 in Update compile.rst #363
Tutorials by @bbleaptrot in Tutorials #364
Update fpgaflow_default_tool_path.conf by @foggy-slt in Update fpgaflow_default_tool_path.conf #374
add wget to list of dependencies by @coolbreeze413 in add wget to list of dependencies #385
Typo fixes, detail error message in case of exception and message formatting in scripts by @xtofalex in Typo fixes, detail error message in case of exception and message formatting in scripts #391
Make CI Portable by @ganeshgore in Make CI Portable #392
[Bugfix] CI docker image build by @ganeshgore in [Bugfix] CI docker image build #396
Fixed port names for mult_36x36 by @aram-rs in Fixed port names for mult_36x36 #400
Updated CI documentation by @ganeshgore in Updated CI documentation #397
Use Yosys HQ v0.10 as a submodule by @tangxifan in Use Yosys HQ v0.10 as a submodule #403
Adding Yosys+Verific support. by @aram-rs in Adding Yosys+Verific support. #402
add plugins, set yosys install for plugin by @coolbreeze413 in add plugins, set yosys install for plugin #408
Enable all quicklogic tests by @coolbreeze413 in Enable all quicklogic tests #420
update yosys plugin to latest by @tpagarani in update yosys plugin to latest #422
Address: Compilation fails on Manjaro by @skulis in Address: Compilation fails on Manjaro #425
added in CMakeList.txt to check if yosys binary already exist to avoi… by @nadeemyaseen-rs in added in CMakeList.txt to check if yosys binary already exist to avoi… #426
Updated yosys paths to copy in docker image by @ganeshgore in Updated yosys paths to copy in docker image #430
Update contact.rst by @tangxifan in Update contact.rst #429
Fixed missing yosys share directory by @ganeshgore in Fixed missing yosys share directory #431
re-enable counter_5clock,sdc_controller, lut_adder tests by @coolbreeze413 in re-enable counter_5clock,sdc_controller, lut_adder tests #421
Automatic PR creation for yosys-symbiflow-plugins update by @coolbreeze413 in Automatic PR creation for yosys-symbiflow-plugins update #433
Bump yosys-plugins from e320419 to b7bc5f4 by @dependabot in Bump yosys-plugins from e320419 to b7bc5f4 #434
Bump yosys-plugins from b7bc5f4 to b48dda6 by @dependabot in Bump yosys-plugins from b7bc5f4 to b48dda6 #436
allow bitstream setting on hard blocks by @tpagarani in allow bitstream setting on hard blocks #435
Enable Yosys in dependabot by @tangxifan in Enable Yosys in dependabot #440
Bump yosys-plugins from b48dda6 to 3fb0f3b by @dependabot in Bump yosys-plugins from b48dda6 to 3fb0f3b #441
Now CI tests will cancel previous runs by @tangxifan in Now CI tests will cancel previous runs #439
Bump yosys-plugins from 3fb0f3b to b40f6cd by @dependabot in Bump yosys-plugins from 3fb0f3b to b40f6cd #445
Patch counter by @nadeemyaseen-rs in Patch counter #453
Bump yosys-plugins from b40f6cd to 9ee3057 by @dependabot in Bump yosys-plugins from b40f6cd to 9ee3057 #452
Bump yosys-plugins from 9ee3057 to b79ad0d by @dependabot in Bump yosys-plugins from 9ee3057 to b79ad0d #454
Added Auto PR step by @nadeemyaseen-rs in Added Auto PR step #455
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #457
Bump yosys-plugins from b79ad0d to 91d7db0 by @dependabot in Bump yosys-plugins from b79ad0d to 91d7db0 #458
Add version naming convention to developer guidelines by @tangxifan in Add version naming convention to developer guidelines #459
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #460
🏆 A new Configuration Procotol: QuickLogic Memory Bank by @tangxifan in 🏆 A new Configuration Procotol: QuickLogic Memory Bank #466
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #468
New test case: DSP block with input and output registers by @tangxifan in New test case: DSP block with input and output registers #469
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #472
Bump yosys-plugins from 91d7db0 to 35c6c33 by @dependabot in Bump yosys-plugins from 91d7db0 to 35c6c33 #475
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #478
Bump yosys-plugins from 35c6c33 to 8a23827 by @dependabot in Bump yosys-plugins from 35c6c33 to 8a23827 #479
Bump yosys-plugins from 8a23827 to 2acc97d by @dependabot in Bump yosys-plugins from 8a23827 to 2acc97d #482
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #481
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #484
Bump yosys-plugins from 2acc97d to 12fa74f by @dependabot in Bump yosys-plugins from 2acc97d to 12fa74f #485
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #486
Bump yosys-plugins from 12fa74f to db3a9c7 by @dependabot in Bump yosys-plugins from 12fa74f to db3a9c7 #487
Yosys only support added in OpenFPGA by @awaisabbas-rs in Yosys only support added in OpenFPGA #476
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #490
Read HDL files as a single compilation unit in yosys_vpr flow for Verific mode. by @aram-rs in Read HDL files as a single compilation unit in yosys_vpr flow for Verific mode. #488
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #491
Bump yosys-plugins from db3a9c7 to a081891 by @dependabot in Bump yosys-plugins from db3a9c7 to a081891 #493
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #494
Bump yosys-plugins from a081891 to a97ae02 by @dependabot in Bump yosys-plugins from a081891 to a97ae02 #495
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #496
Bump yosys-plugins from a97ae02 to 7fa69f8 by @dependabot in Bump yosys-plugins from a97ae02 to 7fa69f8 #497
Moved 'verific_' and 'yosys_' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. by @aram-rs in Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. #492
FPGA-Verilog/FPGA-Bitstream/FPGA-SDC commands have a new option --no_time_stamp by @tangxifan in FPGA-Verilog/FPGA-Bitstream/FPGA-SDC commands have a new option --no_time_stamp #499
Patch the errors in basic regression tests due to --no_time_stamp support by @tangxifan in Patch the errors in basic regression tests due to --no_time_stamp support #501
Bump yosys-plugins from 7fa69f8 to eaecd87 by @dependabot in Bump yosys-plugins from 7fa69f8 to eaecd87 #502
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #500
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #504
New option --unique available in command write_gsb_to_xml by @tangxifan in New option --unique available in command write_gsb_to_xml #503
changing condition of bitstream downloading by @eemincetin in changing condition of bitstream downloading #505
Bump yosys-plugins from eaecd87 to 003c697 by @dependabot in Bump yosys-plugins from eaecd87 to 003c697 #506
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #507
[FPGA-Verilog] Now have a new option --use_relative_path by @tangxifan in [FPGA-Verilog] Now have a new option --use_relative_path #509
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #510
Now Verilog Testbench Generator has a new option --use_relative_path by @tangxifan in Now Verilog Testbench Generator has a new option --use_relative_path #511
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #512
Bump yosys-plugins from 003c697 to d7ec931 by @dependabot in Bump yosys-plugins from 003c697 to d7ec931 #513
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #514
Bump yosys-plugins from d7ec931 to f184835 by @dependabot in Bump yosys-plugins from d7ec931 to f184835 #517
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #519
Bump yosys-plugins from f184835 to 8bf72c3 by @dependabot in Bump yosys-plugins from f184835 to 8bf72c3 #520
Bump yosys-plugins from 8bf72c3 to 13520da by @dependabot in Bump yosys-plugins from 8bf72c3 to 13520da #522
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #521
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #524
Now preconfigured top-level module has the same port name as reference benchmarks by @tangxifan in Now preconfigured top-level module has the same port name as reference benchmarks #526
Bump yosys-plugins from 13520da to 3b18b54 by @dependabot in Bump yosys-plugins from 13520da to 3b18b54 #527
Now the shared input ports in top-level testbench has a dedicated postfix (except clock ports) by @tangxifan in Now the shared input ports in top-level testbench has a dedicated postfix (except clock ports) #528
Enable comprehensive tests for counter benchmarks by @tangxifan in Enable comprehensive tests for counter benchmarks #529
Fixed a bug in task run when removing previous runs by @tangxifan in Fixed a bug in task run when removing previous runs #530
Bump yosys-plugins from 3b18b54 to ea7411a by @dependabot in Bump yosys-plugins from 3b18b54 to ea7411a #531
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #534
Add initial conditions to counter benchmarks by @tangxifan in Add initial conditions to counter benchmarks #533
Bump yosys-plugins from ea7411a to 503b979 by @dependabot in Bump yosys-plugins from ea7411a to 503b979 #535
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #536
Bump yosys-plugins from 503b979 to 0fa6d61 by @dependabot in Bump yosys-plugins from 503b979 to 0fa6d61 #537
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #538
Support buses in Verilog testbenches by @tangxifan in Support buses in Verilog testbenches #539
Bus support now support big-endian and little-endian by @tangxifan in Bus support now support big-endian and little-endian #540
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #541
More tests on Bus support: Validate its correctness on Input buses by @tangxifan in More tests on Bus support: Validate its correctness on Input buses #542
Pulling refs/heads/master into master by @github-actions in Pulling refs/heads/master into master #543
[Version] Bump up for release v1.1 by @tangxifan in [Version] Bump up for release v1.1 #544

New Contributors

@skulis made their first contribution in Fix tutorial configuration file #36
@srtemp made their first contribution in Fix GUI support with cmake 3.16 #44
@LNIS-Projects made their first contribution in Update dev to be even with master's documentation update #45
@samycharas made their first contribution in Updated Dockerfile for Ubuntu 18.04 #66
@lukefahr made their first contribution in Edits to enable basic run_fpga_flow.py #100
@olofk made their first contribution in Update README.md #117
@mkurc-ant made their first contribution in Fix for rr graph loading by VPR #130
@ganeshgore made their first contribution in Support Delay Customization in OpenFPGA Task Configuration File #134
@sharmaln made their first contribution in Replace yosys #152
@yashton made their first contribution in GitHub action optimizations #164
@apond308 made their first contribution in Changed readthedocs.io dependencies link #215
@tpagarani made their first contribution in Tpagarani dev #236
@nachiket made their first contribution in Standard-cell flow #227
@bbleaptrot made their first contribution in Tutorials #274
@hitblunders made their first contribution in Updated compile.rst #299
@WRansohoff made their first contribution in Accept absolute project paths in the 'run_fpga_task.py' script #366
@foggy-slt made their first contribution in Update fpgaflow_default_tool_path.conf #374
@coolbreeze413 made their first contribution in add wget to list of dependencies #385
@xtofalex made their first contribution in Typo fixes, detail error message in case of exception and message formatting in scripts #391
@aram-rs made their first contribution in Fixed port names for mult_36x36 #400
@nadeemyaseen-rs made their first contribution in added in CMakeList.txt to check if yosys binary already exist to avoi… #426
@dependabot made their first contribution in Bump yosys-plugins from e320419 to b7bc5f4 #434
@github-actions made their first contribution in Pulling refs/heads/master into master #457
@awaisabbas-rs made their first contribution in Yosys only support added in OpenFPGA #476
@eemincetin made their first contribution in changing condition of bitstream downloading #505

Full Changelog: v0.3-alpha...v1.1.0

This discussion was created from the release V1.1.0.

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