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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
# Start of session at: Mon Jun 15 19:32:04 2020
# Process ID: 9580
# Current directory: C:/Users/kubam/Desktop/PULEEEE/RTC
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14876 C:\Users\kubam\Desktop\PULEEEE\RTC\RTC.xpr
# Log file: C:/Users/kubam/Desktop/PULEEEE/RTC/vivado.log
# Journal file: C:/Users/kubam/Desktop/PULEEEE/RTC\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/kubam/Desktop/PULEEEE/RTC/RTC.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.2/data/ip'.
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/kubam/Desktop/PULEEEE/RTC/RTC.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'RTC_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/kubam/Desktop/PULEEEE/RTC/RTC.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj RTC_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/kubam/Desktop/PULEEEE/RTC/RTC.srcs/sim_1/new/sim.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'RTC_tb'
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/kubam/Desktop/PULEEEE/RTC/RTC.sim/sim_1/behav/xsim'
"xelab -wto 1776f6688bdb4553b946f3ce26b05899 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot RTC_tb_behav xil_defaultlib.RTC_tb -log elaborate.log"
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto 1776f6688bdb4553b946f3ce26b05899 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot RTC_tb_behav xil_defaultlib.RTC_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling architecture rtc_arch of entity xil_defaultlib.RTC [rtc_default]
Compiling architecture behavioral of entity xil_defaultlib.rtc_tb
Built simulation snapshot RTC_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/kubam/Desktop/PULEEEE/RTC/RTC.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "RTC_tb_behav -key {Behavioral:sim_1:Functional:RTC_tb} -tclbatch {RTC_tb.tcl} -view {C:/Users/kubam/Desktop/PULEEEE/RTC/RTC_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.2
Time resolution is 1 ps
open_wave_config C:/Users/kubam/Desktop/PULEEEE/RTC/RTC_tb_behav.wcfg
source RTC_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'RTC_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 822.445 ; gain = 3.727
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Mon Jun 15 19:34:00 2020...