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cubesat_rp2040.kicad_dru
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cubesat_rp2040.kicad_dru
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(version 1)
##### DESIGN RULES #####
##### JLCPCB FAB RULES (OVERRIDES DESIGN RULES WHERE APPLICABLE) #####
(rule "Drill hole diameter"
(severity error)
(constraint hole_size (min 0.15mm) (max 6.30mm)))
(rule "Expensive drill hole diameter"
(severity warning)
(constraint hole_size (min 0.20mm)))
(rule "Via types"
(severity error)
(constraint disallow micro_via buried_via))
(rule "Via pad diameter"
(severity error)
(constraint via_diameter (min 0.25mm)))
(rule "Via annular width"
(severity error)
(condition " A.Type == 'Via' ")
# Via diameter shall be minimum 0.1mm (0.15mm preferred) larger than hole.
(constraint annular_width (min 0.05mm) (opt 0.075mm)))
(rule "NPTH hole diameter"
(severity error)
(condition "A.Pad_Type == 'NPTH, mechanical'")
(constraint hole_size (min 0.50mm)))
(rule "Plated slot"
(condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y")
(constraint hole_size (min 0.50mm)))
(rule "Non-plated slot"
(condition "A.Pad_Type == 'NPTH, mechanical' && A.Hole_Size_X != A.Hole_Size_Y")
(constraint hole_size (min 1.00mm)))
(rule "Via hole-to-hole spacing"
(severity error)
(condition "A.Type == 'Via' && A.Type == B.Type")
(constraint hole_to_hole (min 0.20mm)))
(rule "Pad hole-to-hole spacing"
(severity error)
(condition "A.Type == 'Pad' && A.Type == B.Type")
(constraint hole_to_hole (min 0.45mm)))
#(rule "Castellated hole diameter")
#(rule "Castellated hole board edge spacing")
#(rule "Castellated hole-to-hole spacing")
(rule "Track width"
(severity error)
(constraint track_width (min 0.10mm)))
(rule "Track spacing"
(severity error)
(condition "A.Type == 'Track' && A.Type == B.Type")
(constraint clearance (min 0.10mm)))
(rule "PTH annular width"
(severity error)
(condition "A.Type == 'Pad' && A.isPlated()")
(constraint annular_width (min 0.2mm)))
(rule "NPTH annular width"
(severity error)
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical'")
(constraint annular_width (min 0.45mm)))
(rule "BGA"
(severity error)
(condition "A.Fabrication_Property == 'BGA pad'")
(constraint assertion "A.Size_X >= 0.25mm && A.Position_Y >= 0.25mm"))
(rule "Inner layer via-to-copper clearance"
(severity error)
(layer inner)
(condition "A.Type == 'Via'")
(constraint clearance (min 0.20mm)))
(rule "Pad-to-track clearance"
(severity error)
(condition "A.Type == 'Pad' && B.Type == 'Track'")
(constraint clearance (min 0.10mm)))
(rule "SMD Pad-to-pad clearance, different nets"
(severity error)
(condition "A.Pad_Type == 'SMD' && A.Pad_Type == B.Pad_Type && A.NetName != B.NetName")
(constraint clearance (min 0.10mm)))
(rule "Pad-to-pad clearance, different nets"
(severity error)
(condition "A.Pad_Type == 'Through-hole' && A.Pad_Type == B.Pad_Type && A.NetName != B.NetName")
(constraint clearance (min 0.45mm)))
(rule "Via-to-track clearance"
(condition "A.Type == 'Via' && B.Type == 'Track'")
(constraint clearance (min 0.2mm)))
(rule "PTH-to-track clearance"
(condition "A.Type == 'Pad' && A.isPlated() && B.Type == 'Track'")
(constraint clearance (min 0.275mm)))
(rule "NPTH-to-track clearance"
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && B.Type == 'Track'")
(constraint clearance (min 0.2mm)))
(rule "Copper-to-board edge clearance"
(condition "A.Type == 'Track'")
(constraint edge_clearance (min 0.2mm) (opt 0.4mm)))
(rule "Silkscreen line width"
(layer "*.Silkscreen")
(constraint text_thickness (min 0.153mm))
(constraint text_height (min 1mm)))
(rule "Pad-to-silkscreen clearance"
(layer outer)
(condition "A.Type == 'Pad'")
(constraint silk_clearance (min 0.15mm)))