From 0f4ff9fbde62ebf2b8ef8c09a40fb0326dadbf81 Mon Sep 17 00:00:00 2001
From: mbtaylor1982 <mike@dewberryfields.com>
Date: Wed, 6 Sep 2023 12:14:29 +0100
Subject: [PATCH] setup pytest

---
 .vscode/tasks.json                              |  8 ++++----
 ...fo_3bit_cntr.py => cocotb_fifo_3bit_cntr.py} |  2 +-
 RTL/cocotb/test_counter.py                      | 17 +++++++++++++++++
 makefile                                        |  2 +-
 4 files changed, 23 insertions(+), 6 deletions(-)
 rename RTL/cocotb/{test_fifo_3bit_cntr.py => cocotb_fifo_3bit_cntr.py} (94%)
 create mode 100644 RTL/cocotb/test_counter.py

diff --git a/.vscode/tasks.json b/.vscode/tasks.json
index 723097f..9d08bad 100644
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@@ -24,7 +24,7 @@
                   "severity": 1,
                   "message": 3,
                   "file": 4,
-                  "line": 5                  
+                  "line": 5 
                 }
             },
             "group": {
@@ -35,12 +35,12 @@
         {
             "label": "Run Testbench",
             "type": "shell",
-            "command": "docker run --rm -v ${pwd}:/test -w /test -it mbtaylor1982/cocotb-iverilog:latest ./makefile",
+            "command": "docker run --rm -v ${pwd}:/test -w /test/RTL/cocotb/ -it mbtaylor1982/cocotb-iverilog:latest pytest",//./makefile",
             "detail": "Run Testbench",
             "presentation": {
                 "echo": true,
-                "reveal": "silent",
-                "focus": false,
+                "reveal": "always",
+                "focus": true,
                 "panel": "dedicated",
                 "showReuseMessage": false,
                 "clear": true
diff --git a/RTL/cocotb/test_fifo_3bit_cntr.py b/RTL/cocotb/cocotb_fifo_3bit_cntr.py
similarity index 94%
rename from RTL/cocotb/test_fifo_3bit_cntr.py
rename to RTL/cocotb/cocotb_fifo_3bit_cntr.py
index 5f03686..75d9d6c 100644
--- a/RTL/cocotb/test_fifo_3bit_cntr.py
+++ b/RTL/cocotb/cocotb_fifo_3bit_cntr.py
@@ -36,6 +36,6 @@ async def fifo_3bit_cntr_test(dut):
     
     
     await RisingEdge(dut.CLK)
-    assert dut.COUNT.value == 1, "output COUNT did not return to zero"
+    assert dut.COUNT.value == 0, "output COUNT did not return to zero"
 
     
\ No newline at end of file
diff --git a/RTL/cocotb/test_counter.py b/RTL/cocotb/test_counter.py
new file mode 100644
index 0000000..f65abf0
--- /dev/null
+++ b/RTL/cocotb/test_counter.py
@@ -0,0 +1,17 @@
+from cocotb_test.simulator import run
+import pytest
+import os
+import cocotb
+
+hdl_dir = os.path.dirname(__file__)
+
+def test_ounter():
+    run(
+        toplevel_lang="verilog",
+        verilog_sources=[os.path.join("/test/RTL/FIFO/", "fifo_3bit_cntr.v")],
+        toplevel="fifo_3bit_cntr",            # top level HDL
+        module="cocotb_fifo_3bit_cntr",        # name of cocotb test module
+        python_search=[hdl_dir],
+        timescale="1ns/100ps",
+        force_compile="True"
+    )
\ No newline at end of file
diff --git a/makefile b/makefile
index 55a286a..17f3ce1 100644
--- a/makefile
+++ b/makefile
@@ -6,5 +6,5 @@ PWD=$(shell pwd)
 export PYTHONPATH := $(PWD)/RTL/cocotb:$(PYTHONPATH)
 VERILOG_SOURCES += $(PWD)/RTL/FIFO/fifo_3bit_cntr.v
 TOPLEVEL = fifo_3bit_cntr
-MODULE = test_fifo_3bit_cntr
+MODULE = cocotb_fifo_3bit_cntr
 include $(shell cocotb-config --makefiles)/Makefile.sim