diff --git a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2.xpr b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2.xpr index 02efc4959..de4e1392a 100644 --- a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2.xpr +++ b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2.xpr @@ -182,7 +182,7 @@ - + @@ -217,7 +217,7 @@ - + diff --git a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_aes.xpr b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_aes.xpr index 6db656d08..9fc2bcad5 100644 --- a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_aes.xpr +++ b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_aes.xpr @@ -232,14 +232,6 @@ - - - - - - - - @@ -267,7 +259,7 @@ - + diff --git a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_ecc.xpr b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_ecc.xpr index 84e9c15fe..18edb2f78 100644 --- a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_ecc.xpr +++ b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss2_cw305_ecc.xpr @@ -450,6 +450,7 @@ + - - - - - - - - @@ -502,11 +495,9 @@ - + - - Vivado Synthesis Defaults - + @@ -516,9 +507,7 @@ - - Default settings for Implementation. - + diff --git a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss_aes.xpr b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss_aes.xpr index ec4ed02f4..e53ff54c1 100644 --- a/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss_aes.xpr +++ b/hardware/victims/cw308_ufo_target/xc7a35/vivado/ss_aes.xpr @@ -115,6 +115,13 @@ + + + + + + + @@ -168,30 +175,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -219,7 +202,7 @@ - + @@ -229,7 +212,7 @@ - + @@ -239,9 +222,11 @@ - + - + + Vivado Synthesis Defaults + @@ -287,7 +272,9 @@ - + + Default settings for Implementation. + diff --git a/software/chipwhisperer/capture/scopes/OpenADC.py b/software/chipwhisperer/capture/scopes/OpenADC.py index b7a568524..503a8b621 100644 --- a/software/chipwhisperer/capture/scopes/OpenADC.py +++ b/software/chipwhisperer/capture/scopes/OpenADC.py @@ -697,9 +697,9 @@ def con(self, sn=None, idProduct=None, bitstream=None, force=False, prog_speed=1 self.glitch_mmcm1 = XilinxMMCMDRP(self.glitch_drp1) self.glitch_mmcm2 = XilinxMMCMDRP(self.glitch_drp2) self.la_mmcm = XilinxMMCMDRP(self.la_drp) - self.clock = ChipWhispererHuskyClock.ChipWhispererHuskyClock(self.sc, \ - self._fpga_clk, self.glitch_mmcm1, self.glitch_mmcm2) self.ADS4128 = ADS4128Settings(self.sc) + self.clock = ChipWhispererHuskyClock.ChipWhispererHuskyClock(self.sc, \ + self._fpga_clk, self.glitch_mmcm1, self.glitch_mmcm2, self.ADS4128) self.XADC = XADCSettings(self.sc) self.LEDs = LEDSettings(self.sc) self.LA = LASettings(oaiface=self.sc, mmcm=self.la_mmcm, scope=self) diff --git a/software/chipwhisperer/capture/scopes/cwhardware/ChipWhispererHuskyClock.py b/software/chipwhisperer/capture/scopes/cwhardware/ChipWhispererHuskyClock.py index 8aee18e63..46b016a6c 100644 --- a/software/chipwhisperer/capture/scopes/cwhardware/ChipWhispererHuskyClock.py +++ b/software/chipwhisperer/capture/scopes/cwhardware/ChipWhispererHuskyClock.py @@ -5,6 +5,8 @@ from ....logging import * import numpy as np from .._OpenADCInterface import OpenADCInterface, ClockSettings +from ..cwhardware.ChipWhispererHuskyMisc import ADS4128Settings + import time ADDR_EXTCLK = 38 @@ -778,7 +780,7 @@ def inner(self, *args, **kwargs) : self._adc_error_enabled(True) return inner - def __init__(self, oaiface : OpenADCInterface, fpga_clk_settings : ClockSettings, mmcm1, mmcm2): + def __init__(self, oaiface : OpenADCInterface, fpga_clk_settings : ClockSettings, mmcm1, mmcm2, adc: ADS4128Settings): super().__init__() # cache ADC freq to improve capture speed @@ -787,6 +789,7 @@ def __init__(self, oaiface : OpenADCInterface, fpga_clk_settings : ClockSettings self.oa = oaiface self.naeusb = oaiface.serial self.pll = CDCI6214(self.naeusb, mmcm1, mmcm2) + self.adc = adc self.fpga_clk_settings = fpga_clk_settings self.fpga_clk_settings.freq_ctr_src = "extclk" self.adc_phase = 0 @@ -865,6 +868,16 @@ def clkgen_src(self, clk_src): else: raise ValueError("Invalid src settings! Must be 'internal', 'system', 'extclk' or 'extclk_aux_io', not {}".format(clk_src)) + def _update_adc_speed_mode(self, mul, freq): + """Husky's ADC has a high speed / low speed mode bit. + When the ADC clock is changed, this automatically sets the appropriate + speed mode. + """ + if mul * freq < 80e6: + self.adc.low_speed = True + else: + self.adc.low_speed = False + @property def clkgen_freq(self): """The target clock frequency in Hz. @@ -908,9 +921,9 @@ def clkgen_freq(self, freq): self.pll._fpga_clk_freq = self.fpga_clk_settings.freq_ctr if self.clkgen_src == "test": self.pll._fpga_clk_freq = freq - self.pll.target_freq = freq self.extclk_error = None + self._update_adc_speed_mode(self.adc_mul, freq) @property def adc_mul(self): @@ -935,6 +948,7 @@ def adc_mul(self): def adc_mul(self, mul): self._cached_adc_freq = None self.pll.adc_mul = mul + self._update_adc_speed_mode(mul, self.clkgen_freq) @property def adc_freq(self): diff --git a/tests/test_husky.py b/tests/test_husky.py index 36e9de0c4..331974c35 100644 --- a/tests/test_husky.py +++ b/tests/test_husky.py @@ -92,7 +92,7 @@ def reset_target(): if scope._is_husky_plus: MAXCLOCK = 250e6 OVERCLOCK1 = 255e6 - OVERCLOCK2 = 255e6 + OVERCLOCK2 = 300e6 MAXSAMPLES = 327828 MAXSEGMENTSAMPLES = 295056 else: