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Husky sampling clock phase is not consistent. #490

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jpcrypt opened this issue Jun 3, 2024 · 0 comments
Open

Husky sampling clock phase is not consistent. #490

jpcrypt opened this issue Jun 3, 2024 · 0 comments
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jpcrypt commented Jun 3, 2024

The relative phase between the target clock and the ADC sampling clock phase is not always consistent when scope.clock.adc_mul is changed, or when the frequency of scope.clock.clkgen_src is changed.

Running scope.clock.pll.recal() and re-setting scope.clock.clkgen_src appears to resolve the problem but more testing is needed.
jpcrypt added a commit that referenced this issue Oct 22, 2024
@jpcrypt
Big update to PLL programming.
afc42f0 
Updates all PLL registers, in the prescribed order, whenever any of them
needs to be updated. Towards fixing
#490.

Functional (but not fully tested) for XIN case; not tested at all with
external clock.
@jpcrypt jpcrypt self-assigned this Nov 1, 2024
@jpcrypt jpcrypt added the bug label Nov 1, 2024
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