diff --git a/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst b/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst index c2b5d68ab652..4c6ab4244ed8 100644 --- a/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst +++ b/doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst @@ -379,7 +379,12 @@ Wi-Fi samples Other samples ------------- -|no_changes_yet_note| +* :ref:`coremark_sample` sample: + + * Updated: + + * Configuration for the :ref:`zephyr:nrf54h20dk_nrf54h20` board to support multi-domain logging using the ARM Coresight STM. + * The logging format in the standard logging mode to align it with the format used in the multi-domain logging mode. Drivers ======= diff --git a/samples/benchmarks/coremark/Kconfig.sysbuild b/samples/benchmarks/coremark/Kconfig.sysbuild index fd8ca4554861..fb277c0e7d89 100644 --- a/samples/benchmarks/coremark/Kconfig.sysbuild +++ b/samples/benchmarks/coremark/Kconfig.sysbuild @@ -14,12 +14,4 @@ config APP_CPUNET_RUN config APP_CPUPPR_RUN bool "Run the CoreMark benchmark on the PPR core" depends on SUPPORT_PPRCORE - depends on !BOARD_NRF54H20DK || !APP_CPUNET_RUN - help - Due to the limited number of UART ports on the nRF54H20 DK, you can run the CoreMark - benchmark only on two cores at a time; application core and either radio core or PPR - core. - - PPR code is run from RAM. You must use the "nordic-ppr" snippet for the application - core to be able to boot the PPR core. You need to provide the "coremark_SNIPPET=nordic" - build argument. + default y diff --git a/samples/benchmarks/coremark/README.rst b/samples/benchmarks/coremark/README.rst index 8d5a0e169515..0ec8ae186d8b 100644 --- a/samples/benchmarks/coremark/README.rst +++ b/samples/benchmarks/coremark/README.rst @@ -28,6 +28,44 @@ For the button assignment, see the :ref:`coremark_user_interface` section. When the benchmark has completed, you can press the same button to restart it. If you want to run the sample upon startup, enable the :ref:`CONFIG_APP_MODE_FLASH_AND_RUN ` Kconfig option. +Logging +======= + +The logging mode depends on the chosen board target. +The sample supports two distinct modes that are described in the following subsections. + +Standard logging +---------------- + +This logging mode is used by most board targets. +Each core running the CoreMark benchmark has an independent UART instance that is used for logging. + +To see all logging information for the multi-core board targets, you must open a terminal for each active core. + +The sample configuration sets up the following board targets for standard logging: + +* ``nrf52840dk/nrf52840`` +* ``nrf52833dk/nrf52833`` +* ``nrf52dk/nrf52832`` +* ``nrf5340dk/nrf5340/cpuapp`` +* ``nrf54l15dk/nrf54l15/cpuapp`` + +Multi-domain logging +-------------------- + +This logging mode is used by multi-core board targets that support logging using the ARM Coresight STM. +Each core running the CoreMark benchmark writes its logging information to its own set of STM Extended Stimulus Port (STMESP). +One core in the system is designated to collect all logs and to send them to the chosen UART instance. +The sample supports multi-domain logging in the standalone mode. +See :ref:`zephyr:logging_cs_stm` for more details. + +To see all logging information in this logging mode, it is enough to open one terminal. +When the core used for sending the logs to UART is running the CoreMark benchmark, the logging activity is blocked until the benchmark has completed. + +The sample configuration sets up the following board targets for multi-domain logging: + +* ``nrf54h20dk/nrf54h20/cpuapp`` + .. _coremark_user_interface: User interface @@ -146,13 +184,6 @@ SB_CONFIG_APP_CPUPPR_RUN - Enable execution for the PPR core .. note:: PPR code is run from RAM. - You must use the ``nordic-ppr`` snippet for the application core to be able to boot the PPR core. - Use the build argument ``coremark_SNIPPET=nordic-ppr``. - To build the sample with the execution for the PPR core enabled, run the following command: - - .. code-block:: console - - west build -b nrf54h20dk/nrf54h20/cpuapp -- -DSB_CONFIG_APP_CPUNET_RUN=n -DSB_CONFIG_APP_CPUPPR_RUN=y -Dcoremark_SNIPPET=nordic-ppr Building and running ******************** @@ -176,6 +207,11 @@ Testing After programming the sample to your development kit, complete the following steps to test it: 1. |connect_terminal| + + .. note:: + To see all logging information for the multi-core board targets and the standard logging mode, you must open a terminal for each active core. + The ``nrf5340dk/nrf5340/cpuapp`` is an example of such board target. + #. Reset your development kit. #. To start the test, press the button assigned to the respective core. For button assignment, refer to the :ref:`coremark_user_interface` section. @@ -190,29 +226,116 @@ After programming the sample to your development kit, complete the following ste #. Wait for the console output for all tested cores. The results will be similar to the following example: - .. code-block:: console - - *** Booting nRF Connect SDK v2.7.0-b6081ebcf502 *** - *** Using Zephyr OS v3.6.99-100befc70c74 *** - I: CoreMark sample for nrf52840dk/nrf52840 - I: Press Push button switch 0 to start the test ... - I: Push button switch 0 pressed! - I: CoreMark started! CPU FREQ: 64000000 Hz, threads: 1, data size: 2000; iterations: 2000 - - 2K performance run parameters for coremark. - CoreMark Size : 666 - Total ticks : 400968 - Total time (secs): 12.236000 - Iterations/Sec : 163.452109 - Iterations : 2000 - Compiler version : GCC12.2.0 - Compiler flags : -O3 + see compiler flags added by Zephyr - Memory location : STACK - seedcrc : 0xe9f5 - [0]crclist : 0xe714 - [0]crcmatrix : 0x1fd7 - [0]crcstate : 0x8e3a - [0]crcfinal : 0x4983 - Correct operation validated. See README.md for run and reporting rules. - CoreMark 1.0 : 163.452109 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK - I: CoreMark finished! Push Push button switch 0 to restart ... + .. tabs:: + + .. group-tab:: Standard logging + + .. code-block:: console + + *** Booting nRF Connect SDK v2.8.99-bd4a30a3a758 *** + *** Using Zephyr OS v3.7.99-02718211f9a9 *** + [00:00:00.261,383] app: Standard logging mode + + [00:00:00.266,967] app: CoreMark sample for nrf52840dk/nrf52840 + [00:00:00.274,139] app: Press Push button switch 0 to start the test ... + + [00:00:01.267,608] app: Push button switch 0 pressed! + [00:00:01.273,864] app: CoreMark started! CPU FREQ: 64000000 Hz, threads: 1, data size: 2000; iterations: 2000 + + 2K performance run parameters for coremark. + CoreMark Size : 666 + Total ticks : 401215 + Total time (secs): 12.244000 + Iterations/Sec : 163.345312 + Iterations : 2000 + Compiler version : GCC12.2.0 + Compiler flags : -O3 + see compiler flags added by Zephyr + Memory location : STACK + seedcrc : 0xe9f5 + [0]crclist : 0xe714 + [0]crcmatrix : 0x1fd7 + [0]crcstate : 0x8e3a + [0]crcfinal : 0x4983 + Correct operation validated. See README.md for run and reporting rules. + CoreMark 1.0 : 163.345312 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK + [00:00:13.597,778] app: CoreMark finished! Press Push button switch 0 to restart ... + + .. group-tab:: Multi-domain logging + + .. code-block:: console + + *** Booting nRF Connect SDK v2.8.99-f9add8e14565 *** + *** Using Zephyr OS v3.7.99-02718211f9a9 *** + [00:00:00.208,166] app/app: Multi-domain logging mode + [00:00:00.208,168] app/app: This core is used to output logs from all cores to terminal over UART + + [00:00:00.208,441] ppr/app: CoreMark sample for nrf54h20dk@0.9.0/nrf54h20/cpuppr + [00:00:00.208,496] ppr/app: CoreMark started! CPU FREQ: 16000000 Hz, threads: 1, data size: 2000; iterations: 500 + + [00:00:01.186,256] rad/app: CoreMark sample for nrf54h20dk@0.9.0/nrf54h20/cpurad + [00:00:01.186,305] rad/app: Press Push button 1 to start the test ... + + [00:00:01.285,614] app/app: CoreMark sample for nrf54h20dk@0.9.0/nrf54h20/cpuapp + [00:00:01.285,654] app/app: Press Push button 0 to start the test ... + + [00:00:04.984,744] app/app: Push button 0 pressed! + [00:00:04.984,753] app/app: CoreMark started! CPU FREQ: 320000000 Hz, threads: 1, data size: 2000; iterations: 10000 + + [00:00:04.984,755] app/app: Logging is blocked for all cores until this core finishes the CoreMark benchmark + + [00:00:05.714,470] rad/app: Push button 1 pressed! + [00:00:05.714,486] rad/app: CoreMark started! CPU FREQ: 256000000 Hz, threads: 1, data size: 2000; iterations: 10000 + + 2K performance run parameters for coremark. + CoreMark Size : 666 + Total ticks : 13471150 + Total time (secs): 13.471000 + Iterations/Sec : 37.116769 + Iterations : 500 + Compiler version : GCC12.2.0 + Compiler flags : -O3 + see compiler flags added by Zephyr + Memory location : STACK + seedcrc : 0xe9f5 + [0]crclist : 0xe714 + [0]crcmatrix : 0x1fd7 + [0]crcstate : 0x8e3a + [0]crcfinal : 0xa14c + Correct operation validated. See README.md for run and reporting rules. + CoreMark 1.0 : 37.116769 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK + [00:00:13.595,072] ppr/app: CoreMark finished! Press the reset button to restart... + + 2K performance run parameters for coremark. + CoreMark Size : 666 + Total ticks : 11436744 + Total time (secs): 11.436000 + Iterations/Sec : 874.431619 + Iterations : 10000 + Compiler version : GCC12.2.0 + Compiler flags : -O3 + see compiler flags added by Zephyr + Memory location : STACK + seedcrc : 0xe9f5 + [0]crclist : 0xe714 + [0]crcmatrix : 0x1fd7 + [0]crcstate : 0x8e3a + [0]crcfinal : 0x988c + Correct operation validated. See README.md for run and reporting rules. + CoreMark 1.0 : 874.431619 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK + [00:00:16.446,916] app/app: CoreMark finished! Press Push button 0 to restart ... + + 2K performance run parameters for coremark. + CoreMark Size : 666 + Total ticks : 14290211 + Total time (secs): 14.290000 + Iterations/Sec : 699.790063 + Iterations : 10000 + Compiler version : GCC12.2.0 + Compiler flags : -O3 + see compiler flags added by Zephyr + Memory location : STACK + seedcrc : 0xe9f5 + [0]crclist : 0xe714 + [0]crcmatrix : 0x1fd7 + [0]crcstate : 0x8e3a + [0]crcfinal : 0x988c + Correct operation validated. See README.md for run and reporting rules. + CoreMark 1.0 : 699.790063 / GCC12.2.0 -O3 + see compiler flags added by Zephyr / STACK + [00:00:19.911,390] rad/app: CoreMark finished! Press Push button 1 to restart ... diff --git a/samples/benchmarks/coremark/boards/nrf52833dk_nrf52833.conf b/samples/benchmarks/coremark/boards/nrf52833dk_nrf52833.conf new file mode 100644 index 000000000000..4d3fb68bcada --- /dev/null +++ b/samples/benchmarks/coremark/boards/nrf52833dk_nrf52833.conf @@ -0,0 +1,6 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/benchmarks/coremark/boards/nrf52840dk_nrf52840.conf b/samples/benchmarks/coremark/boards/nrf52840dk_nrf52840.conf new file mode 100644 index 000000000000..4d3fb68bcada --- /dev/null +++ b/samples/benchmarks/coremark/boards/nrf52840dk_nrf52840.conf @@ -0,0 +1,6 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/benchmarks/coremark/boards/nrf52dk_nrf52832.conf b/samples/benchmarks/coremark/boards/nrf52dk_nrf52832.conf new file mode 100644 index 000000000000..4d3fb68bcada --- /dev/null +++ b/samples/benchmarks/coremark/boards/nrf52dk_nrf52832.conf @@ -0,0 +1,6 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpuapp.conf index af4820e985af..2b11d0b8458b 100644 --- a/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpuapp.conf +++ b/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpuapp.conf @@ -4,3 +4,5 @@ # SPDX-License-Identifier: LicenseRef-Nordic-5-Clause CONFIG_SOC_NRF53_CPUNET_ENABLE=y + +CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpunet.conf b/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpunet.conf new file mode 100644 index 000000000000..4d3fb68bcada --- /dev/null +++ b/samples/benchmarks/coremark/boards/nrf5340dk_nrf5340_cpunet.conf @@ -0,0 +1,6 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.conf b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.conf index e171b0644802..c999f4db93db 100644 --- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.conf +++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.conf @@ -4,3 +4,12 @@ # SPDX-License-Identifier: LicenseRef-Nordic-5-Clause CONFIG_COREMARK_ITERATIONS=10000 + +# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet. +CONFIG_TEST_LOGGING_DEFAULTS=n +CONFIG_LOG_FRONTEND=y +CONFIG_LOG_FRONTEND_ONLY=y +CONFIG_LOG_FRONTEND_STMESP=y +CONFIG_LOG_FRONTEND_STMESP_FSC=y + +CONFIG_UART_ASYNC_API=y diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay index bb3511cfc403..4c23931e04f1 100644 --- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay +++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuapp.overlay @@ -29,3 +29,23 @@ owned-channels = <7>; status = "okay"; }; + +/* DTS nodes required to run the cpuppr target. */ +&cpuppr_vpr { + status = "okay"; +}; + +&cpuppr_ram3x_region { + status = "okay"; +}; + +/* DTS nodes required for the STM standalone logging, imported from the nordic-log-stm snippet. */ +&tbm { + status = "okay"; +}; + +&tddconf { + status = "okay"; + etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE | NRF_TDDCONF_SOURCE_STMPPR)>; + portconfig = <0>; +}; diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.conf b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.conf index c090057e78c8..b4ca5a3ed134 100644 --- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.conf +++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.conf @@ -4,3 +4,17 @@ # SPDX-License-Identifier: LicenseRef-Nordic-5-Clause CONFIG_COREMARK_ITERATIONS=500 + +# Disable the UART console Kconfig to make Kconfig configuration with the DTS configuration. +CONFIG_UART_CONSOLE=n + +# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet. +CONFIG_TEST_LOGGING_DEFAULTS=n +CONFIG_LOG_FRONTEND=y +CONFIG_LOG_FRONTEND_ONLY=y +CONFIG_LOG_FRONTEND_STMESP=y +CONFIG_LOG_FRONTEND_STMESP_FSC=y + +# Disable the NCS boot banner - the application core is responsible for printing the boot banner. +CONFIG_NCS_BOOT_BANNER=n +CONFIG_BOOT_BANNER=n diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.overlay index 6901e9f5cefb..cabad3b9d342 100644 --- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.overlay +++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpuppr.overlay @@ -4,4 +4,10 @@ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause */ -/* Intentionally left empty to overwrite default app.overlay. */ +/* Disable the default UART node for the pepper core, as logs are forwarded + * with STM and the application core UART. This setting also prevents access + * issues to the same UART instance from two or more different cores. + */ +&uart135 { + status = "disabled"; +}; diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.conf b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.conf index e171b0644802..ab3cf9ddbfa1 100644 --- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.conf +++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.conf @@ -4,3 +4,17 @@ # SPDX-License-Identifier: LicenseRef-Nordic-5-Clause CONFIG_COREMARK_ITERATIONS=10000 + +# Disable the UART console Kconfig to make Kconfig configuration with the DTS configuration. +CONFIG_UART_CONSOLE=n + +# Kconfigs required for the STM standalone logging, imported from the nordic-log-stm snippet. +CONFIG_TEST_LOGGING_DEFAULTS=n +CONFIG_LOG_FRONTEND=y +CONFIG_LOG_FRONTEND_ONLY=y +CONFIG_LOG_FRONTEND_STMESP=y +CONFIG_LOG_FRONTEND_STMESP_FSC=y + +# Disable the NCS boot banner - the application core is responsible for printing the boot banner. +CONFIG_NCS_BOOT_BANNER=n +CONFIG_BOOT_BANNER=n diff --git a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.overlay index eeb0d38c9f0f..9d296906f576 100644 --- a/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.overlay +++ b/samples/benchmarks/coremark/boards/nrf54h20dk_nrf54h20_cpurad.overlay @@ -40,3 +40,18 @@ owned-channels = <6>; status = "okay"; }; + +/* Disable the default UART node for the radio core, as logs are forwarded + * with STM and the application core UART. This setting also prevents access + * issues to the same UART instance from two or more different cores. + */ +&uart135 { + status = "disabled"; +}; + +/* DTS nodes required for the STM standalone logging, imported from the nordic-log-stm snippet. */ +&tddconf { + status = "okay"; + etrsources = <(NRF_TDDCONF_SOURCE_STMMAINCORE)>; + portconfig = <0>; +}; diff --git a/samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.conf b/samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.conf index 304e69ba4645..67f26401cef0 100644 --- a/samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.conf +++ b/samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.conf @@ -4,3 +4,5 @@ # SPDX-License-Identifier: LicenseRef-Nordic-5-Clause CONFIG_COREMARK_ITERATIONS=4000 + +CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/benchmarks/coremark/prj.conf b/samples/benchmarks/coremark/prj.conf index e4e18eef6cad..fade2c90af10 100644 --- a/samples/benchmarks/coremark/prj.conf +++ b/samples/benchmarks/coremark/prj.conf @@ -14,7 +14,6 @@ CONFIG_COMPILER_OPT="-O3" # Config results output CONFIG_LOG=y -CONFIG_LOG_MODE_MINIMAL=y CONFIG_LOG_DEFAULT_LEVEL=0 CONFIG_CBPRINTF_FP_SUPPORT=y diff --git a/samples/benchmarks/coremark/prj_multiple_threads.conf b/samples/benchmarks/coremark/prj_multiple_threads.conf index fa6af1debbf2..3951316f0064 100644 --- a/samples/benchmarks/coremark/prj_multiple_threads.conf +++ b/samples/benchmarks/coremark/prj_multiple_threads.conf @@ -8,4 +8,4 @@ CONFIG_COREMARK_THREADS_NUMBER=4 # Increse if number of threads increases. CONFIG_TIMESLICE_SIZE=10 -CONFIG_MAIN_STACK_SIZE=14240 +CONFIG_MAIN_STACK_SIZE=10240 diff --git a/samples/benchmarks/coremark/sample.yaml b/samples/benchmarks/coremark/sample.yaml index 1c696d338d52..56079b907929 100644 --- a/samples/benchmarks/coremark/sample.yaml +++ b/samples/benchmarks/coremark/sample.yaml @@ -81,15 +81,3 @@ tests: - nrf54h20dk/nrf54h20/cpuapp tags: ci_build sysbuild ci_samples_benchmarks extra_args: EXTRA_CONF_FILE="prj_multiple_threads.conf" - sample.benchmark.coremark_ppr: - sysbuild: true - build_only: true - platform_allow: - - nrf54h20dk/nrf54h20/cpuapp - integration_platforms: - - nrf54h20dk/nrf54h20/cpuapp - tags: ci_build sysbuild ci_samples_benchmarks - extra_args: - SB_CONFIG_APP_CPUNET_RUN=n - SB_CONFIG_APP_CPUPPR_RUN=y - coremark_SNIPPET=nordic-ppr diff --git a/samples/benchmarks/coremark/src/main.c b/samples/benchmarks/coremark/src/main.c index d51b5640376d..3663de8a4cbd 100644 --- a/samples/benchmarks/coremark/src/main.c +++ b/samples/benchmarks/coremark/src/main.c @@ -4,9 +4,11 @@ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause */ +#include #include #include #include +#include #include #include "coremark_zephyr.h" @@ -49,10 +51,63 @@ static const struct gpio_dt_spec status_led; static K_SEM_DEFINE(start_coremark, 0, 1); static atomic_t coremark_in_progress; -/* Enforce synchronous logging as the sample doesn't flush logs. */ -BUILD_ASSERT(IS_ENABLED(CONFIG_LOG_MODE_MINIMAL) || IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE), - "Logs should be processed synchronously to avoid negative impact on the " - "benchamrk performance"); +static void logging_mode_multi_domain_blocked_state_indicate(void) +{ + if (!IS_ENABLED(CONFIG_NRF_ETR)) { + return; + } + + LOG_INF("Logging is blocked for all cores until this core finishes the CoreMark " + "benchmark\n"); + + /* The wait time is necessary to include the log in the ETR flush operation. The logging + * frontend submits the log to the STM port (STMESP), which STM processes and directs the + * generated logging stream to the STM sink - ETR. The log should be available in the ETR + * peripheral after the sleep operation. + */ + k_sleep(K_MSEC(100)); + + /* Flush logs from the ETR and direct them to UART. */ + nrf_etr_flush(); +} + +static int logging_mode_indicate(void) +{ + /* Enforce synchronous logging as the sample doesn't flush logs. */ + BUILD_ASSERT(IS_ENABLED(CONFIG_LOG_MODE_MINIMAL) || + IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE) || + IS_ENABLED(CONFIG_LOG_FRONTEND_ONLY), + "Logs should be processed synchronously to avoid negative impact on the " + "benchamrk performance"); + + /* Standard logging mode */ + if (IS_ENABLED(CONFIG_LOG_MODE_MINIMAL) || IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE)) { + LOG_INF("Standard logging mode\n"); + + return 0; + } + + /* Multi-domain logging mode */ + if (IS_ENABLED(CONFIG_LOG_FRONTEND_ONLY) || IS_ENABLED(CONFIG_LOG_FRONTEND_STMESP)) { + /* Only the core responsible for moving the logs from the STM sink to UART + * indicates the logging mode. + */ + if (IS_ENABLED(CONFIG_NRF_ETR)) { + LOG_INF("Multi-domain logging mode"); + LOG_INF("This core is used to output logs from all cores to terminal " + "over UART\n"); + } + + return 0; + } + + /* This part should never be executed. */ + k_panic(); + + return 0; +} + +SYS_INIT(logging_mode_indicate, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY); static void button_pressed(const struct device *dev, struct gpio_callback *cb, uint32_t pins) { @@ -130,7 +185,7 @@ int main(void) k_panic(); } - LOG_INF("Press %s to start the test ...", BUTTON_LABEL); + LOG_INF("Press %s to start the test ...\n", BUTTON_LABEL); } while (true) { @@ -142,12 +197,16 @@ int main(void) CONFIG_COREMARK_DATA_SIZE, CONFIG_COREMARK_ITERATIONS); + logging_mode_multi_domain_blocked_state_indicate(); + LED_ON(); coremark_run(); LED_OFF(); - if (!IS_ENABLED(CONFIG_APP_MODE_FLASH_AND_RUN)) { - LOG_INF("CoreMark finished! Push %s to restart ...\n", BUTTON_LABEL); + if (IS_ENABLED(CONFIG_APP_MODE_FLASH_AND_RUN)) { + LOG_INF("CoreMark finished! Press the reset button to restart...\n"); + } else { + LOG_INF("CoreMark finished! Press %s to restart ...\n", BUTTON_LABEL); } (void)atomic_set(&coremark_in_progress, false);