The project so far has focused on generating a PRN generator and the carrier signal using one FPGA, and recording the radiofrequency signal for post-processing with an Ettus Research B210 SDR transceiver. The B210 FPGA however still has plenty of space left, so that the PRN generation gateware can be merged with the datastream handling functions provided by Ettus Research. Since the two functions are running independently, the Amaranth generate Verilog code is merged next to the original B210 software and the resulting program is synthesized to produce a single bitstream.
Putting the resulting usrp_b210_fpga.bin in /usr/share/uhd/images/
will tell UHD to configure the B210 FPGA with the updated bitstream which
is generated according to the following procedure.
A patch is provided to modify B210 firmware:
git clone https://github.com/EttusResearch/uhd.git
cd uhd
git checkout VERSION -b VERSION
patch -p1 < /somewhere/amaranth_twstft/0001-VERSION-b200-add-pps_gen-stream-tag-and-twstft-amaranth.patch
VERSION may be v4.1.0.5, v4.3.0.0 or v4.4.0.0.
cd fpga/usrp3/top/b200
make B210 [TAPS=XXX] [NOISELEN=YYY] [BITLEN=ZZZ] [INVERT_FIRST_CODE=1]
Note: TAPS NOISELEN and BITLEN are used to select a specific taps and to
configure PRN length before reinit. INVERT_FIRST_CODE is used to apply a xor
for the first code after PPS rise.
The input and output signals are available on the GPIO header J504 next to the FPGA:
- PPS in to be connected to the corresponding SMA
- fp_gpio 1: enable
- fp_gpio 3: output signal
- fp_gpio 5: pps out
- fp_gpio 7: switch BPSK/QPSK