From 916e40a575a5c71a383b076724ed5238364fd9a6 Mon Sep 17 00:00:00 2001 From: Gabor Leitner Date: Thu, 24 Dec 2020 02:04:17 +0100 Subject: [PATCH 1/7] Fix product_line and variant --- boards/nucleo_g431kb.json | 4 ++-- examples/arduino-blink/platformio.ini | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/boards/nucleo_g431kb.json b/boards/nucleo_g431kb.json index b80628b1..a00fd6bb 100644 --- a/boards/nucleo_g431kb.json +++ b/boards/nucleo_g431kb.json @@ -5,8 +5,8 @@ "extra_flags": "-DSTM32G4xx -DSTM32G431xx", "f_cpu": "170000000L", "mcu": "stm32g431kbt6", - "product_line": "STM32F407xx", - "variant": "STM32G431xx" + "product_line": "STM32G431xx", + "variant": "NUCLEO_G431KB" }, "connectivity": [ "can" diff --git a/examples/arduino-blink/platformio.ini b/examples/arduino-blink/platformio.ini index b5637510..cfb5b9d2 100644 --- a/examples/arduino-blink/platformio.ini +++ b/examples/arduino-blink/platformio.ini @@ -44,6 +44,12 @@ board = nucleo_h743zi [env:nucleo_g071rb] board = nucleo_g071rb +[env:nucleo_g431kb] +board = nucleo_g431kb + +[env:nucleo_g431rb] +board = nucleo_g431rb + [env:robotdyn_blackpill_f303cc] board = robotdyn_blackpill_f303cc From 5183d2089bfbd85d34a962f8dfd4b714653549eb Mon Sep 17 00:00:00 2001 From: valeros Date: Fri, 25 Dec 2020 18:32:41 +0200 Subject: [PATCH 2/7] Update mbed packages --- .../mbed-blink/platformio.ini | 1 - .../mbed-custom-target/platformio.ini | 4 +- .../mbed-events/platformio.ini | 2 +- .../mbed-filesystem/platformio.ini | 2 +- .../mbed-rtos-ethernet-tls/platformio.ini | 2 +- .../mbed-rtos-mesh-minimal/platformio.ini | 2 +- .../mbed-rtos/platformio.ini | 2 +- .../mbed-serial/platformio.ini | 2 +- .../mbed-rtos-custom-target/platformio.ini | 2 +- .../src/TARGET_STM32L452xE/CMakeLists.txt | 27 + .../TARGET_NUCLEO_L452RE_P/CMakeLists.txt | 12 + .../TARGET_NUCLEO_L452RE_P/PeripheralNames.h | 95 - .../TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S | 24 +- .../stm32l452xe.ld} | 6 +- .../{device => }/cmsis_nvic.h | 0 .../TARGET_STM32L452xE/device/stm32l452xx.h | 16062 ---------------- .../device/us_ticker_data.h | 45 - .../src/TARGET_STM32L452xE/objects.h | 67 - .../system_clock.c | 86 +- platform.json | 2 +- platform.py | 2 +- 21 files changed, 83 insertions(+), 16364 deletions(-) create mode 100644 examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/CMakeLists.txt create mode 100644 examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/CMakeLists.txt delete mode 100644 examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralNames.h rename examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/{device => }/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S (94%) rename examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/{device/TOOLCHAIN_GCC_ARM/STM32L452XX.ld => TOOLCHAIN_GCC_ARM/stm32l452xe.ld} (97%) rename examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/{device => }/cmsis_nvic.h (100%) delete mode 100644 examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/stm32l452xx.h delete mode 100644 examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/us_ticker_data.h delete mode 100644 examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/objects.h rename examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/{TARGET_NUCLEO_L452RE_P => }/system_clock.c (80%) diff --git a/examples/mbed-legacy-examples/mbed-blink/platformio.ini b/examples/mbed-legacy-examples/mbed-blink/platformio.ini index 69c30e4a..f086b12e 100644 --- a/examples/mbed-legacy-examples/mbed-blink/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-blink/platformio.ini @@ -16,4 +16,3 @@ board = disco_f100rb platform = ststm32 framework = mbed board = nucleo_l053r8 - diff --git a/examples/mbed-legacy-examples/mbed-custom-target/platformio.ini b/examples/mbed-legacy-examples/mbed-custom-target/platformio.ini index 1843ecdb..c38bdb7c 100644 --- a/examples/mbed-legacy-examples/mbed-custom-target/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-custom-target/platformio.ini @@ -14,9 +14,9 @@ platform = ststm32 framework = mbed board = custom_nucleo_l452re_mbed board_build.mbed.ldscript = $PROJECTSRC_DIR/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/STM32L452XX.ld -build_flags = +build_flags = -I$PROJECTSRC_DIR/TARGET_STM32L452xE -I$PROJECTSRC_DIR/TARGET_STM32L452xE/device -I$PROJECTSRC_DIR/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE platform_packages = - framework-mbed @ ~6.51504.0 \ No newline at end of file + framework-mbed @ ~6.51506.0 diff --git a/examples/mbed-legacy-examples/mbed-events/platformio.ini b/examples/mbed-legacy-examples/mbed-events/platformio.ini index 67073a6a..57f0415d 100644 --- a/examples/mbed-legacy-examples/mbed-events/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-events/platformio.ini @@ -21,4 +21,4 @@ framework = mbed board = nucleo_f767zi build_flags = -DPIO_FRAMEWORK_MBED_RTOS_PRESENT platform_packages = - framework-mbed @ ~6.51504.0 + framework-mbed @ ~6.51506.0 diff --git a/examples/mbed-legacy-examples/mbed-filesystem/platformio.ini b/examples/mbed-legacy-examples/mbed-filesystem/platformio.ini index 98d47d4f..93b052b9 100644 --- a/examples/mbed-legacy-examples/mbed-filesystem/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-filesystem/platformio.ini @@ -13,4 +13,4 @@ framework = mbed board = nucleo_f767zi build_flags = -DPIO_FRAMEWORK_MBED_RTOS_PRESENT platform_packages = - framework-mbed @ ~6.51504.0 + framework-mbed @ ~6.51506.0 diff --git a/examples/mbed-legacy-examples/mbed-rtos-ethernet-tls/platformio.ini b/examples/mbed-legacy-examples/mbed-rtos-ethernet-tls/platformio.ini index ce31dc96..93b052b9 100644 --- a/examples/mbed-legacy-examples/mbed-rtos-ethernet-tls/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-rtos-ethernet-tls/platformio.ini @@ -13,4 +13,4 @@ framework = mbed board = nucleo_f767zi build_flags = -DPIO_FRAMEWORK_MBED_RTOS_PRESENT platform_packages = - framework-mbed @ ~6.51504.0 \ No newline at end of file + framework-mbed @ ~6.51506.0 diff --git a/examples/mbed-legacy-examples/mbed-rtos-mesh-minimal/platformio.ini b/examples/mbed-legacy-examples/mbed-rtos-mesh-minimal/platformio.ini index 09916b48..38f7a2bc 100644 --- a/examples/mbed-legacy-examples/mbed-rtos-mesh-minimal/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-rtos-mesh-minimal/platformio.ini @@ -13,4 +13,4 @@ framework = mbed board = nucleo_f411re build_flags = -DPIO_FRAMEWORK_MBED_RTOS_PRESENT platform_packages = - framework-mbed @ ~6.51504.0 + framework-mbed @ ~6.51506.0 diff --git a/examples/mbed-legacy-examples/mbed-rtos/platformio.ini b/examples/mbed-legacy-examples/mbed-rtos/platformio.ini index 602741a3..aa997a9a 100644 --- a/examples/mbed-legacy-examples/mbed-rtos/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-rtos/platformio.ini @@ -13,7 +13,7 @@ framework = mbed board = nucleo_f207zg build_flags = -DPIO_FRAMEWORK_MBED_RTOS_PRESENT platform_packages = - framework-mbed @ ~6.51504.0 + framework-mbed @ ~6.51506.0 [env:disco_f303vc] platform = ststm32 diff --git a/examples/mbed-legacy-examples/mbed-serial/platformio.ini b/examples/mbed-legacy-examples/mbed-serial/platformio.ini index 76d76df9..62a819ca 100644 --- a/examples/mbed-legacy-examples/mbed-serial/platformio.ini +++ b/examples/mbed-legacy-examples/mbed-serial/platformio.ini @@ -10,4 +10,4 @@ [env:nucleo_f030r8] platform = ststm32 framework = mbed -board = nucleo_f030r8 \ No newline at end of file +board = nucleo_f030r8 diff --git a/examples/mbed-rtos-custom-target/platformio.ini b/examples/mbed-rtos-custom-target/platformio.ini index 226909a6..76f2f788 100644 --- a/examples/mbed-rtos-custom-target/platformio.ini +++ b/examples/mbed-rtos-custom-target/platformio.ini @@ -13,7 +13,7 @@ platform = ststm32 framework = mbed board = custom_nucleo_l452re_mbed -board_build.mbed.ldscript = $PROJECTSRC_DIR/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/STM32L452XX.ld +board_build.mbed.ldscript = $PROJECTSRC_DIR/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/stm32l452xe.ld build_flags = -I$PROJECTSRC_DIR/TARGET_STM32L452xE -I$PROJECTSRC_DIR/TARGET_STM32L452xE/device diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/CMakeLists.txt b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/CMakeLists.txt new file mode 100644 index 00000000..ad2bd275 --- /dev/null +++ b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("NUCLEO_L452RE_P" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_NUCLEO_L452RE_P) +endif() + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32l452xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32l452xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32l452xe.sct) +endif() + +set_property(GLOBAL PROPERTY MBED_TARGET_LINKER_FILE ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_sources(mbed-core + INTERFACE + system_clock.c + ${STARTUP_FILE} +) + +target_include_directories(mbed-core + INTERFACE + . +) diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/CMakeLists.txt b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/CMakeLists.txt new file mode 100644 index 00000000..118fbc11 --- /dev/null +++ b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-core + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-core + INTERFACE + . +) diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralNames.h b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralNames.h deleted file mode 100644 index bcd95123..00000000 --- a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralNames.h +++ /dev/null @@ -1,95 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - LPUART_1 = (int)LPUART1_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 3 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE, - I2C_4 = (int)I2C4_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, // TIM2 used by usticker - PWM_3 = (int)TIM3_BASE, - PWM_6 = (int)TIM6_BASE, -// PWM_7 = (int)TIM7_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, -} PWMName; - -typedef enum { - CAN_1 = (int)CAN1_BASE -} CANName; - -typedef enum { - QSPI_1 = (int)QSPI_R_BASE, -} QSPIName; - -typedef enum { - USB_FS = (int)USB_BASE, -} USBName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S similarity index 94% rename from examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S rename to examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S index 7e9dd534..07ad0876 100644 --- a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S +++ b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/startup_stm32l452xx.S @@ -18,10 +18,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -60,7 +60,10 @@ defined in linker script */ .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: - ldr sp, =_estack /* Atollic update: set stack pointer */ + ldr sp, =_estack /* Set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 @@ -90,21 +93,12 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start + bl _start + bx lr LoopForever: b LoopForever - + .size Reset_Handler, .-Reset_Handler /** diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/STM32L452XX.ld b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/stm32l452xe.ld similarity index 97% rename from examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/STM32L452XX.ld rename to examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/stm32l452xe.ld index cde243f9..17fbe4a7 100644 --- a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/TOOLCHAIN_GCC_ARM/STM32L452XX.ld +++ b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/TOOLCHAIN_GCC_ARM/stm32l452xe.ld @@ -28,10 +28,10 @@ M_CRASH_DATA_RAM_SIZE = 0x100; -#if !defined(MBED_BOOT_STACK_SIZE) +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_BOOT_STACK_SIZE 0x400 + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 #endif /* Round up VECTORS_SIZE to 8 bytes */ @@ -137,7 +137,7 @@ SECTIONS { __StackLimit = .; *(.stack*); - . += MBED_BOOT_STACK_SIZE - (. - __StackLimit); + . += MBED_CONF_TARGET_BOOT_STACK_SIZE - (. - __StackLimit); } > SRAM2 /* Set stack top to end of RAM, and stack limit move down by diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/cmsis_nvic.h b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/cmsis_nvic.h similarity index 100% rename from examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/cmsis_nvic.h rename to examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/cmsis_nvic.h diff --git a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/stm32l452xx.h b/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/stm32l452xx.h deleted file mode 100644 index 731f19b1..00000000 --- a/examples/mbed-rtos-custom-target/src/TARGET_STM32L452xE/device/stm32l452xx.h +++ /dev/null @@ -1,16062 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l452xx.h - * @author MCD Application Team - * @brief CMSIS STM32L452xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS_Device - * @{ - */ - -/** @addtogroup stm32l452xx - * @{ - */ - -#ifndef __STM32L452xx_H -#define __STM32L452xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ - DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ - COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ - LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ - USB_IRQn = 67, /*!< USB event Interrupt */ - DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ - DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ - LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ - QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ - TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ - RNG_IRQn = 80, /*!< RNG global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - CRS_IRQn = 82, /*!< CRS global interrupt */ - I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */ - I2C4_ER_IRQn = 84 /*!< I2C4 Error interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32l4xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, 0x1C */ - __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ - __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ - uint32_t RESERVED3; /*!< Reserved, 0x44 */ - uint32_t RESERVED4; /*!< Reserved, 0x48 */ - __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ - uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ - __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ - uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ - __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ - uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ - uint32_t RESERVED9; /*!< Reserved, 0x0AC */ - __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ - -} ADC_TypeDef; - -typedef struct -{ - uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ - __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ - __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ - __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ - __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ - __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ - __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ -} DAC_TypeDef; - -/** - * @brief DFSDM module registers - */ -typedef struct -{ - __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ - __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ - __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ - __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ - __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ - __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ - __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ - __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ - __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ - __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ - __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ - __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ - __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ - __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ - __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ -} DFSDM_Filter_TypeDef; - -/** - * @brief DFSDM channel configuration registers - */ -typedef struct -{ - __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ - __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ - __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and - short circuit detector register, Address offset: 0x08 */ - __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ - __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ -} DFSDM_Channel_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ -} DBGMCU_TypeDef; - - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register */ -} DMA_Request_TypeDef; - -/* Legacy define */ -#define DMA_request_TypeDef DMA_Request_TypeDef - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ -} EXTI_TypeDef; - - -/** - * @brief Firewall - */ - -typedef struct -{ - __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ - __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ - __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ - __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ - __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ - __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ - __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ -} FIREWALL_TypeDef; - - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ - __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ - __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ - __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ - __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ - __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ - __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ - __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ -} FLASH_TypeDef; - - - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - -} GPIO_TypeDef; - - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ -} IWDG_TypeDef; - -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ -} LPTIM_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ -} OPAMP_Common_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ - __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ - __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ - __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ - __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ - __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ - __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ - __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ - __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ - __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ - __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ - __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ - __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ - __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ - __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ -} PWR_TypeDef; - - -/** - * @brief QUAD Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ - __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ - __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ - __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ - __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ - __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ - __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ -} QUADSPI_TypeDef; - - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ - __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ - __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ - __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ - __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ - __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ - __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ - __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ - __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ - __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ - __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ - __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ - __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ - __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ - uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ - __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ - __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ - __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ - __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - uint32_t reserved; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - - -/** - * @brief Secure digital input/output Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ -} SPI_TypeDef; - - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ - __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ - __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ -} SYSCFG_TypeDef; - - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ - __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ - __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ -} TIM_TypeDef; - - -/** - * @brief Touch Sensing Controller (TSC) - */ - -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ -} TSC_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ - -typedef struct -{ - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ - __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ - __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ - __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ - __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ - __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ - __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ - __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ - __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ - __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ - __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ - __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ - __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ - __IO uint16_t RESERVEDD; /*!< Reserved */ - __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ - __IO uint16_t RESERVEDE; /*!< Reserved */ -} USB_TypeDef; - -/** - * @brief VREFBUF - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ - __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ -} VREFBUF_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 512 KB) base address */ -#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 128 KB) base address */ -#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ -#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ -#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ - -#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - -#define SRAM1_SIZE_MAX (0x00020000UL) /*!< maximum SRAM1 size (up to 128 KBytes) */ -#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) - - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) -#define USB_BASE (APB1PERIPH_BASE + 0x6800UL) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00UL) /*!< USB_IP Packet Memory Area base address */ -#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) - - -/*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) - -/*!< AHB1 peripherals */ -#define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) - - -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) - - -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) - - -/*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) - - -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) -#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) - - -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) - - - -/* Debug MCU registers base address */ -#define DBGMCU_BASE (0xE0042000UL) - - -#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ -#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CRS ((CRS_TypeDef *) CRS_BASE) -// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED already has (and thus compilers hate this) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define USB ((USB_TypeDef *) USB_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC1_BASE) -#define DAC1 ((DAC_TypeDef *) DAC1_BASE) -#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) -#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) -#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) -#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) - -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) -#define COMP1 ((COMP_TypeDef *) COMP1_BASE) -#define COMP2 ((COMP_TypeDef *) COMP2_BASE) -#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) -#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) -#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) -#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) -#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) -#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) -#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) -/* Aliases to keep compatibility after DFSDM renaming */ -#define DFSDM_Channel0 DFSDM1_Channel0 -#define DFSDM_Channel1 DFSDM1_Channel1 -#define DFSDM_Channel2 DFSDM1_Channel2 -#define DFSDM_Channel3 DFSDM1_Channel3 -#define DFSDM_Filter0 DFSDM1_Filter0 -#define DFSDM_Filter1 DFSDM1_Filter1 -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define TSC ((TSC_TypeDef *) TSC_BASE) - -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - - -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) - - -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) -#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) - - - -#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) - */ -/* Note: No specific macro feature on this device */ - -/******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ -#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ -#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ -#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ -#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ -#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ -#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ -#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ -#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ -#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ -#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ - -/******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ -#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ -#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ -#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ -#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ -#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ -#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ -#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ -#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ -#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ -#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ -#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ - -/* Legacy defines */ -#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) -#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) -#define ADC_IER_EOC (ADC_IER_EOCIE) -#define ADC_IER_EOS (ADC_IER_EOSIE) -#define ADC_IER_OVR (ADC_IER_OVRIE) -#define ADC_IER_JEOC (ADC_IER_JEOCIE) -#define ADC_IER_JEOS (ADC_IER_JEOSIE) -#define ADC_IER_AWD1 (ADC_IER_AWD1IE) -#define ADC_IER_AWD2 (ADC_IER_AWD2IE) -#define ADC_IER_AWD3 (ADC_IER_AWD3IE) -#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ -#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ -#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ -#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ -#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ -#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ -#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ -#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ -#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ -#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ -#define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ -#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ - -/******************** Bit definition for ADC_CFGR register ******************/ -#define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ -#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ -#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ - -#define ADC_CFGR_DFSDMCFG_Pos (2U) -#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ -#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ - -#define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ -#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ - -#define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ - -#define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ -#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ - -#define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ -#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ - -#define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ -#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ -#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ -#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ - -#define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ -#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ - -#define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ -#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ - -#define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ -#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ -#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ -#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ -#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ -#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ -#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ - -#define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ -#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ - -#define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ -#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ - -/******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ -#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ -#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ - -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - -#define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ -#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ - -#define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ -#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ -#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ - -/******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ - -#define ADC_SMPR1_SMPPLUS_Pos (31U) -#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ -#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ - -/******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ - -/******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ -#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ - -#define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ -#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ -#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ - -#define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ -#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ - -#define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ -#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ - -#define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ -#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ - -#define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ -#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ - -#define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ -#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ -#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ - -#define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ - -#define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ - -#define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ -#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ - -#define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ -#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ - -#define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ -#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ - -#define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ -#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ -#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ - -#define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ -#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ - -#define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ -#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ - -#define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ -#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ - -#define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ - -#define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ - -#define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ - -#define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ - -#define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ - -/******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ - -#define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ - -/******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ - -#define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ - -/******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ - -#define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ - -/******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR2 register ******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR3 register ******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR4 register ******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ -#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ - -#define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ -#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ - -/************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ -#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ - -#define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ - -#define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!*/ -#define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ -#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! Date: Mon, 28 Dec 2020 14:07:58 +0200 Subject: [PATCH 3/7] Delete deprecated STM32Cube example --- .../stm32cube-hal-usb-host-hid/.gitignore | 1 - .../stm32cube-hal-usb-host-hid/.travis.yml | 67 --- .../stm32cube-hal-usb-host-hid/README.rst | 32 -- .../stm32cube-hal-usb-host-hid/include/README | 39 -- .../stm32cube-hal-usb-host-hid/lib/README | 46 -- .../stm32cube-hal-usb-host-hid/platformio.ini | 15 - .../stm32cube-hal-usb-host-hid/src/keyboard.c | 197 ------- .../src/lcd_log_conf.h | 132 ----- .../stm32cube-hal-usb-host-hid/src/main.c | 341 ------------- .../stm32cube-hal-usb-host-hid/src/main.h | 101 ---- .../stm32cube-hal-usb-host-hid/src/menu.c | 334 ------------ .../stm32cube-hal-usb-host-hid/src/mouse.c | 299 ----------- .../src/stm32l4xx_hal_conf.h | 402 --------------- .../src/stm32l4xx_it.c | 170 ------ .../src/stm32l4xx_it.h | 52 -- .../src/system_stm32l4xx.c | 344 ------------- .../src/usbh_conf.c | 482 ------------------ .../src/usbh_conf.h | 85 --- .../stm32cube-hal-usb-host-hid/test/README | 11 - 19 files changed, 3150 deletions(-) delete mode 100644 examples/stm32cube-hal-usb-host-hid/.gitignore delete mode 100644 examples/stm32cube-hal-usb-host-hid/.travis.yml delete mode 100644 examples/stm32cube-hal-usb-host-hid/README.rst delete mode 100644 examples/stm32cube-hal-usb-host-hid/include/README delete mode 100644 examples/stm32cube-hal-usb-host-hid/lib/README delete mode 100644 examples/stm32cube-hal-usb-host-hid/platformio.ini delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/keyboard.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/lcd_log_conf.h delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/main.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/main.h delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/menu.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/mouse.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_hal_conf.h delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.h delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/system_stm32l4xx.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/usbh_conf.c delete mode 100644 examples/stm32cube-hal-usb-host-hid/src/usbh_conf.h delete mode 100644 examples/stm32cube-hal-usb-host-hid/test/README diff --git a/examples/stm32cube-hal-usb-host-hid/.gitignore b/examples/stm32cube-hal-usb-host-hid/.gitignore deleted file mode 100644 index 03f4a3c1..00000000 --- a/examples/stm32cube-hal-usb-host-hid/.gitignore +++ /dev/null @@ -1 +0,0 @@ -.pio diff --git a/examples/stm32cube-hal-usb-host-hid/.travis.yml b/examples/stm32cube-hal-usb-host-hid/.travis.yml deleted file mode 100644 index 7c486f18..00000000 --- a/examples/stm32cube-hal-usb-host-hid/.travis.yml +++ /dev/null @@ -1,67 +0,0 @@ -# Continuous Integration (CI) is the practice, in software -# engineering, of merging all developer working copies with a shared mainline -# several times a day < https://docs.platformio.org/page/ci/index.html > -# -# Documentation: -# -# * Travis CI Embedded Builds with PlatformIO -# < https://docs.travis-ci.com/user/integration/platformio/ > -# -# * PlatformIO integration with Travis CI -# < https://docs.platformio.org/page/ci/travis.html > -# -# * User Guide for `platformio ci` command -# < https://docs.platformio.org/page/userguide/cmd_ci.html > -# -# -# Please choose one of the following templates (proposed below) and uncomment -# it (remove "# " before each line) or use own configuration according to the -# Travis CI documentation (see above). -# - - -# -# Template #1: General project. Test it using existing `platformio.ini`. -# - -# language: python -# python: -# - "2.7" -# -# sudo: false -# cache: -# directories: -# - "~/.platformio" -# -# install: -# - pip install -U platformio -# - platformio update -# -# script: -# - platformio run - - -# -# Template #2: The project is intended to be used as a library with examples. -# - -# language: python -# python: -# - "2.7" -# -# sudo: false -# cache: -# directories: -# - "~/.platformio" -# -# env: -# - PLATFORMIO_CI_SRC=path/to/test/file.c -# - PLATFORMIO_CI_SRC=examples/file.ino -# - PLATFORMIO_CI_SRC=path/to/test/directory -# -# install: -# - pip install -U platformio -# - platformio update -# -# script: -# - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N diff --git a/examples/stm32cube-hal-usb-host-hid/README.rst b/examples/stm32cube-hal-usb-host-hid/README.rst deleted file mode 100644 index bb158330..00000000 --- a/examples/stm32cube-hal-usb-host-hid/README.rst +++ /dev/null @@ -1,32 +0,0 @@ -.. Copyright 2014-present PlatformIO - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - -How to build PlatformIO based project -===================================== - -1. `Install PlatformIO Core `_ -2. Download `development platform with examples `_ -3. Extract ZIP archive -4. Run these commands: - -.. code-block:: bash - - # Change directory to example - > cd platform-ststm32/examples/stm32cube-hal-extmem-boot - - # Build project - > platformio run - - # Upload firmware - > platformio run --target upload - - # Clean build files - > platformio run --target clean diff --git a/examples/stm32cube-hal-usb-host-hid/include/README b/examples/stm32cube-hal-usb-host-hid/include/README deleted file mode 100644 index 194dcd43..00000000 --- a/examples/stm32cube-hal-usb-host-hid/include/README +++ /dev/null @@ -1,39 +0,0 @@ - -This directory is intended for project header files. - -A header file is a file containing C declarations and macro definitions -to be shared between several project source files. You request the use of a -header file in your project source file (C, C++, etc) located in `src` folder -by including it, with the C preprocessing directive `#include'. - -```src/main.c - -#include "header.h" - -int main (void) -{ - ... -} -``` - -Including a header file produces the same results as copying the header file -into each source file that needs it. Such copying would be time-consuming -and error-prone. With a header file, the related declarations appear -in only one place. If they need to be changed, they can be changed in one -place, and programs that include the header file will automatically use the -new version when next recompiled. The header file eliminates the labor of -finding and changing all the copies as well as the risk that a failure to -find one copy will result in inconsistencies within a program. - -In C, the usual convention is to give header files names that end with `.h'. -It is most portable to use only letters, digits, dashes, and underscores in -header file names, and at most one dot. - -Read more about using header files in official GCC documentation: - -* Include Syntax -* Include Operation -* Once-Only Headers -* Computed Includes - -https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/stm32cube-hal-usb-host-hid/lib/README b/examples/stm32cube-hal-usb-host-hid/lib/README deleted file mode 100644 index 6debab1e..00000000 --- a/examples/stm32cube-hal-usb-host-hid/lib/README +++ /dev/null @@ -1,46 +0,0 @@ - -This directory is intended for project specific (private) libraries. -PlatformIO will compile them to static libraries and link into executable file. - -The source code of each library should be placed in a an own separate directory -("lib/your_library_name/[here are source files]"). - -For example, see a structure of the following two libraries `Foo` and `Bar`: - -|--lib -| | -| |--Bar -| | |--docs -| | |--examples -| | |--src -| | |- Bar.c -| | |- Bar.h -| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html -| | -| |--Foo -| | |- Foo.c -| | |- Foo.h -| | -| |- README --> THIS FILE -| -|- platformio.ini -|--src - |- main.c - -and a contents of `src/main.c`: -``` -#include -#include - -int main (void) -{ - ... -} - -``` - -PlatformIO Library Dependency Finder will find automatically dependent -libraries scanning project source files. - -More information about PlatformIO Library Dependency Finder -- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/stm32cube-hal-usb-host-hid/platformio.ini b/examples/stm32cube-hal-usb-host-hid/platformio.ini deleted file mode 100644 index 40d4126d..00000000 --- a/examples/stm32cube-hal-usb-host-hid/platformio.ini +++ /dev/null @@ -1,15 +0,0 @@ -; PlatformIO Project Configuration File -; -; Build options: build flags, source filter, extra scripting -; Upload options: custom port, speed and extra flags -; Library options: dependencies, extra library storages -; -; Please visit documentation for the other options and examples -; http://docs.platformio.org/page/projectconf.html - -[env:nucleo_l4r5zi] -platform = ststm32 -framework = stm32cube -board = nucleo_l4r5zi -board_build.stm32cube.variant = STM32L4xx_Nucleo_144 -board_build.stm32cube.disable_embedded_libs = yes \ No newline at end of file diff --git a/examples/stm32cube-hal-usb-host-hid/src/keyboard.c b/examples/stm32cube-hal-usb-host-hid/src/keyboard.c deleted file mode 100644 index c2d5a6fb..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/keyboard.c +++ /dev/null @@ -1,197 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Src/keyboard.c - * @author MCD Application Team - * @brief This file implements the HID keyboard functions - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* -#define KYBRD_FIRST_COLUMN (uint16_t)7 -#define KYBRD_LAST_COLUMN (uint16_t)479 -#define KYBRD_FIRST_LINE (uint8_t) 70 -#define SMALL_FONT_COLUMN_WIDTH 8 -#define SMALL_FONT_LINE_WIDTH 15 -#define KYBRD_LAST_LINE (uint16_t)200 -*/ - -#define KYBRD_FIRST_COLUMN 7 -#define KYBRD_LAST_COLUMN 121 -#define KYBRD_FIRST_LINE 50 -#define SMALL_FONT_COLUMN_WIDTH 6 -#define SMALL_FONT_LINE_WIDTH 10 -#define KYBRD_LAST_LINE 81 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -extern HID_DEMO_StateMachine hid_demo; -extern uint8_t *DEMO_KEYBOARD_menu[]; -extern uint8_t prev_select; -extern uint32_t hid_demo_ready; -uint8_t KeybrdCharXpos = 0; -uint16_t KeybrdCharYpos = 0; - -/* Private function prototypes -----------------------------------------------*/ -static void USR_KEYBRD_Init(void); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Manages Keyboard Menu Process. - * @param None - * @retval None - */ -void HID_KeyboardMenuProcess(void) -{ - switch(hid_demo.keyboard_state) - { - case HID_KEYBOARD_IDLE: - hid_demo.keyboard_state = HID_KEYBOARD_START; - HID_SelectItem(DEMO_KEYBOARD_menu, 0); - hid_demo.select = 0; - prev_select = 0; - break; - - case HID_KEYBOARD_WAIT: - if(hid_demo.select != prev_select) - { - prev_select = hid_demo.select ; - HID_SelectItem(DEMO_KEYBOARD_menu, hid_demo.select & 0x7F); - /* Handle select item */ - if(hid_demo.select & 0x80) - { - hid_demo.select &= 0x7F; - switch(hid_demo.select) - { - case 0: - hid_demo.keyboard_state = HID_KEYBOARD_START; - break; - - case 1: /* Return */ - LCD_LOG_ClearTextZone(); - hid_demo.state = HID_DEMO_REENUMERATE; - hid_demo.select = 0; - break; - - default: - break; - } - } - } - break; - - case HID_KEYBOARD_START: - USR_KEYBRD_Init(); - hid_demo.keyboard_state = HID_KEYBOARD_WAIT; - break; - - default: - break; - } -} - -/** - * @brief Init Keyboard window. - * @param None - * @retval None - */ -static void USR_KEYBRD_Init(void) -{ - LCD_LOG_ClearTextZone(); - BSP_LCD_SetTextColor(LCD_COLOR_YELLOW); - - BSP_LCD_DisplayStringAtLine(4, (uint8_t *)"Use Keyboard to tape"); - BSP_LCD_DisplayStringAtLine(5, (uint8_t *)"characters:"); - BSP_LCD_SetTextColor(LCD_COLOR_WHITE); - - KeybrdCharXpos = KYBRD_FIRST_LINE; - KeybrdCharYpos = KYBRD_FIRST_COLUMN; -} - -/** - * @brief Processes Keyboard data. - * @param data: Keyboard data to be displayed - * @retval None - */ -void USR_KEYBRD_ProcessData(uint8_t data) -{ - if(data == '\n') - { - KeybrdCharYpos = KYBRD_FIRST_COLUMN; - - /* Increment char X position */ - KeybrdCharXpos += SMALL_FONT_LINE_WIDTH; - - if(KeybrdCharXpos > KYBRD_LAST_LINE) - { - LCD_LOG_ClearTextZone(); - KeybrdCharXpos = KYBRD_FIRST_LINE; - KeybrdCharYpos = KYBRD_FIRST_COLUMN; - } - } - else if(data == '\r') - { - /* Manage deletion of character and upadte cursor location */ - if( KeybrdCharYpos == KYBRD_FIRST_COLUMN) - { - /* First character of first line to be deleted */ - if(KeybrdCharXpos == KYBRD_FIRST_LINE) - { - KeybrdCharYpos = KYBRD_FIRST_COLUMN; - } - else - { - KeybrdCharXpos -= SMALL_FONT_LINE_WIDTH; - KeybrdCharYpos = (KYBRD_LAST_COLUMN - SMALL_FONT_COLUMN_WIDTH); - } - } - else - { - KeybrdCharYpos -= SMALL_FONT_COLUMN_WIDTH; - } - BSP_LCD_DisplayChar(KeybrdCharYpos, KeybrdCharXpos, ' '); - } - else - { - /* Update the cursor position on LCD */ - BSP_LCD_DisplayChar(KeybrdCharYpos, KeybrdCharXpos, data); - - /* Increment char Y position */ - KeybrdCharYpos += SMALL_FONT_COLUMN_WIDTH; - - /* Check if the Y position has reached the last column */ - if(KeybrdCharYpos == KYBRD_LAST_COLUMN) - { - KeybrdCharYpos = KYBRD_FIRST_COLUMN; - - /* Increment char X position */ - KeybrdCharXpos += SMALL_FONT_LINE_WIDTH; - } - - if(KeybrdCharXpos > KYBRD_LAST_LINE) - { - LCD_LOG_ClearTextZone(); - KeybrdCharXpos = KYBRD_FIRST_LINE; - /* Start New Display of the cursor position on LCD */ - BSP_LCD_DisplayChar(KeybrdCharYpos,KeybrdCharXpos, data); - } - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/lcd_log_conf.h b/examples/stm32cube-hal-usb-host-hid/src/lcd_log_conf.h deleted file mode 100644 index 9f2ea48a..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/lcd_log_conf.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - ****************************************************************************** - * @file lcd_log_conf.h - * @author MCD Application Team - * @brief lcd_log configuration template file. - * This file should be copied to the application folder and modified - * as follows: - * - Rename it to 'lcd_log_conf.h'. - * - Update the name of the LCD driver's header file, depending on - * the EVAL board you are using, see line40 below (be default this - * file will generate compile error unless you do this modification). - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __LCD_LOG_CONF_H__ -#define __LCD_LOG_CONF_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_nucleo_144.h" -#include "stm32_adafruit_lcd.h" -#include - - -/** @addtogroup LCD_LOG - * @{ - */ - -/** @defgroup LCD_LOG - * @brief This file is the - * @{ - */ - - -/** @defgroup LCD_LOG_CONF_Exported_Defines - * @{ - */ - -/* Define the LCD default text color */ -#define LCD_LOG_DEFAULT_COLOR LCD_COLOR_WHITE - -/* Comment the line below to disable the scroll back and forward features */ -#define LCD_SCROLL_ENABLED 1 - - -/* Define the Fonts */ -#define LCD_LOG_HEADER_FONT Font8 -#define LCD_LOG_FOOTER_FONT Font8 -#define LCD_LOG_TEXT_FONT Font8 - -/* Define the LCD LOG Color */ -#define LCD_LOG_BACKGROUND_COLOR LCD_COLOR_BLACK -#define LCD_LOG_TEXT_COLOR LCD_COLOR_WHITE - -#define LCD_LOG_SOLID_BACKGROUND_COLOR LCD_COLOR_BLUE -#define LCD_LOG_SOLID_TEXT_COLOR LCD_COLOR_WHITE - -/* Define the cache depth */ -#define CACHE_SIZE 100 -#define YWINDOW_SIZE 8 - -#if (YWINDOW_SIZE > 14) - #error "Wrong YWINDOW SIZE" -#endif - -/* Redirect the printf to the LCD */ -#ifdef __GNUC__ -/* With GCC, small printf (option LD Linker->Libraries->Small printf - set to 'Yes') calls __io_putchar() */ -#define LCD_LOG_PUTCHAR int __io_putchar(int ch) -#else -#define LCD_LOG_PUTCHAR int fputc(int ch, FILE *f) -#endif /* __GNUC__ */ - -/** @defgroup LCD_LOG_CONF_Exported_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup LCD_LOG_Exported_Macros - * @{ - */ - - -/** - * @} - */ - -/** @defgroup LCD_LOG_CONF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup LCD_LOG_CONF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - - -#endif //__LCD_LOG_CONF_H__ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/main.c b/examples/stm32cube-hal-usb-host-hid/src/main.c deleted file mode 100644 index 0164f5fd..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/main.c +++ /dev/null @@ -1,341 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Src/main.c - * @author MCD Application Team - * @brief USB host HID Mouse and Keyboard demo main file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private typedef -----------------------------------------------------------*/ -typedef enum -{ - SHIELD_NOT_DETECTED = 0, - SHIELD_DETECTED -}ShieldStatus; -/* Private define ------------------------------------------------------------*/ -#define ADC_MULTIMODE_SUPPORT 1 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -USBH_HandleTypeDef hUSBHost; -HID_ApplicationTypeDef Appli_state = APPLICATION_IDLE; - - - -/* Private function prototypes -----------------------------------------------*/ -static void SystemClock_Config(void); -static ShieldStatus TFT_ShieldDetect(void); -static void USBH_UserProcess(USBH_HandleTypeDef *phost, uint8_t id); -static void HID_InitApplication(void); -static void Error_Handler(void); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Main program - * @param None - * @retval None - */ -int main(void) -{ - /* STM32L4xx HAL library initialization: - - Configure the Flash prefetch - - Systick timer is configured by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - - Set NVIC Group Priority to 4 - - Low Level Initialization - */ - - /* Initialize the HAL Library */ - HAL_Init(); - - /* Configure the system clock to 80 MHz */ - SystemClock_Config(); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Check the availability of adafruit 1.8" TFT shield on top of STM32NUCLEO - board. This is done by reading the state of IO PF.03 pin (mapped to - JoyStick available on adafruit 1.8" TFT shield). If the state of PF.03 - is high then the adafruit 1.8" TFT shield is available. */ - if(TFT_ShieldDetect() != SHIELD_DETECTED) - { - Error_Handler(); - } - - /* Enable USB power on Pwrctrl CR2 register */ - HAL_PWREx_EnableVddUSB(); - - /* Init HID Application */ - HID_InitApplication(); - - /* Init Host Library */ - USBH_Init(&hUSBHost, USBH_UserProcess, 0); - - /* Add Supported Class */ - USBH_RegisterClass(&hUSBHost, USBH_HID_CLASS); - - /* Start Host Process */ - USBH_Start(&hUSBHost); - - /* Run Application (Blocking mode) */ - while (1) - { - /* USB Host Background task */ - USBH_Process(&hUSBHost); - - /* HID Menu Process */ - HID_MenuProcess(); - /* HID Joystick */ - HID_Joysticky(); - } -} - - - - -/** - * @brief HID application Init - * @param None - * @retval None - */ -static void HID_InitApplication(void) -{ - /* Initialize the LCD */ - BSP_LCD_Init(); - - /* Configure Joystick in EXTI mode */ - BSP_JOY_Init(); - - /* Configure KEY Button */ - BSP_PB_Init(BUTTON_USER, BUTTON_MODE_EXTI); - - /* Configure the LEDs */ - BSP_LED_Init(LED1); - BSP_LED_Init(LED2); - BSP_LED_Init(LED3); - - /* Init the LCD Log module */ - LCD_LOG_Init(); - - LCD_LOG_SetHeader((uint8_t *)" USB OTG FS HID Host"); - - LCD_UsrLog("USB Host library started.\n"); - - /* Start HID Interface */ - HID_MenuInit(); -} - -/** - * @brief User Process - * @param phost: Host Handle - * @param id: Host Library user message ID - * @retval None - */ -static void USBH_UserProcess(USBH_HandleTypeDef *phost, uint8_t id) -{ - switch(id) - { - case HOST_USER_SELECT_CONFIGURATION: - break; - - case HOST_USER_DISCONNECTION: - Appli_state = APPLICATION_DISCONNECT; - break; - - case HOST_USER_CLASS_ACTIVE: - Appli_state = APPLICATION_READY; - break; - - case HOST_USER_CONNECTION: - Appli_state = APPLICATION_START; - break; - - default: - break; - } -} - -/** - * @brief Toggles LEDs to show user input state. - * @param None - * @retval None - */ -void Toggle_Leds(void) -{ - static uint32_t ticks; - - if(ticks++ == 100) - { - BSP_LED_Toggle(LED1); - BSP_LED_Toggle(LED2); - BSP_LED_Toggle(LED3); - ticks = 0; - } -} - -/** - * @brief Check the availability of adafruit 1.8" TFT shield on top of STM32NUCLEO - * board. This is done by reading the state of IO PF.03 pin (mapped to - * JoyStick available on adafruit 1.8" TFT shield). If the state of PF.03 - * is high then the adafruit 1.8" TFT shield is available. - * @param None - * @retval SHIELD_DETECTED: 1.8" TFT shield is available - * SHIELD_NOT_DETECTED: 1.8" TFT shield is not available - */ -static ShieldStatus TFT_ShieldDetect(void) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /* Enable GPIO clock */ - NUCLEO_ADCx_GPIO_CLK_ENABLE(); - - GPIO_InitStruct.Pin = NUCLEO_ADCx_GPIO_PIN ; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - HAL_GPIO_Init(NUCLEO_ADCx_GPIO_PORT , &GPIO_InitStruct); - - if(HAL_GPIO_ReadPin(NUCLEO_ADCx_GPIO_PORT, NUCLEO_ADCx_GPIO_PIN) != 0) - { - return SHIELD_DETECTED; - } - else - { - return SHIELD_NOT_DETECTED; - } -} - - -/** - * @brief System Clock Configuration - * The system Clock is configured as follows : - * System Clock source = PLL (HSE) - * SYSCLK(Hz) = 120000000 - * HCLK(Hz) = 120000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 1 - * HSE Frequency(Hz) = 8000000 - * PLL_M = 2 - * PLL_N = 60 - * PLL_Q = 1 - * PLL_R = 1 - * PLL_P = 1 - * USB Clock source = PLLSAI1 - * PLLSAI1 source = PLL (HSE) - * PLLSAI1 out Frequency(Hz) = 48000000 - * PLLSAI1_M = 4 - * PLLSAI1_N = 96 - * PLLSAI1_Q = 4 - * PLLSAI1_P = 1 - * Flash Latency(WS) = 4 - * @param None - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /* Enable voltage range 1 boost mode for frequency above 80 Mhz */ - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - __HAL_RCC_PWR_CLK_DISABLE(); - - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 60; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; - - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - while(1) {}; - } - - /* Select PLLSAI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; - PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 4; - PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 96; - PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = 4; - PeriphClkInitStruct.PLLSAI1.PLLSAI1P = 1; - PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; - PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - while(1) {}; - } - - /* To avoid undershoot due to maximum frequency, select PLL as system clock source */ - /* with AHB prescaler divider 2 as first step */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { - while(1) {}; - } -} - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -static void Error_Handler(void) -{ - /* Turn LED3 on */ - BSP_LED_On(LED3); - - while (1) - { - } -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} -#endif - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/main.h b/examples/stm32cube-hal-usb-host-hid/src/main.h deleted file mode 100644 index 522aeacd..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/main.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Inc/main.h - * @author MCD Application Team - * @brief Header for main.c module - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -/* Includes ------------------------------------------------------------------*/ -#include "stdio.h" -#include "usbh_core.h" -#include "stm32l4xx_nucleo_144.h" -#include "stm32_adafruit_lcd.h" -#include "lcd_log.h" -#include "usbh_hid.h" -#include "usbh_hid_parser.h" - - -/* Exported types ------------------------------------------------------------*/ -typedef enum { - HID_DEMO_IDLE = 0, - HID_DEMO_WAIT, - HID_DEMO_START, - HID_DEMO_MOUSE, - HID_DEMO_KEYBOARD, - HID_DEMO_REENUMERATE, -}HID_Demo_State; - -typedef enum { - HID_MOUSE_IDLE = 0, - HID_MOUSE_WAIT, - HID_MOUSE_START, -}HID_mouse_State; - -typedef enum { - HID_KEYBOARD_IDLE = 0, - HID_KEYBOARD_WAIT, - HID_KEYBOARD_START, -}HID_keyboard_State; - -typedef struct _DemoStateMachine { - __IO HID_Demo_State state; - __IO HID_mouse_State mouse_state; - __IO HID_keyboard_State keyboard_state; - __IO JOYState_TypeDef joy_state; - __IO uint8_t select; - __IO uint8_t lock; -}HID_DEMO_StateMachine; - -typedef enum { - APPLICATION_IDLE = 0, - APPLICATION_DISCONNECT, - APPLICATION_START, - APPLICATION_READY, - APPLICATION_RUNNING, -}HID_ApplicationTypeDef; - -extern USBH_HandleTypeDef hUSBHost; -extern HID_ApplicationTypeDef Appli_state; -extern HID_MOUSE_Info_TypeDef mouse_info; -extern uint8_t *DEMO_MOUSE_menu[]; -extern HID_DEMO_StateMachine hid_demo; -extern uint8_t prev_select; - -/* Exported constants --------------------------------------------------------*/ - -/* Enable one of the following defines to select which clock will be used for USB */ -/* #define USB_USE_LSE_MSI_CLOCK */ /* Use MSI clock automatically trimmed by LSE as USB clock */ -#define USB_USE_HSE_CLOCK /* Use HSE as clock source for USB */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void Toggle_Leds(void); -void HID_SelectItem(uint8_t **menu, uint8_t item); -void HID_MenuInit(void); -void HID_MenuProcess(void); -void HID_MouseMenuProcess(void); -void HID_Joysticky(void); -void HID_KeyboardMenuProcess(void); -void HID_MOUSE_ButtonReleased(uint8_t button_idx); -void HID_MOUSE_ButtonPressed(uint8_t button_idx); -void USR_MOUSE_ProcessData(HID_MOUSE_Info_TypeDef *data); -void USR_KEYBRD_ProcessData(uint8_t data); -#endif /* __MAIN_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/menu.c b/examples/stm32cube-hal-usb-host-hid/src/menu.c deleted file mode 100644 index b51e84aa..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/menu.c +++ /dev/null @@ -1,334 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Src/menu.c - * @author MCD Application Team - * @brief This file implements Menu Functions - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -HID_DEMO_StateMachine hid_demo; -uint8_t prev_select = 0; - -uint8_t *DEMO_KEYBOARD_menu[] = -{ - (uint8_t *)" 1 - Start Keyboard / Clear ", - (uint8_t *)" 2 - Return ", -}; - -uint8_t *DEMO_MOUSE_menu[] = -{ - (uint8_t *)" 1 - Start Mouse / Re-Initialize ", - (uint8_t *)" 2 - Return ", -}; - -uint8_t *DEMO_HID_menu[] = -{ - (uint8_t *)" 1 - Start HID ", - (uint8_t *)" 2 - Re-Enumerate ", -}; - -/* Private function prototypes -----------------------------------------------*/ -static void HID_DEMO_ProbeKey(JOYState_TypeDef state); -static void USBH_MouseDemo(USBH_HandleTypeDef *phost); -static void USBH_KeybdDemo(USBH_HandleTypeDef *phost); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Demo state machine. - * @param None - * @retval None - */ -void HID_MenuInit(void) -{ - /* Start HID Interface */ - USBH_UsrLog("Starting HID Demo"); - - BSP_LCD_SetTextColor(LCD_COLOR_GREEN); - BSP_LCD_DisplayStringAtLine(14, (uint8_t *)"Use [Joystick Left/Right]"); - BSP_LCD_DisplayStringAtLine(15, (uint8_t *)"to scroll up/down"); - BSP_LCD_DisplayStringAtLine(16, (uint8_t *)"Use [Joystick Up/Down]"); - BSP_LCD_DisplayStringAtLine(17, (uint8_t *)"to scroll HID menu"); - hid_demo.state = HID_DEMO_IDLE; - HID_MenuProcess(); -} - -/** - * @brief Manages HID Menu Process. - * @param None - * @retval None - */ -void HID_MenuProcess(void) -{ - switch(hid_demo.state) - { - case HID_DEMO_IDLE: - HID_SelectItem(DEMO_HID_menu, 0); - hid_demo.state = HID_DEMO_WAIT; - hid_demo.select = 0; - break; - - case HID_DEMO_WAIT: - if(hid_demo.select != prev_select) - { - prev_select = hid_demo.select; - - HID_SelectItem(DEMO_HID_menu, hid_demo.select & 0x7F); - /* Handle select item */ - if(hid_demo.select & 0x80) - { - hid_demo.select &= 0x7F; - switch(hid_demo.select) - { - case 0: - hid_demo.state = HID_DEMO_START; - break; - - case 1: - hid_demo.state = HID_DEMO_REENUMERATE; - break; - - default: - break; - } - } - } - break; - - case HID_DEMO_START: - if(Appli_state == APPLICATION_READY) - { - if(USBH_HID_GetDeviceType(&hUSBHost) == HID_KEYBOARD) - { - hid_demo.keyboard_state = HID_KEYBOARD_IDLE; - hid_demo.state = HID_DEMO_KEYBOARD; - } - else if(USBH_HID_GetDeviceType(&hUSBHost) == HID_MOUSE) - { - hid_demo.mouse_state = HID_MOUSE_IDLE; - hid_demo.state = HID_DEMO_MOUSE; - } - } - else - { - LCD_ErrLog("No supported HID device!\n"); - hid_demo.state = HID_DEMO_WAIT; - } - break; - - case HID_DEMO_REENUMERATE: - /* Force HID Device to re-enumerate */ - USBH_ReEnumerate(&hUSBHost); - hid_demo.state = HID_DEMO_WAIT; - break; - - case HID_DEMO_MOUSE: - if(Appli_state == APPLICATION_READY) - { - HID_MouseMenuProcess(); - USBH_MouseDemo(&hUSBHost); - } - break; - - case HID_DEMO_KEYBOARD: - if(Appli_state == APPLICATION_READY) - { - HID_KeyboardMenuProcess(); - USBH_KeybdDemo(&hUSBHost); - } - break; - - default: - break; - } - - if(Appli_state == APPLICATION_DISCONNECT) - { - Appli_state = APPLICATION_IDLE; - LCD_LOG_ClearTextZone(); - LCD_ErrLog("HID device disconnected!\n"); - hid_demo.state = HID_DEMO_IDLE; - hid_demo.select = 0; - } -} - -/** - * @brief Manages the menu on the screen. - * @param menu: Menu table - * @param item: Selected item to be highlighted - * @retval None - */ -void HID_SelectItem(uint8_t **menu, uint8_t item) -{ - BSP_LCD_SetTextColor(LCD_COLOR_WHITE); - - switch(item) - { - case 0: - BSP_LCD_SetBackColor(LCD_COLOR_MAGENTA); - BSP_LCD_DisplayStringAtLine(18, menu [0]); - BSP_LCD_SetBackColor(LCD_COLOR_BLUE); - BSP_LCD_DisplayStringAtLine(19, menu [1]); - break; - - case 1: - BSP_LCD_SetBackColor(LCD_COLOR_BLUE); - BSP_LCD_DisplayStringAtLine(18, menu [0]); - BSP_LCD_SetBackColor(LCD_COLOR_MAGENTA); - BSP_LCD_DisplayStringAtLine(19, menu [1]); - BSP_LCD_SetBackColor(LCD_COLOR_BLUE); - break; - } - BSP_LCD_SetBackColor(LCD_COLOR_BLACK); - -} - -/** - * @brief Probes the HID joystick state. - * @param state: Joystick state - * @retval None - */ -static void HID_DEMO_ProbeKey(JOYState_TypeDef state) -{ - /* Handle Menu inputs */ - if(hid_demo.joy_state != state) - { - if((state == JOY_UP) && (hid_demo.select > 0)) - { - hid_demo.select--; - } - else if((state == JOY_DOWN) && (hid_demo.select < 2)) - { - hid_demo.select++; - } - else if(state == JOY_SEL) - { - hid_demo.select |= 0x80; - } - } - hid_demo.joy_state = state; -} - -/** - * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line - * @retval None - */ -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - return; -} - -/** - * @brief Get the joystick state. - * @param None - * @retval None - */ -void HID_Joysticky(void) -{ - static JOYState_TypeDef JoyState = JOY_NONE; - - /* Get the Joystick State */ - JoyState = BSP_JOY_GetState(); - - HID_DEMO_ProbeKey(JoyState); - - switch(JoyState) - { - case JOY_LEFT: - LCD_LOG_ScrollBack(); - break; - - case JOY_RIGHT: - LCD_LOG_ScrollForward(); - break; - - default: - break; - } -} - -/** - * @brief Main routine for Mouse application - * @param phost: Host handle - * @retval None - */ -static void USBH_MouseDemo(USBH_HandleTypeDef *phost) -{ - HID_MOUSE_Info_TypeDef *m_pinfo; - - m_pinfo = USBH_HID_GetMouseInfo(phost); - if(m_pinfo != NULL) - { - /* Handle Mouse data position */ - USR_MOUSE_ProcessData(&mouse_info); - - if(m_pinfo->buttons[0]) - { - HID_MOUSE_ButtonPressed(0); - } - else - { - HID_MOUSE_ButtonReleased(0); - } - - if(m_pinfo->buttons[1]) - { - HID_MOUSE_ButtonPressed(2); - } - else - { - HID_MOUSE_ButtonReleased(2); - } - - if(m_pinfo->buttons[2]) - { - HID_MOUSE_ButtonPressed(1); - } - else - { - HID_MOUSE_ButtonReleased(1); - } - } -} - -/** - * @brief Main routine for Keyboard application - * @param phost: Host handle - * @retval None - */ -static void USBH_KeybdDemo(USBH_HandleTypeDef *phost) -{ - HID_KEYBD_Info_TypeDef *k_pinfo; - char c; - k_pinfo = USBH_HID_GetKeybdInfo(phost); - - if(k_pinfo != NULL) - { - c = USBH_HID_GetASCIICode(k_pinfo); - if(c != 0) - { - USR_KEYBRD_ProcessData(c); - } - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/mouse.c b/examples/stm32cube-hal-usb-host-hid/src/mouse.c deleted file mode 100644 index abb9c265..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/mouse.c +++ /dev/null @@ -1,299 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Src/mouse.c - * @author MCD Application Team - * @brief This file implements Functions for mouse menu - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private typedef -----------------------------------------------------------*/ -extern USBH_HandleTypeDef hUSBHost; - -/* Private define ------------------------------------------------------------*/ - -/* Left Button Report data */ -#define HID_MOUSE_BUTTON1 0x01 -/* Right Button Report data */ -#define HID_MOUSE_BUTTON2 0x02 -/* Middle Button Report data */ -#define HID_MOUSE_BUTTON3 0x04 - -/* Mouse directions */ -#define MOUSE_TOP_DIR 0x80 -#define MOUSE_BOTTOM_DIR 0x00 -#define MOUSE_LEFT_DIR 0x80 -#define MOUSE_RIGHT_DIR 0x00 -/* -#define MOUSE_WINDOW_X 50 -#define MOUSE_WINDOW_Y 70 -#define MOUSE_WINDOW_X_MAX 181 -#define MOUSE_WINDOW_Y_MIN 101 -#define MOUSE_WINDOW_HEIGHT 80 -#define MOUSE_WINDOW_WIDTH 200 - -#define HID_MOUSE_BUTTON_HEIGHT 15 -#define HID_MOUSE_BUTTON_WIDTH 25 -#define HID_MOUSE_BUTTON1_XCHORD 50 -#define HID_MOUSE_BUTTON2_XCHORD 135 -#define HID_MOUSE_BUTTON3_XCHORD 225 -#define HID_MOUSE_BUTTON_YCHORD 170 -*/ - -#define MOUSE_WINDOW_X 7 -#define MOUSE_WINDOW_Y 52 -#define MOUSE_WINDOW_X_MAX 10 -#define MOUSE_WINDOW_Y_MIN 50 -#define MOUSE_WINDOW_HEIGHT 40 -#define MOUSE_WINDOW_WIDTH 110 - -#define HID_MOUSE_BUTTON_HEIGHT 10 -#define HID_MOUSE_BUTTON_WIDTH 30 -#define HID_MOUSE_BUTTON1_XCHORD 8 -#define HID_MOUSE_BUTTON2_XCHORD 48 -#define HID_MOUSE_BUTTON3_XCHORD 88 -#define HID_MOUSE_BUTTON_YCHORD 100 - -#define MOUSE_LEFT_MOVE 1 -#define MOUSE_RIGHT_MOVE 2 -#define MOUSE_UP_MOVE 3 -#define MOUSE_DOWN_MOVE 4 - -#define HID_MOUSE_HEIGHTLSB 2 -#define HID_MOUSE_WIDTHLSB 2 -#define HID_MOUSE_RES_X 4 -#define HID_MOUSE_RES_Y 4 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void USR_MOUSE_Init(void); -static void HID_MOUSE_UpdatePosition(int8_t x, int8_t y); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Manages Mouse Menu Process. - * @param None - * @retval None - */ -void HID_MouseMenuProcess(void) -{ - switch(hid_demo.mouse_state) - { - case HID_MOUSE_IDLE: - hid_demo.mouse_state = HID_MOUSE_START; - HID_SelectItem(DEMO_MOUSE_menu, 0); - hid_demo.select = 0; - prev_select = 0; - break; - - case HID_MOUSE_WAIT: - if(hid_demo.select != prev_select) - { - prev_select = hid_demo.select ; - HID_SelectItem(DEMO_MOUSE_menu, hid_demo.select & 0x7F); - - /* Handle select item */ - if(hid_demo.select & 0x80) - { - hid_demo.select &= 0x7F; - switch(hid_demo.select) - { - case 0: - hid_demo.mouse_state = HID_MOUSE_START; - break; - - case 1: /* Return */ - LCD_LOG_ClearTextZone(); - BSP_LCD_ClearStringLine(12); - BSP_LCD_ClearStringLine(13); - hid_demo.state = HID_DEMO_REENUMERATE; - hid_demo.select = 0; - break; - - default: - break; - } - } - } - break; - - case HID_MOUSE_START: - USR_MOUSE_Init(); - hid_demo.mouse_state = HID_MOUSE_WAIT; - HID_MOUSE_UpdatePosition(0,0); - break; - - default: - break; - } -} - -/** - * @brief Init Mouse window. - * @param None - * @retval None - */ -static void USR_MOUSE_Init(void) -{ - LCD_LOG_ClearTextZone(); - BSP_LCD_ClearStringLine(12); - BSP_LCD_ClearStringLine(13); - BSP_LCD_SetTextColor(LCD_COLOR_YELLOW); - BSP_LCD_DisplayStringAtLine(4, (uint8_t *)"USB HID Host Mouse Demo... "); - BSP_LCD_SetTextColor(LCD_LOG_DEFAULT_COLOR); - - /* Display Mouse Window */ - BSP_LCD_DrawRect(MOUSE_WINDOW_X, MOUSE_WINDOW_Y, MOUSE_WINDOW_WIDTH, MOUSE_WINDOW_HEIGHT); - - HID_MOUSE_ButtonReleased(0); - HID_MOUSE_ButtonReleased(1); - HID_MOUSE_ButtonReleased(2); - - BSP_LCD_SetTextColor(LCD_COLOR_GREEN); - BSP_LCD_SetBackColor(LCD_COLOR_BLACK); - - HID_MOUSE_UpdatePosition(0,0); -} - -/** - * @brief Processes Mouse data. - * @param data: Mouse data to be displayed - * @retval None - */ -void USR_MOUSE_ProcessData(HID_MOUSE_Info_TypeDef *data) -{ - if((data->x != 0) && (data->y != 0)) - { - HID_MOUSE_UpdatePosition(data->x , data->y); - } -} - -/** - * @brief Handles mouse scroll to update the mouse position on display window. - * @param x: USB HID Mouse X co-ordinate - * @param y: USB HID Mouse Y co-ordinate - * @retval None - */ -static void HID_MOUSE_UpdatePosition(int8_t x, int8_t y) -{ - static int16_t x_loc = 0, y_loc = 0; - static int16_t prev_x = 5, prev_y = 1; - - if((x != 0) || (y != 0)) - { - x_loc += x/2; - y_loc += y/10; - - if(y_loc > MOUSE_WINDOW_HEIGHT - 12) - { - y_loc = MOUSE_WINDOW_HEIGHT - 12; - } - if(x_loc > MOUSE_WINDOW_WIDTH - 10) - { - x_loc = MOUSE_WINDOW_WIDTH - 10; - } - - if(y_loc < 2) - { - y_loc = 2; - } - if(x_loc < 2) - { - x_loc = 2; - } - BSP_LCD_SetBackColor(LCD_COLOR_BLACK); - BSP_LCD_SetTextColor(LCD_COLOR_BLACK); - BSP_LCD_DisplayChar(MOUSE_WINDOW_X + prev_x, MOUSE_WINDOW_Y + prev_y, 'x'); - - BSP_LCD_SetTextColor(LCD_COLOR_GREEN); - BSP_LCD_DisplayChar(MOUSE_WINDOW_X + x_loc, MOUSE_WINDOW_Y + y_loc, 'x'); - - prev_x = x_loc; - prev_y = y_loc; - } -} - -/** - * @brief Handles mouse button press. - * @param button_idx: Mouse button pressed - * @retval None - */ -void HID_MOUSE_ButtonPressed(uint8_t button_idx) -{ - /* Set the color for button press status */ - BSP_LCD_SetTextColor(LCD_COLOR_BLUE); - BSP_LCD_SetBackColor(LCD_COLOR_BLUE); - - /* Change the color of button pressed to indicate button press */ - switch(button_idx) - { - /* Left Button Pressed */ - case 0: - BSP_LCD_FillRect(HID_MOUSE_BUTTON1_XCHORD, HID_MOUSE_BUTTON_YCHORD,\ - HID_MOUSE_BUTTON_WIDTH, HID_MOUSE_BUTTON_HEIGHT ); - break; - - /* Right Button Pressed */ - case 1: - BSP_LCD_FillRect(HID_MOUSE_BUTTON2_XCHORD,HID_MOUSE_BUTTON_YCHORD,\ - HID_MOUSE_BUTTON_WIDTH,HID_MOUSE_BUTTON_HEIGHT); - break; - - /* Middle button Pressed */ - case 2: - BSP_LCD_FillRect(HID_MOUSE_BUTTON3_XCHORD,HID_MOUSE_BUTTON_YCHORD,\ - HID_MOUSE_BUTTON_WIDTH,HID_MOUSE_BUTTON_HEIGHT); - break; - } -} - -/** - * @brief Handles mouse button release. - * @param button_idx: Mouse button released - * @retval None - */ -void HID_MOUSE_ButtonReleased(uint8_t button_idx) -{ - /* Set the color for release status */ - BSP_LCD_SetTextColor(LCD_COLOR_WHITE); - BSP_LCD_SetBackColor(LCD_COLOR_BLACK); - - /* Change the color of button released to default button color */ - switch(button_idx) - { - /* Left Button Released */ - case 0: - BSP_LCD_FillRect(HID_MOUSE_BUTTON1_XCHORD, HID_MOUSE_BUTTON_YCHORD,\ - HID_MOUSE_BUTTON_WIDTH, HID_MOUSE_BUTTON_HEIGHT); - break; - - /* Right Button Released */ - case 1: - BSP_LCD_FillRect(HID_MOUSE_BUTTON2_XCHORD, HID_MOUSE_BUTTON_YCHORD,\ - HID_MOUSE_BUTTON_WIDTH, HID_MOUSE_BUTTON_HEIGHT); - break; - - /* Middle Button Released */ - case 2: - BSP_LCD_FillRect(HID_MOUSE_BUTTON3_XCHORD, HID_MOUSE_BUTTON_YCHORD,\ - HID_MOUSE_BUTTON_WIDTH, HID_MOUSE_BUTTON_HEIGHT); - break; - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_hal_conf.h b/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_hal_conf.h deleted file mode 100644 index 143a21ef..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_hal_conf.h +++ /dev/null @@ -1,402 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_FIREWALL_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -#define HAL_NOR_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -#define HAL_HCD_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -#define HAL_LCD_MODULE_ENABLED -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_OPAMP_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -#define HAL_SAI_MODULE_ENABLED -#define HAL_SD_MODULE_ENABLED -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -#define HAL_SPI_MODULE_ENABLED -/* #define HAL_SWPMI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/** - * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "Legacy/stm32l4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32l4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32l4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32l4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32l4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32l4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_GFXMMU_MODULE_ENABLED - #include "stm32l4xx_hal_gfxmmu.h" -#endif /* HAL_GFXMMU_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t *file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.c b/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.c deleted file mode 100644 index d1b5fbb5..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.c +++ /dev/null @@ -1,170 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Src/stm32l4xx_it.c - * @author MCD Application Team - * @brief Main Interrupt Service Routines. - * This file provides template for all exceptions handler and - * peripherals interrupt service routine. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_it.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -extern HCD_HandleTypeDef hhcd; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************/ -/* Cortex-M4 Processor Exceptions Handlers */ -/******************************************************************************/ - -/** - * @brief This function handles NMI exception. - * @param None - * @retval None - */ -void NMI_Handler(void) -{ -} - -/** - * @brief This function handles Hard Fault exception. - * @param None - * @retval None - */ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Memory Manage exception. - * @param None - * @retval None - */ -void MemManage_Handler(void) -{ - /* Go to infinite loop when Memory Manage exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Bus Fault exception. - * @param None - * @retval None - */ -void BusFault_Handler(void) -{ - /* Go to infinite loop when Bus Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Usage Fault exception. - * @param None - * @retval None - */ -void UsageFault_Handler(void) -{ - /* Go to infinite loop when Usage Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles SVCall exception. - * @param None - * @retval None - */ -void SVC_Handler(void) -{ -} - -/** - * @brief This function handles Debug Monitor exception. - * @param None - * @retval None - */ -void DebugMon_Handler(void) -{ -} - -/** - * @brief This function handles PendSVC exception. - * @param None - * @retval None - */ -void PendSV_Handler(void) -{ -} - -/** - * @brief This function handles SysTick Handler. - * @param None - * @retval None - */ -void SysTick_Handler(void) -{ - HAL_IncTick(); -} - -/******************************************************************************/ -/* STM32L4xx Peripherals Interrupt Handlers */ -/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ -/* available peripheral interrupt handler's name please refer to the startup */ -/* file (startup_stm32l4xx.s). */ -/******************************************************************************/ - - -/** - * @brief This function handles USB-On-The-Go FS global interrupt request. - * @param None - * @retval None - */ -void OTG_FS_IRQHandler(void) -{ - HAL_HCD_IRQHandler(&hhcd); -} - -/** - * @brief This function handles External lines 15 to 10 interrupt request. - * @param None - * @retval None - */ -void EXTI15_10_IRQHandler(void) -{ - HAL_GPIO_EXTI_IRQHandler(USER_BUTTON_PIN); -} - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.h b/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.h deleted file mode 100644 index 8ec61f4d..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/stm32l4xx_it.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_it.h - * @author MCD Application Team - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_IT_H -#define __STM32L4xx_IT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void OTG_FS_IRQHandler(void); -void EXTI15_10_IRQHandler(void); -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/system_stm32l4xx.c b/examples/stm32cube-hal-usb-host-hid/src/system_stm32l4xx.c deleted file mode 100644 index f4189475..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/system_stm32l4xx.c +++ /dev/null @@ -1,344 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the MSI (4 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | MSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 8 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * PLLSAI1_P | NA - *----------------------------------------------------------------------------- - * PLLSAI1_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI1_R | NA - *----------------------------------------------------------------------------- - * PLLSAI2_P | NA - *----------------------------------------------------------------------------- - * PLLSAI2_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI2_R | NA - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * Copyright (c) 2009-2018 ARM Limited - STMicroelectronics. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** @addtogroup STM32L4xx_System_Private_Includes - * @{ - */ - -#include "stm32l4xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 4000000U; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ - 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000U; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= 0xEAF6FFFFU; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000U; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000U; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; - - /* Get MSI Range frequency--------------------------------------------------*/ - if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x00: /* MSI used as system clock source */ - SystemCoreClock = msirange; - break; - - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; - - switch (pllsource) - { - case 0x02: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm); - break; - - case 0x03: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm); - break; - - default: /* MSI used as PLL clock source */ - pllvco = (msirange / pllm); - break; - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - SystemCoreClock = msirange; - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/usbh_conf.c b/examples/stm32cube-hal-usb-host-hid/src/usbh_conf.c deleted file mode 100644 index 5761ca5a..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/usbh_conf.c +++ /dev/null @@ -1,482 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Src/usbh_conf.c - * @author MCD Application Team - * @brief USB Host configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2017 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" -#include "usbh_core.h" - -#define USBOTG_PPWR_GPIO_PIN GPIO_PIN_6 -#define USBOTG_PPWR_GPIO_PORT GPIOG -#define USBOTG_PPWR_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() - -HCD_HandleTypeDef hhcd; - -/******************************************************************************* - HCD BSP Routines -*******************************************************************************/ -/** - * @brief Initializes the HCD MSP. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) -{ - GPIO_InitTypeDef GPIO_InitStruct; - - /* Configure USB FS GPIOs */ - __HAL_RCC_GPIOA_CLK_ENABLE(); - - /* Configure USBOTG_PPWR GPIO */ - USBOTG_PPWR_GPIO_CLK_ENABLE(); - - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_EnableVddIO2(); - __HAL_RCC_PWR_CLK_DISABLE(); - - GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = USBOTG_PPWR_GPIO_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - HAL_GPIO_Init(USBOTG_PPWR_GPIO_PORT, &GPIO_InitStruct); - - /* Enable USB FS Clocks */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - - /* Set USBFS Interrupt to the lowest priority */ - HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0); - - /* Enable USBFS Interrupt */ - HAL_NVIC_EnableIRQ(OTG_FS_IRQn); -} - -/** - * @brief DeInitializes the HCD MSP. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) -{ - /* Disable USB FS Clocks */ - __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); -} - -/******************************************************************************* - LL Driver Callbacks (HCD -> USB Host Library) -*******************************************************************************/ - -/** - * @brief SOF callback. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) -{ - USBH_LL_IncTimer (hhcd->pData); -} - -/** - * @brief Connect callback. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) -{ - uint32_t i = 0; - - USBH_LL_Connect(hhcd->pData); - - for (i = 0; i< 200000; i ++) - { - __asm ("nop"); - } -} - -/** - * @brief Disconnect callback. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) -{ - USBH_LL_Disconnect(hhcd->pData); -} - -/** - * @brief Port Port Enabled callback. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) -{ - USBH_LL_PortEnabled(hhcd->pData); -} - -/** - * @brief Port Port Disabled callback. - * @param hhcd: HCD handle - * @retval None - */ -void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) -{ - USBH_LL_PortDisabled(hhcd->pData); -} - -/** - * @brief Notify URB state change callback. - * @param hhcd: HCD handle - * @param chnum: Channel number - * @param urb_state: URB State - * @retval None - */ -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, - HCD_URBStateTypeDef urb_state) -{ - /* To be used with OS to sync URB state with the global state machine */ -} - -/******************************************************************************* - LL Driver Interface (USB Host Library --> HCD) -*******************************************************************************/ -/** - * @brief USBH_LL_Init - * Initialize the Low Level portion of the Host driver. - * @param phost: Host handle - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_Init (USBH_HandleTypeDef *phost) -{ - /* Set the LL Driver parameters */ - hhcd.Instance = USB_OTG_FS; - hhcd.Init.Host_channels = 11; - hhcd.Init.dma_enable = 0; - hhcd.Init.low_power_enable = 0; - hhcd.Init.phy_itface = HCD_PHY_EMBEDDED; - hhcd.Init.Sof_enable = 0; - hhcd.Init.speed = HCD_SPEED_FULL; - /* Link the driver to the stack */ - hhcd.pData = phost; - phost->pData = &hhcd; - /* Initialize the LL Driver */ - HAL_HCD_Init(&hhcd); - - USBH_LL_SetTimer(phost, HAL_HCD_GetCurrentFrame(&hhcd)); - - return USBH_OK; -} - -/** - * @brief USBH_LL_DeInit - * De-Initialize the Low Level portion of the Host driver. - * @param phost: Host handle - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_DeInit (USBH_HandleTypeDef *phost) -{ - HAL_HCD_DeInit(phost->pData); - return USBH_OK; -} - -/** - * @brief USBH_LL_Start - * Start the Low Level portion of the Host driver. - * @param phost: Host handle - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_Start(USBH_HandleTypeDef *phost) -{ - HAL_HCD_Start(phost->pData); - return USBH_OK; -} - -/** - * @brief USBH_LL_Stop - * Stop the Low Level portion of the Host driver. - * @param phost: Host handle - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_Stop (USBH_HandleTypeDef *phost) -{ - HAL_HCD_Stop(phost->pData); - return USBH_OK; -} - -/** - * @brief USBH_LL_GetSpeed - * Return the USB Host Speed from the Low Level Driver. - * @param phost: Host handle - * @retval USBH Speeds - */ -USBH_SpeedTypeDef USBH_LL_GetSpeed (USBH_HandleTypeDef *phost) -{ - USBH_SpeedTypeDef speed = USBH_SPEED_FULL; - - switch (HAL_HCD_GetCurrentSpeed(phost->pData)) - { - case 1: - speed = USBH_SPEED_FULL; - break; - - case 2: - speed = USBH_SPEED_LOW; - break; - - default: - speed = USBH_SPEED_FULL; - break; - } - return speed; -} - -/** - * @brief USBH_LL_ResetPort - * Reset the Host Port of the Low Level Driver. - * @param phost: Host handle - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_ResetPort (USBH_HandleTypeDef *phost) -{ - HAL_HCD_ResetPort(phost->pData); - return USBH_OK; -} - -/** - * @brief USBH_LL_GetLastXferSize - * Return the last transferred packet size. - * @param phost: Host handle - * @param pipe: Pipe index - * @retval Packet Size - */ -uint32_t USBH_LL_GetLastXferSize (USBH_HandleTypeDef *phost, uint8_t pipe) -{ - return HAL_HCD_HC_GetXferCount(phost->pData, pipe); -} - -/** - * @brief USBH_LL_OpenPipe - * Open a pipe of the Low Level Driver. - * @param phost: Host handle - * @param pipe: Pipe index - * @param epnum: Endpoint Number - * @param dev_address: Device USB address - * @param speed: Device Speed - * @param ep_type: Endpoint Type - * @param mps: Endpoint Max Packet Size - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_OpenPipe (USBH_HandleTypeDef *phost, - uint8_t pipe, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - HAL_HCD_HC_Init(phost->pData, - pipe, - epnum, - dev_address, - speed, - ep_type, - mps); - return USBH_OK; -} - -/** - * @brief USBH_LL_ClosePipe - * Close a pipe of the Low Level Driver. - * @param phost: Host handle - * @param pipe: Pipe index - * @retval USBH Status - */ -USBH_StatusTypeDef USBH_LL_ClosePipe (USBH_HandleTypeDef *phost, uint8_t pipe) -{ - HAL_HCD_HC_Halt(phost->pData, pipe); - return USBH_OK; -} - -/** - * @brief USBH_LL_SubmitURB - * Submit a new URB to the low level driver. - * @param phost: Host handle - * @param pipe: Pipe index - * This parameter can be a value from 1 to 15 - * @param direction : Channel number - * This parameter can be one of the these values: - * 0 : Output - * 1 : Input - * @param ep_type : Endpoint Type - * This parameter can be one of the these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochronous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param token : Endpoint Type - * This parameter can be one of the these values: - * @arg 0: PID_SETUP - * @arg 1: PID_DATA - * @param pbuff : pointer to URB data - * @param length : Length of URB data - * @param do_ping : activate do ping protocol (for high speed only) - * This parameter can be one of the these values: - * 0 : do ping inactive - * 1 : do ping active - * @retval Status - */ - -USBH_StatusTypeDef USBH_LL_SubmitURB (USBH_HandleTypeDef *phost, - uint8_t pipe, - uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, - uint16_t length, - uint8_t do_ping ) -{ - HAL_HCD_HC_SubmitRequest(phost->pData, - pipe, - direction, - ep_type, - token, - pbuff, - length, - do_ping); - return USBH_OK; -} - -/** - * @brief USBH_LL_GetURBState - * Get a URB state from the low level driver. - * @param phost: Host handle - * @param pipe: Pipe index - * This parameter can be a value from 1 to 15 - * @retval URB state - * This parameter can be one of the these values: - * @arg URB_IDLE - * @arg URB_DONE - * @arg URB_NOTREADY - * @arg URB_NYET - * @arg URB_ERROR - * @arg URB_STALL - */ -USBH_URBStateTypeDef USBH_LL_GetURBState (USBH_HandleTypeDef *phost, uint8_t pipe) -{ - return (USBH_URBStateTypeDef)HAL_HCD_HC_GetURBState (phost->pData, pipe); -} - -/** - * @brief USBH_LL_DriverVBUS - * Drive VBUS. - * @param phost: Host handle - * @param state : VBUS state - * This parameter can be one of the these values: - * 0 : VBUS Active - * 1 : VBUS Inactive - * @retval Status - */ - -USBH_StatusTypeDef USBH_LL_DriverVBUS (USBH_HandleTypeDef *phost, uint8_t state) -{ - if(state == 0) - { - /* Configure Low Charge pump */ - HAL_GPIO_WritePin(USBOTG_PPWR_GPIO_PORT, USBOTG_PPWR_GPIO_PIN, GPIO_PIN_RESET); - } - else - { - /* Drive High Charge pump */ - HAL_GPIO_WritePin(USBOTG_PPWR_GPIO_PORT, USBOTG_PPWR_GPIO_PIN, GPIO_PIN_SET); - } - - HAL_Delay(200); - return USBH_OK; -} - -/** - * @brief USBH_LL_SetToggle - * Set toggle for a pipe. - * @param phost: Host handle - * @param pipe: Pipe index - * @param toggle: toggle (0/1) - * @retval Status - */ -USBH_StatusTypeDef USBH_LL_SetToggle (USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t toggle) -{ - if(hhcd.hc[pipe].ep_is_in) - { - hhcd.hc[pipe].toggle_in = toggle; - } - else - { - hhcd.hc[pipe].toggle_out = toggle; - } - return USBH_OK; -} - -/** - * @brief USBH_LL_GetToggle - * Return the current toggle of a pipe. - * @param phost: Host handle - * @param pipe: Pipe index - * @retval toggle (0/1) - */ -uint8_t USBH_LL_GetToggle (USBH_HandleTypeDef *phost, uint8_t pipe) -{ - uint8_t toggle = 0; - - if(hhcd.hc[pipe].ep_is_in) - { - toggle = hhcd.hc[pipe].toggle_in; - } - else - { - toggle = hhcd.hc[pipe].toggle_out; - } - return toggle; -} - -/** - * @brief USBH_Delay - * Delay routine for the USB Host Library - * @param Delay: Delay in ms - * @retval None - */ -void USBH_Delay (uint32_t Delay) -{ - HAL_Delay(Delay); -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/src/usbh_conf.h b/examples/stm32cube-hal-usb-host-hid/src/usbh_conf.h deleted file mode 100644 index 331157c7..00000000 --- a/examples/stm32cube-hal-usb-host-hid/src/usbh_conf.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Host/HID_Standalone/Inc/usbh_conf.h - * @author MCD Application Team - * @brief General low level driver configuration - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license SLA0044, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBH_CONF_H -#define __USBH_CONF_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" -#include -#include -#include - -/* Exported types ------------------------------------------------------------*/ -#define USBH_MAX_NUM_ENDPOINTS 2 -#define USBH_MAX_NUM_INTERFACES 2 -#define USBH_MAX_NUM_CONFIGURATION 1 -#define USBH_MAX_NUM_SUPPORTED_CLASS 1 -#define USBH_KEEP_CFG_DESCRIPTOR 0 -#define USBH_MAX_SIZE_CONFIGURATION 0x200 -#define USBH_MAX_DATA_BUFFER 0x200 -#define USBH_DEBUG_LEVEL 2 -#define USBH_USE_OS 0 - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* CMSIS OS macros */ -#if (USBH_USE_OS == 1) - #include "cmsis_os.h" - #define USBH_PROCESS_PRIO osPriorityNormal -#endif - -/* Memory management macros */ -#define USBH_malloc malloc -#define USBH_free free -#define USBH_memset memset -#define USBH_memcpy memcpy - -/* DEBUG macros */ -#if (USBH_DEBUG_LEVEL > 0) -#define USBH_UsrLog(...) printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBH_UsrLog(...) -#endif - - -#if (USBH_DEBUG_LEVEL > 1) - -#define USBH_ErrLog(...) printf("ERROR: ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBH_ErrLog(...) -#endif - -#if (USBH_DEBUG_LEVEL > 2) -#define USBH_DbgLog(...) printf("DEBUG : ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBH_DbgLog(...) -#endif - -/* Exported functions ------------------------------------------------------- */ - -#endif /* __USB_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/stm32cube-hal-usb-host-hid/test/README b/examples/stm32cube-hal-usb-host-hid/test/README deleted file mode 100644 index df5066e6..00000000 --- a/examples/stm32cube-hal-usb-host-hid/test/README +++ /dev/null @@ -1,11 +0,0 @@ - -This directory is intended for PIO Unit Testing and project tests. - -Unit Testing is a software testing method by which individual units of -source code, sets of one or more MCU program modules together with associated -control data, usage procedures, and operating procedures, are tested to -determine whether they are fit for use. Unit testing finds problems early -in the development cycle. - -More information about PIO Unit Testing: -- https://docs.platformio.org/page/plus/unit-testing.html From d2046f73c1035f9e4bae6c06006ad3976e672000 Mon Sep 17 00:00:00 2001 From: valeros Date: Mon, 28 Dec 2020 14:37:41 +0200 Subject: [PATCH 4/7] Remove default STM32Cube package Fixes platformio/platformio-core#3777 --- platform.json | 1 - 1 file changed, 1 deletion(-) diff --git a/platform.json b/platform.json index c7507027..13e31d95 100644 --- a/platform.json +++ b/platform.json @@ -56,7 +56,6 @@ "title": "Arduino" }, "stm32cube": { - "package": "framework-stm32cube", "script": "builder/frameworks/stm32cube.py", "description": "STM32Cube embedded software libraries, including: The HAL hardware abstraction layer, enabling portability between different STM32 devices via standardized API calls; The Low-Layer (LL) APIs, a light-weight, optimized, expert oriented set of APIs designed for both performance and runtime efficiency", "homepage": "https://www.st.com/en/ecosystems/stm32cube.html", From 3eedb9e90541bfc2a7e8c24293d30b464ef8b882 Mon Sep 17 00:00:00 2001 From: valeros Date: Mon, 28 Dec 2020 14:38:27 +0200 Subject: [PATCH 5/7] Update STM32Cube example with custom startup code --- .../platformio.ini | 3 +- .../src/startup_stm32f103xb.S | 362 ++++++++++++++++++ 2 files changed, 363 insertions(+), 2 deletions(-) create mode 100644 examples/stm32cube-hal-eeprom-emulation/src/startup_stm32f103xb.S diff --git a/examples/stm32cube-hal-eeprom-emulation/platformio.ini b/examples/stm32cube-hal-eeprom-emulation/platformio.ini index 1da62775..e0d2465f 100644 --- a/examples/stm32cube-hal-eeprom-emulation/platformio.ini +++ b/examples/stm32cube-hal-eeprom-emulation/platformio.ini @@ -11,6 +11,5 @@ platform = ststm32 framework = stm32cube board = nucleo_f103rb -build_flags = -Wl,-Map=system_stm32f1xx.txt +build_flags = -Wl,--fatal-warnings board_build.stm32cube.custom_system_setup = yes -; board_build.stm32cube.custom_config_header = yes \ No newline at end of file diff --git a/examples/stm32cube-hal-eeprom-emulation/src/startup_stm32f103xb.S b/examples/stm32cube-hal-eeprom-emulation/src/startup_stm32f103xb.S new file mode 100644 index 00000000..a463e880 --- /dev/null +++ b/examples/stm32cube-hal-eeprom-emulation/src/startup_stm32f103xb.S @@ -0,0 +1,362 @@ +/** + *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ + * @file startup_stm32f103xb.s + * @author MCD Application Team + * @brief STM32F103xB Devices vector table for Atollic toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_IRQHandler + .word RTC_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN1_TX_IRQHandler + .word USB_LP_CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32F10x Medium Density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN1_TX_IRQHandler + .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN1_RX0_IRQHandler + .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + From 678c480345b112ce9290f6d916cf258b9e36ed3c Mon Sep 17 00:00:00 2001 From: valeros Date: Mon, 28 Dec 2020 14:47:34 +0200 Subject: [PATCH 6/7] Fix the location of CMSIS header files // Resolve #458 --- builder/frameworks/cmsis.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builder/frameworks/cmsis.py b/builder/frameworks/cmsis.py index d4fdf47f..36b8c1e4 100644 --- a/builder/frameworks/cmsis.py +++ b/builder/frameworks/cmsis.py @@ -109,7 +109,7 @@ def prepare_startup_file(src_path): env.Append( CPPPATH=[ - os.path.join(CMSIS_DIR, "CMSIS", "Core", "Include"), + os.path.join(CMSIS_DIR, "CMSIS", "Include"), os.path.join(CMSIS_DEVICE_DIR, "Include") ], From c125f59d22a4e00ca060d3977ea998e4a64434b7 Mon Sep 17 00:00:00 2001 From: valeros Date: Wed, 30 Dec 2020 21:23:43 +0200 Subject: [PATCH 7/7] Bump version to 11.0.0 --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index 13e31d95..eb6fd0f1 100644 --- a/platform.json +++ b/platform.json @@ -18,7 +18,7 @@ "type": "git", "url": "https://github.com/platformio/platform-ststm32.git" }, - "version": "10.0.1", + "version": "11.0.0", "frameworks": { "mbed": { "package": "framework-mbed",