diff --git a/.gitignore b/.gitignore index 5da76aed..cf61c035 100644 --- a/.gitignore +++ b/.gitignore @@ -74,6 +74,13 @@ transcript vsim.wlf scripts/compile_vsim.tcl +# VCS +AN.DB +bin +ucli.key +vc_hdrs.h +scripts/compile_vcs.sh + # Verible verible* diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2b3dc8f3..e13f5004 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -36,6 +36,24 @@ compile-vsim: - work/ - modelsim.ini +compile-vcs: + stage: build + needs: + - collect-bender-sources + parallel: + matrix: + - TB_DUT: + - tb_floo_router + - tb_floo_vc_router + - tb_floo_axi_chimney + - tb_floo_nw_chimney + - tb_floo_rob + script: + - make bin/${TB_DUT}.vcs | tee compile.log 2>&1 + artifacts: + paths: + - bin/ + compile-meshes: stage: build needs: @@ -58,25 +76,29 @@ compile-meshes: paths: - work_*/ -run-vsim: +run-sim: stage: run needs: - collect-bender-sources - compile-vsim + - compile-vcs parallel: matrix: - - VSIM_TB_DUT: + - SIMULATOR: [vsim, vcs] + TB_DUT: - tb_floo_router - tb_floo_vc_router - tb_floo_axi_chimney - tb_floo_nw_chimney - tb_floo_rob script: - - make run-sim-batch | tee vsim.log 2>&1 - - 'grep "Errors: 0," vsim.log' - artifacts: - paths: - - vsim.log + - | + if [ "${SIMULATOR}" = "vsim" ]; then + make run-${SIMULATOR}-batch | tee ${SIMULATOR}.log 2>&1 + grep "Errors: 0," ${SIMULATOR}.log + else + make run-${SIMULATOR}-batch + fi run-traffic: stage: run @@ -89,11 +111,11 @@ run-traffic: matrix: - DUT: [axi_mesh, nw_mesh] ROUTE_ALGO: [xy, src, id] - TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] + TRAFFIC_TYPE: [random, hbm, shuffle, single_dest_center] TRAFFIC_RW: [read, write] script: - make jobs - - make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} WORK=work_${DUT}_${ROUTE_ALGO} | tee vsim.log 2>&1 + - make run-sim-batch TB_DUT=tb_floo_${DUT} WORK=work_${DUT}_${ROUTE_ALGO} | tee vsim.log 2>&1 - 'grep "Errors: 0," vsim.log' morty: diff --git a/Makefile b/Makefile index ff9f49bd..74ae93fa 100644 --- a/Makefile +++ b/Makefile @@ -12,9 +12,12 @@ MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST))) MKFILE_DIR := $(dir $(MKFILE_PATH)) -.PHONY: all clean +.PHONY: all clean compile-sim run-sim run-sim-batch all: compile-sim -clean: clean-sim clean-spyglass clean-jobs clean-sources +clean: clean-sim clean-spyglass clean-jobs clean-sources clean-vcs +compile-sim: compile-vsim +run-sim: run-vsim +run-sim-batch: run-vsim-batch ############ # Programs # @@ -24,6 +27,8 @@ BENDER ?= bender VSIM ?= questa-2023.4 vsim SPYGLASS ?= sg_shell VERIBLE_FMT ?= verible-verilog-format +VCS ?= vcs-2022.06 vcs +VLOGAN ?= vcs-2022.06 vlogan ##################### # Compilation Flags # @@ -35,7 +40,8 @@ BENDER_FLAGS += -t snitch_cluster BENDER_FLAGS += -t idma_test BENDER_FLAGS := $(BENDER_FLAGS) $(EXTRA_BENDER_FLAGS) -WORK ?= work +WORK ?= work +TB_DUT ?= floo_noc_router_test VLOG_ARGS += -suppress vlog-2583 VLOG_ARGS += -suppress vlog-13314 @@ -43,14 +49,20 @@ VLOG_ARGS += -suppress vlog-13233 VLOG_ARGS += -timescale \"1 ns / 1 ps\" VLOG_ARGS += -work $(WORK) -VSIM_TB_DUT ?= floo_noc_router_test - VSIM_FLAGS += -64 VSIM_FLAGS += -t 1ps VSIM_FLAGS += -sv_seed 0 VSIM_FLAGS += -quiet VSIM_FLAGS += -work $(WORK) +VLOGAN_ARGS := -assert svaext +VLOGAN_ARGS += -assert disable_cover +VLOGAN_ARGS += -timescale=1ns/1ps + +VCS_ARGS += -Mlib=$(WORK) +VCS_ARGS += -Mdir=$(WORK) +VCS_ARGS += -j 8 + # Set the job name and directory if specified ifdef JOB_NAME VSIM_FLAGS += +JOB_NAME=$(JOB_NAME) @@ -66,8 +78,8 @@ endif # Automatically open the waveform if a wave.tcl file is present VSIM_FLAGS_GUI += -do "log -r /*" VSIM_FLAGS_GUI += -voptargs=+acc -ifneq ("$(wildcard hw/tb/wave/$(VSIM_TB_DUT).wave.tcl)","") - VSIM_FLAGS_GUI += -do "source hw/tb/wave/$(VSIM_TB_DUT).wave.tcl" +ifneq ("$(wildcard hw/tb/wave/$(TB_DUT).wave.tcl)","") + VSIM_FLAGS_GUI += -do "source hw/tb/wave/$(TB_DUT).wave.tcl" endif ########### @@ -117,7 +129,7 @@ clean-jobs: # QuestaSim Simulation # ######################## -.PHONY: compile-sim run-sim run-sim-batch clean-sim +.PHONY: compile-vsim run-vsim run-vsim-batch clean-vsim scripts/compile_vsim.tcl: Bender.yml mkdir -p scripts @@ -125,21 +137,52 @@ scripts/compile_vsim.tcl: Bender.yml $(BENDER) script vsim --vlog-arg="$(VLOG_ARGS)" $(BENDER_FLAGS) | grep -v "set ROOT" >> scripts/compile_vsim.tcl echo >> scripts/compile_vsim.tcl -compile-sim: scripts/compile_vsim.tcl +compile-vsim: scripts/compile_vsim.tcl $(VSIM) -64 -c -do "source scripts/compile_vsim.tcl; quit" -run-sim: - $(VSIM) $(VSIM_FLAGS) $(VSIM_FLAGS_GUI) $(VSIM_TB_DUT) +run-vsim: + $(VSIM) $(VSIM_FLAGS) $(VSIM_FLAGS_GUI) $(TB_DUT) -run-sim-batch: - $(VSIM) -c $(VSIM_FLAGS) $(VSIM_TB_DUT) -do "run -all; quit" +run-vsim-batch: + $(VSIM) -c $(VSIM_FLAGS) $(TB_DUT) -do "run -all; quit" -clean-sim: +clean-vsim: rm -rf scripts/compile_vsim.tcl rm -rf modelsim.ini rm -rf transcript rm -rf work* +################## +# VCS Simulation # +################## + +.PHONY: compile-vcs clean-vcs run-vcs run-vcs-batch + +scripts/compile_vcs.sh: Bender.yml Bender.lock + @mkdir -p scripts + $(BENDER) script vcs --vlog-arg "\$(VLOGAN_ARGS)" $(BENDER_FLAGS) --vlogan-bin "$(VLOGAN)" > $@ + chmod +x $@ + +compile-vcs: scripts/compile_vcs.sh + $< | tee scripts/compile_vcs.log + +bin/%.vcs: scripts/compile_vcs.sh compile-vcs + mkdir -p bin + $(VCS) $(VCS_ARGS) $(VCS_PARAMS) $* -o $@ + +run-vcs run-vcs-batch: + bin/$(TB_DUT).vcs +permissive -exitstatus +permissive-off + +clean-vcs: + @rm -rf AN.DB + @rm -f scripts/compile_vcs.sh + @rm -rf bin + @rm -rf work-vcs + @rm -f ucli.key + @rm -f vc_hdrs.h + @rm -f logs/*.vcs.log + @rm -f scripts/compile_vcs.log + #################### # Spyglass Linting # #################### diff --git a/README.md b/README.md index 898c9f97..3235c2c8 100644 --- a/README.md +++ b/README.md @@ -77,7 +77,7 @@ Currently, we do not provide any open-source simulation setup. Internally, the F # Compile the sources make compile-sim # Run the simulation -make run-sim-batch VSIM_TB_DUT=tb_floo_dut +make run-sim-batch TB_DUT=tb_floo_dut ``` or in the GUI, with prepared waveforms: @@ -86,7 +86,7 @@ or in the GUI, with prepared waveforms: # Compile the sources make compile-sim # Run the simulation -make run-sim VSIM_TB_DUT=tb_floo_dut +make run-sim TB_DUT=tb_floo_dut ``` By replacing `tb_floo_dut` with the name of the testbench you want to simulate. diff --git a/hw/floo_router.sv b/hw/floo_router.sv index 449f590f..323b7be8 100644 --- a/hw/floo_router.sv +++ b/hw/floo_router.sv @@ -21,7 +21,7 @@ module floo_router parameter int unsigned IdWidth = 0, parameter type id_t = logic[IdWidth-1:0], /// Used for ID-based routing - parameter int unsigned NumAddrRules = 0, + parameter int unsigned NumAddrRules = 1, parameter type addr_rule_t = logic, /// Configuration parameters for special network topologies parameter int unsigned NumInput = NumRoutes, diff --git a/hw/floo_vc_router.sv b/hw/floo_vc_router.sv index 001b0109..642bc51e 100644 --- a/hw/floo_vc_router.sv +++ b/hw/floo_vc_router.sv @@ -55,7 +55,7 @@ module floo_vc_router import floo_pkg::*; #( parameter int unsigned IdWidth = 1, parameter type id_t = logic[IdWidth-1:0], /// Used for ID-based routing - parameter int unsigned NumAddrRules = 0, + parameter int unsigned NumAddrRules = 1, parameter type addr_rule_t = logic ) ( input logic clk_i, @@ -360,7 +360,7 @@ module floo_vc_router import floo_pkg::*; #( always_comb begin sa_local_out_valid = '0; - la_route_per_output = '0; + la_route_per_output = route_direction_e'('0); output_id_oh_sa_stage = '0; for (int out_port = 0; out_port < NumPorts; out_port++) begin : gen_transform_sa_results if (RouteAlgo == XYRouting) begin : gen_reduce_sa_global_input_size_if_xyrouting diff --git a/hw/tb/tb_floo_vc_router.sv b/hw/tb/tb_floo_vc_router.sv index 82c2aeb1..942eebbf 100644 --- a/hw/tb/tb_floo_vc_router.sv +++ b/hw/tb/tb_floo_vc_router.sv @@ -195,7 +195,7 @@ module tb_floo_vc_router; for(int port = 0; port < NumPorts; port++) begin if(expected_result_queue[port].size() != 0) begin $error("Port %0d was still expecting results:", port); - for(; 0 < expected_result_queue[port].size();) begin + while(expected_result_queue[port].size() != 0) begin exp_result = expected_result_queue[port].pop_front(); $display("Expected hdr: %p", exp_result.hdr); end diff --git a/hw/test/axi_reorder_compare.sv b/hw/test/axi_reorder_compare.sv index c8fbf106..4e84fa80 100644 --- a/hw/test/axi_reorder_compare.sv +++ b/hw/test/axi_reorder_compare.sv @@ -345,13 +345,15 @@ module axi_reorder_compare #( logic [NumSlaves-1:0][NumAxiIds-1:0][31:0] b_queue_state; logic [NumSlaves-1:0][NumAxiIds-1:0][31:0] r_queue_state; - for (genvar i = 0; i < NumSlaves; i++) begin : gen_b_queue_state - assign aw_queue_state[i] = aw_queue[i].size(); - assign w_queue_state[i] = w_queue[i].size(); - assign ar_queue_state[i] = ar_queue[i].size(); - for (genvar j = 0; j < NumAxiIds; j++) begin : gen_b_queue_state - assign b_queue_state[i][j] = b_queue[i][j].size(); - assign r_queue_state[i][j] = r_queue[i][j].size(); + always_comb begin + for (int i = 0; i < NumSlaves; i++) begin : gen_b_queue_state + aw_queue_state[i] = aw_queue[i].size(); + w_queue_state[i] = w_queue[i].size(); + ar_queue_state[i] = ar_queue[i].size(); + for (int j = 0; j < NumAxiIds; j++) begin : gen_b_queue_state + b_queue_state[i][j] = b_queue[i][j].size(); + r_queue_state[i][j] = r_queue[i][j].size(); + end end end diff --git a/hw/test/axi_reorder_remap_compare.sv b/hw/test/axi_reorder_remap_compare.sv index 686ba2b0..38d9efe1 100644 --- a/hw/test/axi_reorder_remap_compare.sv +++ b/hw/test/axi_reorder_remap_compare.sv @@ -186,21 +186,26 @@ logic [NumAxiOutIds-1:0] ar_queue_recv_empty; logic [NumAxiInIds-1:0] b_queue_empty; logic [NumAxiInIds-1:0] r_queue_empty; -assign aw_w_queue_sent_empty = (aw_w_queue_sent.size() == 0); -assign aw_w_queue_recv_empty = (aw_w_queue_recv.size() == 0); +// verilog_lint: waive-start always-ff-non-blocking +always_ff @(posedge clk_i) begin + aw_w_queue_sent_empty = (aw_w_queue_sent.size() == 0); + aw_w_queue_recv_empty = (aw_w_queue_recv.size() == 0); -for (genvar i = 0; i < NumAxiInIds; i++) begin : gen_aw_queue_sent_empty - assign aw_queue_sent_empty[i] = (aw_queue_sent[i].size() == 0); - assign w_queue_empty[i] = (w_queue[i].size() == 0); - assign ar_queue_sent_empty[i] = (ar_queue_sent[i].size() == 0); - assign b_queue_empty[i] = (b_queue[i].size() == 0); - assign r_queue_empty[i] = (r_queue[i].size() == 0); -end + for (int i = 0; i < NumAxiInIds; i++) begin : gen_aw_queue_sent_empty + aw_queue_sent_empty[i] = (aw_queue_sent[i].size() == 0); + w_queue_empty[i] = (w_queue[i].size() == 0); + ar_queue_sent_empty[i] = (ar_queue_sent[i].size() == 0); + b_queue_empty[i] = (b_queue[i].size() == 0); + r_queue_empty[i] = (r_queue[i].size() == 0); + end -for (genvar i = 0; i < NumAxiOutIds; i++) begin : gen_aw_queue_recv_empty - assign aw_queue_recv_empty[i] = (aw_queue_recv[i].size() == 0); - assign ar_queue_recv_empty[i] = (ar_queue_recv[i].size() == 0); + for (int i = 0; i < NumAxiOutIds; i++) begin : gen_aw_queue_recv_empty + aw_queue_recv_empty[i] = (aw_queue_recv[i].size() == 0); + ar_queue_recv_empty[i] = (ar_queue_recv[i].size() == 0); + end end +// verilog_lint: waive-stop always-ff-non-blocking + assign end_of_sim_o = aw_w_queue_sent_empty && aw_w_queue_recv_empty && diff --git a/hw/test/floo_test_pkg.sv b/hw/test/floo_test_pkg.sv index 32aa99ff..1e480cfc 100644 --- a/hw/test/floo_test_pkg.sv +++ b/hw/test/floo_test_pkg.sv @@ -30,8 +30,8 @@ package floo_test_pkg; XYAddrOffsetX: 16, XYAddrOffsetY: 20, IdAddrOffset: 0, - NumSamRules: 0, - NumRoutes: 0 + NumSamRules: 1, + NumRoutes: 1 }; // Common chimney parameters