diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index bfc99234..66b972e9 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -10,62 +10,6 @@ on: [push, pull_request] jobs: - ############### - # Check Clean # - ############### - check-clean: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - uses: actions/setup-python@v5 - with: - python-version: '3.10' - cache: 'pip' - - name: Install dependencies and package - run: | - python -m pip install --upgrade pip - pip install . - - name: Install bender - uses: pulp-platform/pulp-actions/bender-install@v2 - - name: Install Verible - uses: chipsalliance/verible-actions-common/install-verible@main - with: - github_token: ${{ secrets.GITHUB_TOKEN }} - - name: Make clean sources - run: | - make clean pkg-sources - - name: Check clean - run: | - git status && test -z "$(git status --porcelain)" - - ############### - # Check Stale # - ############### - check-stale: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - uses: actions/setup-python@v5 - with: - python-version: '3.10' - cache: 'pip' - - name: Install dependencies and package - run: | - python -m pip install --upgrade pip - pip install . - - name: Install bender - uses: pulp-platform/pulp-actions/bender-install@v2 - - name: Install Verible - uses: chipsalliance/verible-actions-common/install-verible@main - with: - github_token: ${{ secrets.GITHUB_TOKEN }} - - name: Make clean sources - run: | - make -B pkg-sources - - name: Check clean - run: | - git status && test -z "$(git status --porcelain)" - ##################### # Bender up-to-date # ##################### diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2b8fa989..eb6870b7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -65,7 +65,7 @@ run-traffic: JOB_NAME: mesh parallel: matrix: - - VSIM_TB_DUT: [tb_floo_dma_mesh, tb_floo_vc_dma_mesh] + - VSIM_TB_DUT: [tb_floo_dma_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center] TRAFFIC_RW: [read, write] needs: diff --git a/Bender.yml b/Bender.yml index 477fb40d..9d5f96cf 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,8 +21,6 @@ export_include_dirs: sources: # Level 0 - hw/floo_pkg.sv - - hw/floo_axi_pkg.sv - - hw/floo_narrow_wide_pkg.sv # Level 1 - hw/floo_cut.sv - hw/floo_fifo.sv @@ -36,11 +34,11 @@ sources: - hw/floo_rob_wrapper.sv - hw/floo_meta_buffer.sv # Level 2 - - hw/floo_narrow_wide_join.sv + - hw/floo_nw_join.sv - hw/floo_axi_chimney.sv - - hw/floo_narrow_wide_chimney.sv + - hw/floo_nw_chimney.sv - hw/floo_router.sv - - hw/floo_narrow_wide_router.sv + - hw/floo_nw_router.sv - target: vc_router files: @@ -56,12 +54,10 @@ sources: - hw/vc_router_util/floo_vc_assignment.sv - hw/vc_router_util/floo_vc_router_switch.sv - hw/vc_router_util/floo_vc_selection.sv - - hw/floo_vc_axi_pkg.sv - - hw/floo_vc_narrow_wide_pkg.sv # Level 2 - - hw/floo_vc_narrow_wide_chimney.sv - hw/floo_vc_router.sv - - hw/floo_vc_narrow_wide_router.sv + - hw/floo_nw_vc_chimney.sv + - hw/floo_nw_vc_router.sv - target: test include_dirs: @@ -79,11 +75,9 @@ sources: - hw/test/floo_hbm_model.sv # Level 2 - hw/tb/tb_floo_axi_chimney.sv - - hw/tb/tb_floo_narrow_wide_chimney.sv + - hw/tb/tb_floo_nw_chimney.sv - hw/tb/tb_floo_router.sv - hw/tb/tb_floo_rob.sv - - hw/tb/tb_floo_dma_chimney.sv - - hw/tb/tb_floo_dma_nw_chimney.sv - hw/tb/tb_floo_dma_mesh.sv - target: all(test, vc_router) diff --git a/Makefile b/Makefile index 72bdd4d0..ffbd74dc 100644 --- a/Makefile +++ b/Makefile @@ -72,15 +72,10 @@ endif ########### FLOOGEN ?= floogen +FLOO_CFG_DIR ?= $(MKFILE_DIR)floogen/examples +FLOOGEN_CFG ?= $(FLOO_CFG_DIR)/single_cluster.yml FLOOGEN_OUT_DIR ?= $(MKFILE_DIR)generated -FLOOGEN_PKG_OUT_DIR ?= $(MKFILE_DIR)hw -FLOOGEN_CFG_DIR ?= $(MKFILE_DIR)floogen/examples -FLOOGEN_TPL_DIR ?= $(MKFILE_DIR)floogen/templates - -FLOOGEN_PKG_CFG ?= $(shell find $(FLOOGEN_CFG_DIR) -name "*_pkg.yml") -FLOOGEN_PKG_SRC ?= $(patsubst $(FLOOGEN_CFG_DIR)/%_pkg.yml,$(FLOOGEN_PKG_OUT_DIR)/floo_%_pkg.sv,$(FLOOGEN_PKG_CFG)) -FLOOGEN_TPL ?= $(shell find $(FLOOGEN_TPL_DIR) -name "*.mako") .PHONY: install-floogen pkg-sources sources clean-sources @@ -90,12 +85,8 @@ check-floogen: install-floogen: @which $(FLOOGEN) > /dev/null || (echo "Installing floogen..." && pip install .) -pkg-sources: check-floogen $(FLOOGEN_PKG_SRC) -$(FLOOGEN_PKG_OUT_DIR)/floo_%_pkg.sv: $(FLOOGEN_CFG_DIR)/%_pkg.yml $(FLOOGEN_TPL) - $(FLOOGEN) -c $< --only-pkg --pkg-outdir $(FLOOGEN_PKG_OUT_DIR) $(FLOOGEN_ARGS) - sources: check-floogen - $(FLOOGEN) -c $(FLOOGEN_CFG) -o $(FLOOGEN_OUT_DIR) --pkg-outdir $(FLOOGEN_PKG_OUT_DIR) $(FLOOGEN_ARGS) + $(FLOOGEN) -c $(FLOOGEN_CFG) -o $(FLOOGEN_OUT_DIR) $(FLOOGEN_ARGS) clean-sources: rm -rf $(FLOOGEN_OUT_DIR) diff --git a/hw/floo_axi_chimney.sv b/hw/floo_axi_chimney.sv index bc22e016..794e939f 100644 --- a/hw/floo_axi_chimney.sv +++ b/hw/floo_axi_chimney.sv @@ -6,20 +6,17 @@ `include "common_cells/registers.svh" `include "common_cells/assertions.svh" +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" /// A bidirectional network interface for connecting AXI4 Buses to the NoC -module floo_axi_chimney - import floo_pkg::*; - import floo_axi_pkg::*; -#( - /// FlooNoC defines subordinate ports as requests that go out - /// of the NoC to AXI subordinates (i.e. memories) that return - /// a response, and manager ports as requests that come into the - /// NoC from AXI managers (i.e. cores) - /// Enable the subordinate port of the AXI4 interface - parameter bit EnSbrPort = 1'b1, - /// Enable the manager port of the AXI4 interface - parameter bit EnMgrPort = 1'b1, +module floo_axi_chimney #( + /// AXI parameter config + parameter floo_pkg::axi_cfg_t AxiCfg = '0, + /// Route config + parameter floo_pkg::route_cfg_t RouteCfg = floo_pkg::RouteDefaultCfg, + /// Chimney config + parameter floo_pkg::chimney_cfg_t ChimneyCfg = floo_pkg::ChimneyDefaultCfg, /// Atomic operation support parameter bit AtopSupport = 1'b1, /// Maximum number of oustanding Atomic transactions, @@ -27,31 +24,20 @@ module floo_axi_chimney /// Every atomic transactions needs to have a unique ID /// and one ID is reserved for non-atomic transactions parameter int unsigned MaxAtomicTxns = 1, - /// ID address offset for ID routing - parameter int unsigned MaxTxns = 32, - /// The number of unique IDs that can be used to send out - /// requests - parameter int unsigned MaxUniqueIds = 1, - /// Maximum number of outstanding requests per ID - parameter int unsigned MaxTxnsPerId = MaxTxns, - /// Type of the narrow reorder buffer - parameter rob_type_e RoBType = NoRoB, - /// Capacity of the reorder buffer - parameter int unsigned ReorderBufferSize = 32, - /// Cut timing paths of outgoing requests - parameter bit CutAx = 1'b0, - /// Cut timing paths of incoming responses - parameter bit CutRsp = 1'b1, - /// Type for implementation inputs and outputs - parameter type sram_cfg_t = logic, - /// Number of System Address Map Rules - parameter int unsigned SamNumRules = 0, - /// Type of System Address Map Rule + // All the types parameter type sam_rule_t = logic, - /// System Address Map - parameter sam_rule_t [SamNumRules-1:0] Sam = '0, - /// Number of rules in the address map - parameter int unsigned NumRoutes = 0 + parameter type hdr_t = logic, + parameter sam_rule_t [RouteCfg.SamNumRules-1:0] Sam = '0, + parameter type axi_in_req_t = logic, + parameter type axi_in_rsp_t = logic, + parameter type axi_out_req_t = logic, + parameter type axi_out_rsp_t = logic, + parameter type rob_idx_t = logic, + parameter type id_t = logic, + parameter type route_t = logic, + parameter type floo_req_t = logic, + parameter type floo_rsp_t = logic, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -65,7 +51,7 @@ module floo_axi_chimney /// Coordinates/ID of the current tile input id_t id_i, /// Routing table for the current tile - input route_t [NumRoutes-1:0] route_table_i, + input route_t [RouteCfg.NumRoutes-1:0] route_table_i, /// Output to NoC output floo_req_t floo_req_o, output floo_rsp_t floo_rsp_o, @@ -74,14 +60,27 @@ module floo_axi_chimney input floo_rsp_t floo_rsp_i ); + import floo_pkg::*; + + typedef logic [AxiCfg.AddrWidth-1:0] axi_addr_t; + typedef logic [AxiCfg.InIdWidth-1:0] axi_in_id_t; + typedef logic [AxiCfg.UserWidth-1:0] axi_user_t; + typedef logic [AxiCfg.DataWidth-1:0] axi_data_t; + typedef logic [AxiCfg.DataWidth/8-1:0] axi_strb_t; + + // (Re-) definitons of `axi_in` and `floo` types, for transport + `AXI_TYPEDEF_ALL_CT(axi, axi_req_t, axi_rsp_t, axi_addr_t, axi_in_id_t, + axi_data_t, axi_strb_t, axi_user_t) + `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi, AxiCfg, hdr_t) + // Duplicate AXI port signals to degenerate ports // in case they are not used - axi_in_req_t axi_req_in; - axi_in_rsp_t axi_rsp_out; + axi_req_t axi_req_in; + axi_rsp_t axi_rsp_out; // AX queue - axi_in_aw_chan_t axi_aw_queue; - axi_in_ar_chan_t axi_ar_queue; + axi_aw_chan_t axi_aw_queue; + axi_ar_chan_t axi_ar_queue; logic axi_aw_queue_valid_out, axi_aw_queue_ready_in; logic axi_ar_queue_valid_out, axi_ar_queue_ready_in; @@ -106,17 +105,17 @@ module floo_axi_chimney floo_axi_r_flit_t floo_axi_r; // Flit unpacking - axi_in_aw_chan_t axi_unpack_aw; - axi_in_ar_chan_t axi_unpack_ar; - axi_in_w_chan_t axi_unpack_w; - axi_in_b_chan_t axi_unpack_b; - axi_in_r_chan_t axi_unpack_r; + axi_aw_chan_t axi_unpack_aw; + axi_ar_chan_t axi_unpack_ar; + axi_w_chan_t axi_unpack_w; + axi_b_chan_t axi_unpack_b; + axi_r_chan_t axi_unpack_r; floo_req_generic_flit_t unpack_req_generic; floo_rsp_generic_flit_t unpack_rsp_generic; // Meta Buffer - axi_in_req_t axi_meta_buf_req_in; - axi_in_rsp_t axi_meta_buf_rsp_out; + axi_req_t meta_buf_req_in; + axi_rsp_t meta_buf_rsp_out; // Flit arbitration typedef enum logic {SelAw, SelW} aw_w_sel_e; @@ -124,34 +123,31 @@ module floo_axi_chimney // ID tracking typedef struct packed { - axi_in_id_t id; - logic rob_req; - rob_idx_t rob_idx; - id_t src_id; - logic atop; - } id_out_buf_t; + axi_in_id_t id; + hdr_t hdr; + } meta_buf_t; // Routing - dst_t [NumAxiChannels-1:0] dst_id; - dst_t axi_aw_id_q; + id_t [NumAxiChannels-1:0] dst_id; + id_t axi_aw_id_q; route_t [NumAxiChannels-1:0] route_out; id_t [NumAxiChannels-1:0] id_out; - id_out_buf_t aw_out_data_in, aw_out_data_out; - id_out_buf_t ar_out_data_in, ar_out_data_out; + meta_buf_t aw_out_hdr_in, aw_out_hdr_out; + meta_buf_t ar_out_hdr_in, ar_out_hdr_out; /////////////////////// // Spill registers // /////////////////////// - if (EnMgrPort) begin : gen_sbr_port + if (ChimneyCfg.EnMgrPort) begin : gen_sbr_port assign axi_req_in = axi_in_req_i; assign axi_in_rsp_o = axi_rsp_out; - if (CutAx) begin : gen_ax_cuts + if (ChimneyCfg.CutAx) begin : gen_ax_cuts spill_register #( - .T ( axi_in_aw_chan_t ) + .T ( axi_aw_chan_t ) ) i_aw_queue ( .clk_i, .rst_ni, @@ -164,7 +160,7 @@ module floo_axi_chimney ); spill_register #( - .T ( axi_in_ar_chan_t ) + .T ( axi_ar_chan_t ) ) i_ar_queue ( .clk_i, .rst_ni, @@ -186,10 +182,10 @@ module floo_axi_chimney end end else begin : gen_err_slv_port axi_err_slv #( - .AxiIdWidth ( AxiInIdWidth ), - .ATOPs ( AtopSupport ), - .axi_req_t ( axi_in_req_t ), - .axi_resp_t ( axi_in_rsp_t ) + .AxiIdWidth ( AxiCfg.InIdWidth ), + .ATOPs ( AtopSupport ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_rsp_t ) ) i_axi_err_slv ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -204,7 +200,7 @@ module floo_axi_chimney assign axi_ar_queue_valid_out = 1'b0; end - if (CutRsp) begin : gen_rsp_cuts + if (ChimneyCfg.CutRsp) begin : gen_rsp_cuts spill_register #( .T ( floo_req_chan_t ) ) i_data_req_arb ( @@ -244,7 +240,7 @@ module floo_axi_chimney /////////////////////// // AW/B RoB - axi_in_b_chan_t axi_b_rob_out, axi_b_rob_in; + axi_b_chan_t axi_b_rob_out, axi_b_rob_in; logic aw_rob_req_out; rob_idx_t aw_rob_idx_out; logic aw_rob_valid_in, aw_rob_ready_out; @@ -253,7 +249,7 @@ module floo_axi_chimney logic b_rob_valid_out, b_rob_ready_in; // AR/R RoB - axi_in_r_chan_t axi_r_rob_out, axi_r_rob_in; + axi_r_chan_t axi_r_rob_out, axi_r_rob_in; logic ar_rob_req_out; rob_idx_t ar_rob_idx_out; logic ar_rob_valid_out, ar_rob_ready_in; @@ -272,17 +268,17 @@ module floo_axi_chimney end floo_rob_wrapper #( - .RoBType ( NoRoB ), - .ReorderBufferSize ( ReorderBufferSize ), - .MaxRoTxnsPerId ( MaxTxnsPerId ), - .OnlyMetaData ( 1'b1 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_in_id_t ), - .rsp_chan_t ( axi_in_b_chan_t ), - .rsp_meta_t ( axi_in_b_chan_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfg.BRoBType ), + .RoBDepth ( ChimneyCfg.BRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfg.MaxTxnsPerId ), + .OnlyMetaData ( 1'b1 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_in_id_t ), + .rsp_chan_t ( axi_b_chan_t ), + .rsp_meta_t ( axi_b_chan_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_b_rob ( .clk_i, .rst_ni, @@ -307,50 +303,49 @@ module floo_axi_chimney .rsp_o ( axi_b_rob_out ) ); - typedef logic [AxiInDataWidth-1:0] r_rob_data_t; typedef struct packed { axi_in_id_t id; - axi_in_user_t user; + axi_user_t user; axi_pkg::resp_t resp; logic last; } r_rob_meta_t; floo_rob_wrapper #( - .RoBType ( NoRoB ), - .ReorderBufferSize ( ReorderBufferSize ), - .MaxRoTxnsPerId ( MaxTxnsPerId ), - .OnlyMetaData ( 1'b0 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_in_id_t ), - .rsp_chan_t ( axi_in_r_chan_t ), - .rsp_data_t ( r_rob_data_t ), - .rsp_meta_t ( r_rob_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfg.RRoBType ), + .RoBDepth ( ChimneyCfg.RRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfg.MaxTxnsPerId ), + .OnlyMetaData ( 1'b0 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_in_id_t ), + .rsp_chan_t ( axi_r_chan_t ), + .rsp_data_t ( axi_data_t ), + .rsp_meta_t ( r_rob_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_r_rob ( .clk_i, .rst_ni, .sram_cfg_i, - .ax_valid_i ( axi_ar_queue_valid_out ), - .ax_ready_o ( axi_ar_queue_ready_in ), - .ax_len_i ( axi_ar_queue.len ), - .ax_id_i ( axi_ar_queue.id ), - .ax_dest_i ( id_out[AxiAr] ), - .ax_valid_o ( ar_rob_valid_out ), - .ax_ready_i ( ar_rob_ready_in ), - .ax_rob_req_o ( ar_rob_req_out ), - .ax_rob_idx_o ( ar_rob_idx_out ), - .rsp_valid_i ( r_rob_valid_in ), - .rsp_ready_o ( r_rob_ready_out ), - .rsp_i ( axi_r_rob_in ), - .rsp_rob_req_i ( floo_rsp_in.axi_r.hdr.rob_req ), - .rsp_rob_idx_i ( floo_rsp_in.axi_r.hdr.rob_idx ), - .rsp_last_i ( floo_rsp_in.axi_r.r.last ), - .rsp_valid_o ( r_rob_valid_out ), - .rsp_ready_i ( r_rob_ready_in ), - .rsp_o ( axi_r_rob_out ) + .ax_valid_i ( axi_ar_queue_valid_out ), + .ax_ready_o ( axi_ar_queue_ready_in ), + .ax_len_i ( axi_ar_queue.len ), + .ax_id_i ( axi_ar_queue.id ), + .ax_dest_i ( id_out[AxiAr] ), + .ax_valid_o ( ar_rob_valid_out ), + .ax_ready_i ( ar_rob_ready_in ), + .ax_rob_req_o ( ar_rob_req_out ), + .ax_rob_idx_o ( ar_rob_idx_out ), + .rsp_valid_i ( r_rob_valid_in ), + .rsp_ready_o ( r_rob_ready_out ), + .rsp_i ( axi_r_rob_in ), + .rsp_rob_req_i ( floo_rsp_in.axi_r.hdr.rob_req ), + .rsp_rob_idx_i ( floo_rsp_in.axi_r.hdr.rob_idx ), + .rsp_last_i ( floo_rsp_in.axi_r.payload.last ), + .rsp_valid_o ( r_rob_valid_out ), + .rsp_ready_i ( r_rob_ready_in ), + .rsp_o ( axi_r_rob_out ) ); ///////////////// @@ -358,17 +353,11 @@ module floo_axi_chimney ///////////////// floo_route_comp #( - .RouteAlgo ( RouteAlgo ), - .UseIdTable ( UseIdTable ), - .XYAddrOffsetX ( XYAddrOffsetX ), - .XYAddrOffsetY ( XYAddrOffsetY ), - .IdAddrOffset ( IdAddrOffset ), - .NumAddrRules ( SamNumRules ), - .NumRoutes ( NumRoutes ), - .id_t ( id_t ), - .addr_t ( axi_in_addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) + .RouteCfg ( RouteCfg ), + .id_t ( id_t ), + .addr_t ( axi_addr_t ), + .addr_rule_t ( sam_rule_t ), + .route_t ( route_t ) ) i_floo_req_route_comp [1:0] ( .clk_i, .rst_ni, @@ -379,33 +368,31 @@ module floo_axi_chimney .route_o ( {route_out[AxiAw], route_out[AxiAr]} ), .id_o ( {id_out[AxiAw], id_out[AxiAr]} ) ); - if (RouteAlgo == SourceRouting) begin : gen_route_field + if (RouteCfg.RouteAlgo == SourceRouting) begin : gen_route_field floo_route_comp #( - .RouteAlgo ( RouteAlgo ), - .UseIdTable ( 1'b0 ), - .NumAddrRules ( SamNumRules ), - .NumRoutes ( NumRoutes ), - .id_t ( id_t ), - .addr_t ( axi_in_addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) + .RouteCfg ( RouteCfg ), + .UseIdTable ( 1'b0 ), // Overwrite RouteCfg + .id_t ( id_t ), + .addr_t ( axi_addr_t ), + .addr_rule_t ( sam_rule_t ), + .route_t ( route_t ) ) i_floo_rsp_route_comp [1:0] ( .clk_i, .rst_ni, .route_table_i, - .addr_i ( '0 ), - .addr_map_i ( '0 ), - .id_i ({aw_out_data_out.src_id, ar_out_data_out.src_id} ), - .route_o ({route_out[AxiB], route_out[AxiR]} ), - .id_o ({id_out[AxiB], id_out[AxiR]} ) + .addr_i ( '0 ), + .addr_map_i ( '0 ), + .id_i ({aw_out_hdr_out.hdr.src_id, ar_out_hdr_out.hdr.src_id} ), + .route_o ({route_out[AxiB], route_out[AxiR]} ), + .id_o ({id_out[AxiB], id_out[AxiR]} ) ); assign route_out[AxiW] = axi_aw_id_q; assign dst_id = route_out; end else begin : gen_dst_field assign dst_id[AxiAw] = id_out[AxiAw]; assign dst_id[AxiAr] = id_out[AxiAr]; - assign dst_id[AxiB] = aw_out_data_out.src_id; - assign dst_id[AxiR] = ar_out_data_out.src_id; + assign dst_id[AxiB] = aw_out_hdr_out.hdr.src_id; + assign dst_id[AxiR] = ar_out_hdr_out.hdr.src_id; assign dst_id[AxiW] = axi_aw_id_q; end `FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out && @@ -424,7 +411,7 @@ module floo_axi_chimney floo_axi_aw.hdr.last = 1'b0; floo_axi_aw.hdr.axi_ch = AxiAw; floo_axi_aw.hdr.atop = axi_aw_queue.atop != axi_pkg::ATOP_NONE; - floo_axi_aw.aw = axi_aw_queue; + floo_axi_aw.payload = axi_aw_queue; end always_comb begin @@ -435,7 +422,7 @@ module floo_axi_chimney floo_axi_w.hdr.src_id = id_i; floo_axi_w.hdr.last = axi_req_in.w.last; floo_axi_w.hdr.axi_ch = AxiW; - floo_axi_w.w = axi_req_in.w; + floo_axi_w.payload = axi_req_in.w; end always_comb begin @@ -446,33 +433,33 @@ module floo_axi_chimney floo_axi_ar.hdr.src_id = id_i; floo_axi_ar.hdr.last = 1'b1; floo_axi_ar.hdr.axi_ch = AxiAr; - floo_axi_ar.ar = axi_ar_queue; + floo_axi_ar.payload = axi_ar_queue; end always_comb begin floo_axi_b = '0; - floo_axi_b.hdr.rob_req = aw_out_data_out.rob_req; - floo_axi_b.hdr.rob_idx = aw_out_data_out.rob_idx; + floo_axi_b.hdr.rob_req = aw_out_hdr_out.hdr.rob_req; + floo_axi_b.hdr.rob_idx = aw_out_hdr_out.hdr.rob_idx; floo_axi_b.hdr.dst_id = dst_id[AxiB]; floo_axi_b.hdr.src_id = id_i; floo_axi_b.hdr.last = 1'b1; floo_axi_b.hdr.axi_ch = AxiB; - floo_axi_b.hdr.atop = aw_out_data_out.atop; - floo_axi_b.b = axi_meta_buf_rsp_out.b; - floo_axi_b.b.id = aw_out_data_out.id; + floo_axi_b.hdr.atop = aw_out_hdr_out.hdr.atop; + floo_axi_b.payload = meta_buf_rsp_out.b; + floo_axi_b.payload.id = aw_out_hdr_out.id; end always_comb begin floo_axi_r = '0; - floo_axi_r.hdr.rob_req = ar_out_data_out.rob_req; - floo_axi_r.hdr.rob_idx = ar_out_data_out.rob_idx; + floo_axi_r.hdr.rob_req = ar_out_hdr_out.hdr.rob_req; + floo_axi_r.hdr.rob_idx = ar_out_hdr_out.hdr.rob_idx; floo_axi_r.hdr.dst_id = dst_id[AxiR]; floo_axi_r.hdr.src_id = id_i; floo_axi_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts floo_axi_r.hdr.axi_ch = AxiR; - floo_axi_r.hdr.atop = ar_out_data_out.atop; - floo_axi_r.r = axi_meta_buf_rsp_out.r; - floo_axi_r.r.id = ar_out_data_out.id; + floo_axi_r.hdr.atop = ar_out_hdr_out.hdr.atop; + floo_axi_r.payload = meta_buf_rsp_out.r; + floo_axi_r.payload.id = ar_out_hdr_out.id; end always_comb begin @@ -488,17 +475,17 @@ module floo_axi_chimney axi_aw_queue_valid_out)) || (aw_w_sel_q == SelW) && axi_req_in.w_valid; assign floo_req_arb_req_in[AxiAr] = ar_rob_valid_out; - assign floo_rsp_arb_req_in[AxiB] = axi_meta_buf_rsp_out.b_valid; - assign floo_rsp_arb_req_in[AxiR] = axi_meta_buf_rsp_out.r_valid; + assign floo_rsp_arb_req_in[AxiB] = meta_buf_rsp_out.b_valid; + assign floo_rsp_arb_req_in[AxiR] = meta_buf_rsp_out.r_valid; - assign aw_rob_ready_in = floo_req_arb_gnt_out[AxiW] && (aw_w_sel_q == SelAw); - assign axi_rsp_out.w_ready = floo_req_arb_gnt_out[AxiW] && (aw_w_sel_q == SelW); - assign ar_rob_ready_in = floo_req_arb_gnt_out[AxiAr]; + assign aw_rob_ready_in = floo_req_arb_gnt_out[AxiW] && (aw_w_sel_q == SelAw); + assign axi_rsp_out.w_ready = floo_req_arb_gnt_out[AxiW] && (aw_w_sel_q == SelW); + assign ar_rob_ready_in = floo_req_arb_gnt_out[AxiAr]; - assign floo_req_arb_in[AxiW] = (aw_w_sel_q == SelAw)? floo_axi_aw : floo_axi_w; - assign floo_req_arb_in[AxiAr] = floo_axi_ar; - assign floo_rsp_arb_in[AxiB] = floo_axi_b; - assign floo_rsp_arb_in[AxiR] = floo_axi_r; + assign floo_req_arb_in[AxiW] = (aw_w_sel_q == SelAw)? floo_axi_aw : floo_axi_w; + assign floo_req_arb_in[AxiAr] = floo_axi_ar; + assign floo_rsp_arb_in[AxiB] = floo_axi_b; + assign floo_rsp_arb_in[AxiR] = floo_axi_r; /////////////////////// // FLIT ARBITRATION // @@ -545,25 +532,25 @@ module floo_axi_chimney assign b_sel_atop = is_atop_b_rsp && !b_rob_pending_q; assign r_sel_atop = is_atop_r_rsp && !r_rob_pending_q; - assign axi_unpack_aw = floo_req_in.axi_aw.aw; - assign axi_unpack_w = floo_req_in.axi_w.w; - assign axi_unpack_ar = floo_req_in.axi_ar.ar; - assign axi_unpack_r = floo_rsp_in.axi_r.r; - assign axi_unpack_b = floo_rsp_in.axi_b.b; + assign axi_unpack_aw = floo_req_in.axi_aw.payload; + assign axi_unpack_w = floo_req_in.axi_w.payload; + assign axi_unpack_ar = floo_req_in.axi_ar.payload; + assign axi_unpack_r = floo_rsp_in.axi_r.payload; + assign axi_unpack_b = floo_rsp_in.axi_b.payload; assign unpack_req_generic = floo_req_in.generic; assign unpack_rsp_generic = floo_rsp_in.generic; assign axi_valid_in[AxiAw] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAw); assign axi_valid_in[AxiW] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiW); assign axi_valid_in[AxiAr] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAr); - assign axi_valid_in[AxiB] = EnMgrPort && floo_rsp_in_valid && + assign axi_valid_in[AxiB] = ChimneyCfg.EnMgrPort && floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiB); - assign axi_valid_in[AxiR] = EnMgrPort && floo_rsp_in_valid && + assign axi_valid_in[AxiR] = ChimneyCfg.EnMgrPort && floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiR); - assign axi_ready_out[AxiAw] = axi_meta_buf_rsp_out.aw_ready; - assign axi_ready_out[AxiW] = axi_meta_buf_rsp_out.w_ready; - assign axi_ready_out[AxiAr] = axi_meta_buf_rsp_out.ar_ready; + assign axi_ready_out[AxiAw] = meta_buf_rsp_out.aw_ready; + assign axi_ready_out[AxiW] = meta_buf_rsp_out.w_ready; + assign axi_ready_out[AxiAr] = meta_buf_rsp_out.ar_ready; assign axi_ready_out[AxiB] = b_rob_ready_out || b_sel_atop && axi_req_in.b_ready; assign axi_ready_out[AxiR] = r_rob_ready_out || r_sel_atop && axi_req_in.r_ready; @@ -574,7 +561,7 @@ module floo_axi_chimney // AXI req/rsp generation // //////////////////////////// - assign axi_meta_buf_req_in ='{ + assign meta_buf_req_in ='{ aw : axi_unpack_aw, aw_valid : axi_valid_in[AxiAw], w : axi_unpack_w, @@ -585,15 +572,15 @@ module floo_axi_chimney r_ready : floo_rsp_arb_gnt_out[AxiR] }; - assign b_rob_valid_in = axi_valid_in[AxiB] && !is_atop_b_rsp; - assign r_rob_valid_in = axi_valid_in[AxiR] && !is_atop_r_rsp; - assign axi_rsp_out.b_valid = b_rob_valid_out || is_atop_b_rsp; - assign axi_rsp_out.r_valid = r_rob_valid_out || is_atop_r_rsp; - assign b_rob_ready_in = axi_req_in.b_ready && !b_sel_atop; - assign r_rob_ready_in = axi_req_in.r_ready && !r_sel_atop; + assign b_rob_valid_in = axi_valid_in[AxiB] && !is_atop_b_rsp; + assign r_rob_valid_in = axi_valid_in[AxiR] && !is_atop_r_rsp; + assign axi_rsp_out.b_valid = b_rob_valid_out || is_atop_b_rsp; + assign axi_rsp_out.r_valid = r_rob_valid_out || is_atop_r_rsp; + assign b_rob_ready_in = axi_req_in.b_ready && !b_sel_atop; + assign r_rob_ready_in = axi_req_in.r_ready && !r_sel_atop; - assign axi_b_rob_in = axi_unpack_b; - assign axi_r_rob_in = axi_unpack_r; + assign axi_b_rob_in = axi_unpack_b; + assign axi_r_rob_in = axi_unpack_r; assign axi_rsp_out.b = (b_sel_atop)? axi_unpack_b : axi_b_rob_out; assign axi_rsp_out.r = (r_sel_atop)? axi_unpack_r : axi_r_rob_out; @@ -603,62 +590,56 @@ module floo_axi_chimney assign atop_has_r_rsp = AtopSupport && axi_valid_in[AxiAw] && axi_unpack_aw.atop[axi_pkg::ATOP_R_RESP]; - assign aw_out_data_in = '{ + assign aw_out_hdr_in = '{ id: axi_unpack_aw.id, - rob_req: unpack_req_generic.hdr.rob_req, - rob_idx: unpack_req_generic.hdr.rob_idx, - src_id: unpack_req_generic.hdr.src_id, - atop: unpack_req_generic.hdr.atop + hdr: unpack_req_generic.hdr }; - assign ar_out_data_in = '{ + assign ar_out_hdr_in = '{ id: (is_atop && atop_has_r_rsp)? axi_unpack_aw.id : axi_unpack_ar.id, - rob_req: unpack_req_generic.hdr.rob_req, - rob_idx: unpack_req_generic.hdr.rob_idx, - src_id: unpack_req_generic.hdr.src_id, - atop: unpack_req_generic.hdr.atop + hdr: unpack_req_generic.hdr }; - if (EnSbrPort) begin : gen_mgr_port + if (ChimneyCfg.EnSbrPort) begin : gen_mgr_port floo_meta_buffer #( - .MaxTxns ( MaxTxns ), - .MaxUniqueIds ( MaxUniqueIds ), - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( MaxAtomicTxns ), - .buf_t ( id_out_buf_t ), - .axi_in_req_t ( axi_in_req_t ), - .axi_in_rsp_t ( axi_in_rsp_t ), - .axi_out_req_t ( axi_out_req_t ), - .axi_out_rsp_t ( axi_out_rsp_t ) + .MaxTxns ( ChimneyCfg.MaxTxns ), + .MaxUniqueIds ( ChimneyCfg.MaxUniqueIds ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .buf_t ( meta_buf_t ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ) ) i_floo_meta_buffer ( .clk_i, .rst_ni, .test_enable_i, - .axi_req_i ( axi_meta_buf_req_in ), - .axi_rsp_o ( axi_meta_buf_rsp_out ), - .axi_req_o ( axi_out_req_o ), - .axi_rsp_i ( axi_out_rsp_i ), - .aw_buf_i ( aw_out_data_in ), - .ar_buf_i ( ar_out_data_in ), - .r_buf_o ( ar_out_data_out ), - .b_buf_o ( aw_out_data_out ) + .axi_req_i ( meta_buf_req_in ), + .axi_rsp_o ( meta_buf_rsp_out ), + .axi_req_o ( axi_out_req_o ), + .axi_rsp_i ( axi_out_rsp_i ), + .aw_buf_i ( aw_out_hdr_in ), + .ar_buf_i ( ar_out_hdr_in ), + .r_buf_o ( ar_out_hdr_out ), + .b_buf_o ( aw_out_hdr_out ) ); end else begin : gen_no_mgr_port axi_err_slv #( - .AxiIdWidth ( AxiInIdWidth ), - .ATOPs ( AtopSupport ), - .axi_req_t ( axi_in_req_t ), - .axi_resp_t ( axi_in_rsp_t ) + .AxiIdWidth ( AxiCfg.InIdWidth ), + .ATOPs ( AtopSupport ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_rsp_t ) ) i_axi_err_slv ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_i ( test_enable_i ), - .slv_req_i ( axi_meta_buf_req_in ), - .slv_resp_o ( axi_meta_buf_rsp_out ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( test_enable_i ), + .slv_req_i ( meta_buf_req_in ), + .slv_resp_o ( meta_buf_rsp_out ) ); assign axi_out_req_o = '0; - assign ar_out_data_out = '0; - assign aw_out_data_out = '0; + assign ar_out_hdr_out = '0; + assign aw_out_hdr_out = '0; end // Registers @@ -667,22 +648,23 @@ module floo_axi_chimney // Multiple outstanding atomics need to use different IDs // Non-atomic transactions all use the same ID - `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**AxiOutIdWidth) + `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**AxiCfg.OutIdWidth) // If Network Interface has no subordinate port, make sure that `RoBType` is `NoRoB` - `ASSERT_INIT(NoMgrPortRobType, EnMgrPort || (RoBType == NoRoB)) + `ASSERT_INIT(NoMgrPortRobType, ChimneyCfg.EnMgrPort || (ChimneyCfg.BRoBType == NoRoB && + ChimneyCfg.RRoBType == NoRoB)) // Network Interface cannot accept any B and R responses if `EnMgrPort` is not set - `ASSERT(NoMgrPortBResponse, EnMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoMgrPortBResponse, ChimneyCfg.EnMgrPort || !(floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiB))) - `ASSERT(NoMgrPortRResponse, EnMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoMgrPortRResponse, ChimneyCfg.EnMgrPort || !(floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiR))) // Network Interface cannot accept any AW, AR and W requests if `EnSbrPort` is not set - `ASSERT(NoSbrPortAwRequest, EnSbrPort || !(floo_req_in_valid && + `ASSERT(NoSbrPortAwRequest, ChimneyCfg.EnSbrPort || !(floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAw))) - `ASSERT(NoSbrPortArRequest, EnSbrPort || !(floo_req_in_valid && + `ASSERT(NoSbrPortArRequest, ChimneyCfg.EnSbrPort || !(floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAr))) - `ASSERT(NoSbrPortWRequest, EnSbrPort || !(floo_req_in_valid && + `ASSERT(NoSbrPortWRequest, ChimneyCfg.EnSbrPort || !(floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiW))) endmodule diff --git a/hw/floo_axi_pkg.sv b/hw/floo_axi_pkg.sv deleted file mode 100644 index 76bc6f18..00000000 --- a/hw/floo_axi_pkg.sv +++ /dev/null @@ -1,179 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// This file is auto-generated. Do not edit! Edit the template file instead - -`include "axi/typedef.svh" - -package floo_axi_pkg; - - import floo_pkg::*; - - //////////////////////// - // AXI Parameters // - //////////////////////// - - typedef enum logic [2:0] { - AxiAw = 3'd0, - AxiW = 3'd1, - AxiAr = 3'd2, - AxiB = 3'd3, - AxiR = 3'd4, - NumAxiChannels = 3'd5 - } axi_ch_e; - - - localparam int unsigned AxiInAddrWidth = 32; - localparam int unsigned AxiInDataWidth = 64; - localparam int unsigned AxiInIdWidth = 3; - localparam int unsigned AxiInUserWidth = 1; - - - localparam int unsigned AxiOutAddrWidth = 32; - localparam int unsigned AxiOutDataWidth = 64; - localparam int unsigned AxiOutIdWidth = 3; - localparam int unsigned AxiOutUserWidth = 1; - - - typedef logic [31:0] axi_in_addr_t; - typedef logic [63:0] axi_in_data_t; - typedef logic [7:0] axi_in_strb_t; - typedef logic [2:0] axi_in_id_t; - typedef logic [0:0] axi_in_user_t; - `AXI_TYPEDEF_ALL_CT(axi_in, axi_in_req_t, axi_in_rsp_t, axi_in_addr_t, axi_in_id_t, axi_in_data_t, - axi_in_strb_t, axi_in_user_t) - - - typedef logic [31:0] axi_out_addr_t; - typedef logic [63:0] axi_out_data_t; - typedef logic [7:0] axi_out_strb_t; - typedef logic [2:0] axi_out_id_t; - typedef logic [0:0] axi_out_user_t; - `AXI_TYPEDEF_ALL_CT(axi_out, axi_out_req_t, axi_out_rsp_t, axi_out_addr_t, axi_out_id_t, - axi_out_data_t, axi_out_strb_t, axi_out_user_t) - - - - ///////////////////////// - // Header Typedefs // - ///////////////////////// - - localparam route_algo_e RouteAlgo = XYRouting; - localparam bit UseIdTable = 1'b0; - localparam int unsigned NumXBits = 3; - localparam int unsigned NumYBits = 3; - localparam int unsigned XYAddrOffsetX = 16; - localparam int unsigned XYAddrOffsetY = 19; - localparam int unsigned IdAddrOffset = 0; - - - typedef logic [0:0] rob_idx_t; - typedef logic [0:0] port_id_t; - typedef logic [2:0] x_bits_t; - typedef logic [2:0] y_bits_t; - typedef struct packed { - x_bits_t x; - y_bits_t y; - port_id_t port_id; - } id_t; - - typedef logic route_t; - typedef id_t dst_t; - - - typedef struct packed { - logic rob_req; - rob_idx_t rob_idx; - dst_t dst_id; - id_t src_id; - logic last; - logic atop; - axi_ch_e axi_ch; - } hdr_t; - - - - //////////////////////// - // Flits Typedefs // - //////////////////////// - - typedef struct packed { - hdr_t hdr; - axi_in_aw_chan_t aw; - logic [2:0] rsvd; - } floo_axi_aw_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_w_chan_t w; - } floo_axi_w_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_b_chan_t b; - logic [64:0] rsvd; - } floo_axi_b_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_ar_chan_t ar; - logic [8:0] rsvd; - } floo_axi_ar_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_r_chan_t r; - } floo_axi_r_flit_t; - - typedef logic [73:0] floo_req_payload_t; - typedef struct packed { - hdr_t hdr; - floo_req_payload_t payload; - } floo_req_generic_flit_t; - - typedef logic [70:0] floo_rsp_payload_t; - typedef struct packed { - hdr_t hdr; - floo_rsp_payload_t payload; - } floo_rsp_generic_flit_t; - - - - ////////////////////////// - // Channel Typedefs // - ////////////////////////// - - typedef union packed { - floo_axi_aw_flit_t axi_aw; - floo_axi_w_flit_t axi_w; - floo_axi_ar_flit_t axi_ar; - floo_req_generic_flit_t generic; - } floo_req_chan_t; - - typedef union packed { - floo_axi_b_flit_t axi_b; - floo_axi_r_flit_t axi_r; - floo_rsp_generic_flit_t generic; - } floo_rsp_chan_t; - - - - /////////////////////// - // Link Typedefs // - /////////////////////// - - typedef struct packed { - logic valid; - logic ready; - floo_req_chan_t req; - } floo_req_t; - - typedef struct packed { - logic valid; - logic ready; - floo_rsp_chan_t rsp; - } floo_rsp_t; - - -endpackage diff --git a/hw/floo_mesh.sv b/hw/floo_mesh.sv index fe6412c7..fd2158be 100644 --- a/hw/floo_mesh.sv +++ b/hw/floo_mesh.sv @@ -104,7 +104,7 @@ import floo_pkg::*; .NumRoutes ( 5 ), .flit_t ( flit_t ), .RouteAlgo ( RouteAlgo ), - .ChannelFifoDepth( 2 ), + .InFifoDepth( 2 ), .IdWidth ( $bits(xy_id_t) ), .id_t ( xy_id_t ), .addr_rule_t ( logic ), diff --git a/hw/floo_mesh_ruche.sv b/hw/floo_mesh_ruche.sv index 39b50d50..5edd34bd 100644 --- a/hw/floo_mesh_ruche.sv +++ b/hw/floo_mesh_ruche.sv @@ -156,7 +156,7 @@ module floo_mesh_ruche .NumRoutes ( NumRoutes ), .flit_t ( flit_t ), .RouteAlgo ( RouteAlgo ), - .ChannelFifoDepth( 2 ), + .InFifoDepth( 2 ), .IdWidth ( $bits(xy_id_t) ), .id_t ( xy_id_t ), .addr_rule_t ( logic ), diff --git a/hw/floo_narrow_wide_pkg.sv b/hw/floo_narrow_wide_pkg.sv index 90b060cb..2cb6db34 100644 --- a/hw/floo_narrow_wide_pkg.sv +++ b/hw/floo_narrow_wide_pkg.sv @@ -97,25 +97,17 @@ package floo_narrow_wide_pkg; // Header Typedefs // ///////////////////////// - localparam route_algo_e RouteAlgo = XYRouting; - localparam bit UseIdTable = 1'b0; - localparam int unsigned NumXBits = 3; - localparam int unsigned NumYBits = 3; - localparam int unsigned XYAddrOffsetX = 16; - localparam int unsigned XYAddrOffsetY = 19; + localparam route_algo_e RouteAlgo = IdTable; + localparam bit UseIdTable = 1'b1; + localparam int unsigned NumIdBits = 3; + localparam int unsigned XYAddrOffsetX = 0; + localparam int unsigned XYAddrOffsetY = 0; localparam int unsigned IdAddrOffset = 0; typedef logic [0:0] rob_idx_t; typedef logic [0:0] port_id_t; - typedef logic [2:0] x_bits_t; - typedef logic [2:0] y_bits_t; - typedef struct packed { - x_bits_t x; - y_bits_t y; - port_id_t port_id; - } id_t; - + typedef logic [2:0] id_t; typedef logic route_t; typedef id_t dst_t; diff --git a/hw/floo_narrow_wide_chimney.sv b/hw/floo_nw_chimney.sv similarity index 70% rename from hw/floo_narrow_wide_chimney.sv rename to hw/floo_nw_chimney.sv index f8c00c71..1121998d 100644 --- a/hw/floo_narrow_wide_chimney.sv +++ b/hw/floo_nw_chimney.sv @@ -6,24 +6,19 @@ `include "common_cells/registers.svh" `include "common_cells/assertions.svh" +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" /// A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC -module floo_narrow_wide_chimney - import floo_pkg::*; - import floo_narrow_wide_pkg::*; -#( - /// FlooNoC defines subordinate ports as requests that go out - /// of the NoC to AXI subordinates (i.e. memories) that return - /// a response, and manager ports as requests that come into the - /// NoC from AXI managers (i.e. cores) - /// Enable the subordinate port of the Narrow AXI4 interface - parameter bit EnNarrowSbrPort = 1'b1, - /// Enable the manager port of the Narrow AXI4 interface - parameter bit EnNarrowMgrPort = 1'b1, - /// Enable the subordinate port of the Wide AXI4 interface - parameter bit EnWideSbrPort = 1'b1, - /// Enable the manager port of the Wide AXI4 interface - parameter bit EnWideMgrPort = 1'b1, +module floo_nw_chimney #( + /// AXI parameter config + parameter floo_pkg::axi_cfg_t AxiCfgN = '0, + parameter floo_pkg::axi_cfg_t AxiCfgW = '0, + // Chimney configs + parameter floo_pkg::chimney_cfg_t ChimneyCfgN = floo_pkg::ChimneyDefaultCfg, + parameter floo_pkg::chimney_cfg_t ChimneyCfgW = floo_pkg::ChimneyDefaultCfg, + /// Route config + parameter floo_pkg::route_cfg_t RouteCfg = floo_pkg::RouteDefaultCfg, /// Atomic operation support, currently only implemented for /// the narrow network! parameter bit AtopSupport = 1'b1, @@ -32,42 +27,25 @@ module floo_narrow_wide_chimney /// Every atomic transactions needs to have a unique ID /// and one ID is reserved for non-atomic transactions parameter int unsigned MaxAtomicTxns = 1, - /// Number of maximum oustanding requests on the narrow network - parameter int unsigned NarrowMaxTxns = 32, - /// Number of maximum oustanding requests on the wide network - parameter int unsigned WideMaxTxns = 32, - /// The number of unique IDs that can be used to send out - /// requests on the narrow network - parameter int unsigned NarrowMaxUniqueIds = 1, - /// The number of unique IDs that can be used to send out - /// requests on the wide network - parameter int unsigned WideMaxUniqueIds = 1, - /// Maximum number of outstanding requests per ID on the narrow network - parameter int unsigned NarrowMaxTxnsPerId = NarrowMaxTxns, - /// Maximum number of outstanding requests per ID on the wide network - parameter int unsigned WideMaxTxnsPerId = WideMaxTxns, - /// Type of the narrow reorder buffer - parameter rob_type_e NarrowRoBType = NoRoB, - /// Type of the wide reorder buffer - parameter rob_type_e WideRoBType = NoRoB, - /// Capacity of the narrow reorder buffers - parameter int unsigned NarrowReorderBufferSize = 256, - /// Capacity of the wide reorder buffers - parameter int unsigned WideReorderBufferSize = 256, - /// Cut timing paths of outgoing requests to the NoC - parameter bit CutAx = 1'b1, - /// Cut timing paths of incoming responses from the NoC - parameter bit CutRsp = 1'b1, /// Type for implementation inputs and outputs - parameter type sram_cfg_t = logic, - /// Number of System Address Map Rules - parameter int unsigned SamNumRules = 0, - /// Type of System Address Map Rule - parameter type sam_rule_t = logic, - /// System Address Map - parameter sam_rule_t [SamNumRules-1:0] Sam = '0, - /// Number of routes in the routing table - parameter int unsigned NumRoutes = 0 + parameter type sam_rule_t = logic, + parameter type hdr_t = logic, + parameter sam_rule_t [RouteCfg.SamNumRules-1:0] Sam = '0, + parameter type axi_narrow_in_req_t = logic, + parameter type axi_narrow_in_rsp_t = logic, + parameter type axi_narrow_out_req_t = logic, + parameter type axi_narrow_out_rsp_t = logic, + parameter type axi_wide_in_req_t = logic, + parameter type axi_wide_in_rsp_t = logic, + parameter type axi_wide_out_req_t = logic, + parameter type axi_wide_out_rsp_t = logic, + parameter type rob_idx_t = logic, + parameter type id_t = logic, + parameter type route_t = logic, + parameter type floo_req_t = logic, + parameter type floo_rsp_t = logic, + parameter type floo_wide_t = logic, + parameter type sram_cfg_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -85,7 +63,7 @@ module floo_narrow_wide_chimney /// Coordinates/ID of the current tile input id_t id_i, /// Routing table for the current tile - input route_t [NumRoutes-1:0] route_table_i, + input route_t [RouteCfg.NumRoutes-1:0] route_table_i, /// Output to NoC output floo_req_t floo_req_o, output floo_rsp_t floo_rsp_o, @@ -96,18 +74,37 @@ module floo_narrow_wide_chimney input floo_wide_t floo_wide_i ); + import floo_pkg::*; + + typedef logic [AxiCfgN.AddrWidth-1:0] axi_addr_t; + typedef logic [AxiCfgN.InIdWidth-1:0] axi_narrow_in_id_t; + typedef logic [AxiCfgN.UserWidth-1:0] axi_narrow_user_t; + typedef logic [AxiCfgN.DataWidth-1:0] axi_narrow_data_t; + typedef logic [AxiCfgN.DataWidth/8-1:0] axi_narrow_strb_t; + typedef logic [AxiCfgW.InIdWidth-1:0] axi_wide_in_id_t; + typedef logic [AxiCfgW.UserWidth-1:0] axi_wide_user_t; + typedef logic [AxiCfgW.DataWidth-1:0] axi_wide_data_t; + typedef logic [AxiCfgW.DataWidth/8-1:0] axi_wide_strb_t; + + // (Re-) definitons of `axi_in` and `floo` types, for transport + `AXI_TYPEDEF_ALL_CT(axi_narrow, axi_narrow_req_t, axi_narrow_rsp_t, axi_addr_t, + axi_narrow_in_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_narrow_user_t) + `AXI_TYPEDEF_ALL_CT(axi_wide, axi_wide_req_t, axi_wide_rsp_t, axi_addr_t, + axi_wide_in_id_t, axi_wide_data_t, axi_wide_strb_t, axi_wide_user_t) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow, axi_wide, AxiCfgN, AxiCfgW, hdr_t) + // Duplicate AXI port signals to degenerate ports // in case they are not used - axi_narrow_in_req_t axi_narrow_req_in; - axi_narrow_in_rsp_t axi_narrow_rsp_out; - axi_wide_in_req_t axi_wide_req_in; - axi_wide_in_rsp_t axi_wide_rsp_out; + axi_narrow_req_t axi_narrow_req_in; + axi_narrow_rsp_t axi_narrow_rsp_out; + axi_wide_req_t axi_wide_req_in; + axi_wide_rsp_t axi_wide_rsp_out; // AX queue - axi_narrow_in_aw_chan_t axi_narrow_aw_queue; - axi_narrow_in_ar_chan_t axi_narrow_ar_queue; - axi_wide_in_aw_chan_t axi_wide_aw_queue; - axi_wide_in_ar_chan_t axi_wide_ar_queue; + axi_narrow_aw_chan_t axi_narrow_aw_queue; + axi_narrow_ar_chan_t axi_narrow_ar_queue; + axi_wide_aw_chan_t axi_wide_aw_queue; + axi_wide_ar_chan_t axi_wide_ar_queue; logic axi_narrow_aw_queue_valid_out, axi_narrow_aw_queue_ready_in; logic axi_narrow_ar_queue_valid_out, axi_narrow_ar_queue_ready_in; logic axi_wide_aw_queue_valid_out, axi_wide_aw_queue_ready_in; @@ -126,19 +123,19 @@ module floo_narrow_wide_chimney floo_wide_chan_t floo_wide_in; logic floo_req_in_valid, floo_rsp_in_valid, floo_wide_in_valid; logic floo_req_out_ready, floo_rsp_out_ready, floo_wide_out_ready; - logic [NumAxiChannels-1:0] axi_valid_in, axi_ready_out; + logic [NumNWAxiChannels-1:0] axi_valid_in, axi_ready_out; // Flit packing - floo_narrow_aw_flit_t floo_narrow_aw; - floo_narrow_ar_flit_t floo_narrow_ar; - floo_narrow_w_flit_t floo_narrow_w; - floo_narrow_b_flit_t floo_narrow_b; - floo_narrow_r_flit_t floo_narrow_r; - floo_wide_aw_flit_t floo_wide_aw; - floo_wide_ar_flit_t floo_wide_ar; - floo_wide_w_flit_t floo_wide_w; - floo_wide_b_flit_t floo_wide_b; - floo_wide_r_flit_t floo_wide_r; + floo_axi_narrow_aw_flit_t floo_narrow_aw; + floo_axi_narrow_ar_flit_t floo_narrow_ar; + floo_axi_narrow_w_flit_t floo_narrow_w; + floo_axi_narrow_b_flit_t floo_narrow_b; + floo_axi_narrow_r_flit_t floo_narrow_r; + floo_axi_wide_aw_flit_t floo_wide_aw; + floo_axi_wide_ar_flit_t floo_wide_ar; + floo_axi_wide_w_flit_t floo_wide_w; + floo_axi_wide_b_flit_t floo_wide_b; + floo_axi_wide_r_flit_t floo_wide_r; // Flit arbitration typedef enum logic {SelAw, SelW} aw_w_sel_e; @@ -146,16 +143,16 @@ module floo_narrow_wide_chimney aw_w_sel_e wide_aw_w_sel_q, wide_aw_w_sel_d; // Flit unpacking - axi_narrow_in_aw_chan_t axi_narrow_unpack_aw; - axi_narrow_in_w_chan_t axi_narrow_unpack_w; - axi_narrow_in_b_chan_t axi_narrow_unpack_b; - axi_narrow_in_ar_chan_t axi_narrow_unpack_ar; - axi_narrow_in_r_chan_t axi_narrow_unpack_r; - axi_wide_in_aw_chan_t axi_wide_unpack_aw; - axi_wide_in_w_chan_t axi_wide_unpack_w; - axi_wide_in_b_chan_t axi_wide_unpack_b; - axi_wide_in_ar_chan_t axi_wide_unpack_ar; - axi_wide_in_r_chan_t axi_wide_unpack_r; + axi_narrow_aw_chan_t axi_narrow_unpack_aw; + axi_narrow_w_chan_t axi_narrow_unpack_w; + axi_narrow_b_chan_t axi_narrow_unpack_b; + axi_narrow_ar_chan_t axi_narrow_unpack_ar; + axi_narrow_r_chan_t axi_narrow_unpack_r; + axi_wide_aw_chan_t axi_wide_unpack_aw; + axi_wide_w_chan_t axi_wide_unpack_w; + axi_wide_b_chan_t axi_wide_unpack_b; + axi_wide_ar_chan_t axi_wide_unpack_ar; + axi_wide_r_chan_t axi_wide_unpack_r; floo_req_generic_flit_t floo_req_unpack_generic; floo_rsp_generic_flit_t floo_rsp_unpack_generic; floo_wide_generic_flit_t floo_wide_unpack_generic; @@ -169,43 +166,38 @@ module floo_narrow_wide_chimney // ID tracking typedef struct packed { axi_narrow_in_id_t id; - logic rob_req; - rob_idx_t rob_idx; - id_t src_id; - logic atop; - } narrow_id_out_buf_t; + hdr_t hdr; + } narrow_meta_buf_t; typedef struct packed { axi_wide_in_id_t id; - logic rob_req; - rob_idx_t rob_idx; - id_t src_id; - } wide_id_out_buf_t; + hdr_t hdr; + } wide_meta_buf_t; // Routing - dst_t [NumAxiChannels-1:0] dst_id; - dst_t narrow_aw_id_q, wide_aw_id_q; - route_t [NumAxiChannels-1:0] route_out; - id_t [NumAxiChannels-1:0] id_out; + id_t [NumNWAxiChannels-1:0] dst_id; + id_t narrow_aw_id_q, wide_aw_id_q; + route_t [NumNWAxiChannels-1:0] route_out; + id_t [NumNWAxiChannels-1:0] id_out; - narrow_id_out_buf_t narrow_aw_out_data_in, narrow_aw_out_data_out; - narrow_id_out_buf_t narrow_ar_out_data_in, narrow_ar_out_data_out; - wide_id_out_buf_t wide_aw_out_data_in, wide_aw_out_data_out; - wide_id_out_buf_t wide_ar_out_data_in, wide_ar_out_data_out; + narrow_meta_buf_t narrow_aw_buf_hdr_in, narrow_aw_buf_hdr_out; + narrow_meta_buf_t narrow_ar_buf_hdr_in, narrow_ar_buf_hdr_out; + wide_meta_buf_t wide_aw_buf_hdr_in, wide_aw_buf_hdr_out; + wide_meta_buf_t wide_ar_buf_hdr_in, wide_ar_buf_hdr_out; /////////////////////// // Spill registers // /////////////////////// - if (EnNarrowMgrPort) begin : gen_narrow_sbr_port + if (ChimneyCfgN.EnMgrPort) begin : gen_narrow_sbr_port assign axi_narrow_req_in = axi_narrow_in_req_i; assign axi_narrow_in_rsp_o = axi_narrow_rsp_out; - if (CutAx) begin : gen_ax_cuts + if (ChimneyCfgN.CutAx) begin : gen_ax_cuts spill_register #( - .T ( axi_narrow_in_aw_chan_t ) + .T ( axi_narrow_aw_chan_t ) ) i_narrow_aw_queue ( .clk_i, .rst_ni, @@ -218,7 +210,7 @@ module floo_narrow_wide_chimney ); spill_register #( - .T ( axi_narrow_in_ar_chan_t ) + .T ( axi_narrow_ar_chan_t ) ) i_narrow_ar_queue ( .clk_i, .rst_ni, @@ -241,7 +233,7 @@ module floo_narrow_wide_chimney end else begin : gen_narrow_err_slv_port axi_err_slv #( - .AxiIdWidth ( AxiNarrowInIdWidth ), + .AxiIdWidth ( AxiCfgN.InIdWidth ), .ATOPs ( AtopSupport ), .axi_req_t ( axi_narrow_in_req_t ), .axi_resp_t ( axi_narrow_in_rsp_t ) @@ -259,14 +251,14 @@ module floo_narrow_wide_chimney assign axi_narrow_ar_queue_valid_out = 1'b0; end - if (EnWideMgrPort) begin : gen_wide_sbr_port + if (ChimneyCfgW.EnMgrPort) begin : gen_wide_sbr_port assign axi_wide_req_in = axi_wide_in_req_i; assign axi_wide_in_rsp_o = axi_wide_rsp_out; - if (CutAx) begin : gen_ax_cuts + if (ChimneyCfgW.CutAx) begin : gen_ax_cuts spill_register #( - .T ( axi_wide_in_aw_chan_t ) + .T ( axi_wide_aw_chan_t ) ) i_wide_aw_queue ( .clk_i, .rst_ni, @@ -279,7 +271,7 @@ module floo_narrow_wide_chimney ); spill_register #( - .T ( axi_wide_in_ar_chan_t ) + .T ( axi_wide_ar_chan_t ) ) i_wide_ar_queue ( .clk_i, .rst_ni, @@ -300,7 +292,7 @@ module floo_narrow_wide_chimney end end else begin : gen_wide_err_slv_port axi_err_slv #( - .AxiIdWidth ( AxiWideInIdWidth ), + .AxiIdWidth ( AxiCfgW.InIdWidth ), .ATOPs ( AtopSupport ), .axi_req_t ( axi_wide_in_req_t ), .axi_resp_t ( axi_wide_in_rsp_t ) @@ -318,7 +310,7 @@ module floo_narrow_wide_chimney assign axi_wide_ar_queue_valid_out = 1'b0; end - if (CutRsp) begin : gen_rsp_cuts + if (ChimneyCfgN.CutRsp && ChimneyCfgW.CutRsp) begin : gen_rsp_cuts spill_register #( .T ( floo_req_chan_t ) ) i_narrow_data_req_arb ( @@ -375,14 +367,14 @@ module floo_narrow_wide_chimney /////////////////////// // AW/B RoB - axi_narrow_in_b_chan_t axi_narrow_b_rob_out, axi_narrow_b_rob_in; + axi_narrow_b_chan_t axi_narrow_b_rob_out, axi_narrow_b_rob_in; logic narrow_aw_rob_req_out; rob_idx_t narrow_aw_rob_idx_out; logic narrow_aw_rob_valid_out, narrow_aw_rob_ready_in; logic narrow_aw_rob_valid_in, narrow_aw_rob_ready_out; logic narrow_b_rob_valid_in, narrow_b_rob_ready_out; logic narrow_b_rob_valid_out, narrow_b_rob_ready_in; - axi_wide_in_b_chan_t axi_wide_b_rob_out, axi_wide_b_rob_in; + axi_wide_b_chan_t axi_wide_b_rob_out, axi_wide_b_rob_in; logic wide_aw_rob_req_out; rob_idx_t wide_aw_rob_idx_out; logic wide_aw_rob_valid_out, wide_aw_rob_ready_in; @@ -390,13 +382,13 @@ module floo_narrow_wide_chimney logic wide_b_rob_valid_out, wide_b_rob_ready_in; // AR/R RoB - axi_narrow_in_r_chan_t axi_narrow_r_rob_out, axi_narrow_r_rob_in; + axi_narrow_r_chan_t axi_narrow_r_rob_out, axi_narrow_r_rob_in; logic narrow_ar_rob_req_out; rob_idx_t narrow_ar_rob_idx_out; logic narrow_ar_rob_valid_out, narrow_ar_rob_ready_in; logic narrow_r_rob_valid_in, narrow_r_rob_ready_out; logic narrow_r_rob_valid_out, narrow_r_rob_ready_in; - axi_wide_in_r_chan_t axi_wide_r_rob_out, axi_wide_r_rob_in; + axi_wide_r_chan_t axi_wide_r_rob_out, axi_wide_r_rob_in; logic wide_ar_rob_req_out; rob_idx_t wide_ar_rob_idx_out; logic wide_ar_rob_valid_out, wide_ar_rob_ready_in; @@ -424,17 +416,17 @@ module floo_narrow_wide_chimney end floo_rob_wrapper #( - .RoBType ( NarrowRoBType ), - .ReorderBufferSize ( NarrowReorderBufferSize ), - .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), - .OnlyMetaData ( 1'b1 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_narrow_in_id_t ), - .rsp_chan_t ( axi_narrow_in_b_chan_t ), - .rsp_meta_t ( axi_narrow_in_b_chan_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgN.BRoBType ), + .RoBDepth ( ChimneyCfgN.BRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgN.MaxTxnsPerId ), + .OnlyMetaData ( 1'b1 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_narrow_in_id_t ), + .rsp_chan_t ( axi_narrow_b_chan_t ), + .rsp_meta_t ( axi_narrow_b_chan_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_narrow_b_rob ( .clk_i, .rst_ni, @@ -467,17 +459,17 @@ module floo_narrow_wide_chimney assign wide_b_rob_last = floo_rsp_in.wide_b.hdr.last; floo_rob_wrapper #( - .RoBType ( WideRoBType ), - .ReorderBufferSize ( WideReorderBufferSize ), - .MaxRoTxnsPerId ( WideMaxTxnsPerId ), - .OnlyMetaData ( 1'b1 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_wide_in_id_t ), - .rsp_chan_t ( axi_wide_in_b_chan_t ), - .rsp_meta_t ( axi_wide_in_b_chan_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgW.BRoBType ), + .RoBDepth ( ChimneyCfgW.BRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgW.MaxTxnsPerId ), + .OnlyMetaData ( 1'b1 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_wide_in_id_t ), + .rsp_chan_t ( axi_wide_b_chan_t ), + .rsp_meta_t ( axi_wide_b_chan_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_wide_b_rob ( .clk_i, .rst_ni, @@ -503,39 +495,39 @@ module floo_narrow_wide_chimney ); typedef struct packed { - axi_narrow_in_id_t id; - axi_narrow_in_user_t user; - axi_pkg::resp_t resp; - logic last; - } narrow_meta_t; - - typedef struct packed { - axi_wide_in_id_t id; - axi_wide_in_user_t user; + axi_narrow_in_id_t id; + axi_narrow_user_t user; axi_pkg::resp_t resp; logic last; - } wide_meta_t; + } narrow_r_rob_meta_t; + + typedef struct packed { + axi_wide_in_id_t id; + axi_wide_user_t user; + axi_pkg::resp_t resp; + logic last; + } wide_r_rob_meta_t; logic narrow_r_rob_rob_req; logic narrow_r_rob_last; rob_idx_t narrow_r_rob_rob_idx; assign narrow_r_rob_rob_req = floo_rsp_in.narrow_r.hdr.rob_req; assign narrow_r_rob_rob_idx = floo_rsp_in.narrow_r.hdr.rob_idx; - assign narrow_r_rob_last = floo_rsp_in.narrow_r.r.last; + assign narrow_r_rob_last = floo_rsp_in.narrow_r.payload.last; floo_rob_wrapper #( - .RoBType ( NarrowRoBType ), - .ReorderBufferSize ( NarrowReorderBufferSize ), - .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), - .OnlyMetaData ( 1'b0 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_narrow_in_id_t ), - .rsp_chan_t ( axi_narrow_in_r_chan_t ), - .rsp_data_t ( axi_narrow_in_data_t ), - .rsp_meta_t ( narrow_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgN.RRoBType ), + .RoBDepth ( ChimneyCfgN.RRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgN.MaxTxnsPerId ), + .OnlyMetaData ( 1'b0 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_narrow_in_id_t ), + .rsp_chan_t ( axi_narrow_r_chan_t ), + .rsp_data_t ( axi_narrow_data_t ), + .rsp_meta_t ( narrow_r_rob_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_narrow_r_rob ( .clk_i, .rst_ni, @@ -565,21 +557,21 @@ module floo_narrow_wide_chimney rob_idx_t wide_r_rob_rob_idx; assign wide_r_rob_rob_req = floo_wide_in.wide_r.hdr.rob_req; assign wide_r_rob_rob_idx = floo_wide_in.wide_r.hdr.rob_idx; - assign wide_r_rob_last = floo_wide_in.wide_r.r.last; + assign wide_r_rob_last = floo_wide_in.wide_r.payload.last; floo_rob_wrapper #( - .RoBType ( WideRoBType ), - .ReorderBufferSize ( WideReorderBufferSize ), - .MaxRoTxnsPerId ( WideMaxTxnsPerId ), - .OnlyMetaData ( 1'b0 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_wide_in_id_t ), - .rsp_chan_t ( axi_wide_in_r_chan_t ), - .rsp_data_t ( axi_wide_in_data_t ), - .rsp_meta_t ( wide_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgW.RRoBType ), + .RoBDepth ( ChimneyCfgW.RRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgW.MaxTxnsPerId ), + .OnlyMetaData ( 1'b0 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_wide_in_id_t ), + .rsp_chan_t ( axi_wide_r_chan_t ), + .rsp_data_t ( axi_wide_data_t ), + .rsp_meta_t ( wide_r_rob_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_wide_r_rob ( .clk_i, .rst_ni, @@ -608,20 +600,14 @@ module floo_narrow_wide_chimney // ROUTING // ///////////////// - typedef axi_narrow_in_addr_t addr_t; + typedef axi_addr_t addr_t; floo_route_comp #( - .RouteAlgo ( RouteAlgo ), - .UseIdTable ( UseIdTable ), - .XYAddrOffsetX ( XYAddrOffsetX ), - .XYAddrOffsetY ( XYAddrOffsetY ), - .IdAddrOffset ( IdAddrOffset ), - .NumAddrRules ( SamNumRules ), - .NumRoutes ( NumRoutes ), - .id_t ( id_t ), - .addr_t ( addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) + .RouteCfg ( RouteCfg ), + .id_t ( id_t ), + .addr_t ( addr_t ), + .addr_rule_t ( sam_rule_t ), + .route_t ( route_t ) ) i_floo_req_route_comp [3:0] ( .clk_i, .rst_ni, @@ -636,12 +622,10 @@ module floo_narrow_wide_chimney .id_o ({id_out[NarrowAw], id_out[NarrowAr],id_out[WideAw], id_out[WideAr]} ) ); - if (RouteAlgo == SourceRouting) begin : gen_route_field + if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field floo_route_comp #( - .RouteAlgo ( RouteAlgo ), - .UseIdTable ( 1'b0 ), - .NumAddrRules ( SamNumRules ), - .NumRoutes ( NumRoutes ), + .RouteCfg ( RouteCfg ), + .UseIdTable ( 1'b0 ), // Overwrite `RouteCfg` .id_t ( id_t ), .addr_t ( addr_t ), .addr_rule_t ( sam_rule_t ), @@ -653,8 +637,8 @@ module floo_narrow_wide_chimney .addr_i ( '0 ), .addr_map_i ( '0 ), .id_i ({ - narrow_aw_out_data_out.src_id, narrow_ar_out_data_out.src_id, - wide_aw_out_data_out.src_id, wide_ar_out_data_out.src_id + narrow_aw_buf_hdr_out.hdr.src_id, narrow_ar_buf_hdr_out.hdr.src_id, + wide_aw_buf_hdr_out.hdr.src_id, wide_ar_buf_hdr_out.hdr.src_id }), .route_o ({route_out[NarrowB], route_out[NarrowR], route_out[WideB], route_out[WideR]} ), .id_o ({id_out[NarrowB], id_out[NarrowR], id_out[WideB], id_out[WideR]} ) @@ -667,10 +651,10 @@ module floo_narrow_wide_chimney assign dst_id[NarrowAr] = id_out[NarrowAr]; assign dst_id[WideAw] = id_out[WideAw]; assign dst_id[WideAr] = id_out[WideAr]; - assign dst_id[NarrowB] = narrow_aw_out_data_out.src_id; - assign dst_id[NarrowR] = narrow_ar_out_data_out.src_id; - assign dst_id[WideB] = wide_aw_out_data_out.src_id; - assign dst_id[WideR] = wide_ar_out_data_out.src_id; + assign dst_id[NarrowB] = narrow_aw_buf_hdr_out.hdr.src_id; + assign dst_id[NarrowR] = narrow_ar_buf_hdr_out.hdr.src_id; + assign dst_id[WideB] = wide_aw_buf_hdr_out.hdr.src_id; + assign dst_id[WideR] = wide_ar_buf_hdr_out.hdr.src_id; assign dst_id[NarrowW] = narrow_aw_id_q; assign dst_id[WideW] = wide_aw_id_q; end @@ -693,7 +677,7 @@ module floo_narrow_wide_chimney floo_narrow_aw.hdr.last = 1'b0; // AW and W need to be sent together floo_narrow_aw.hdr.axi_ch = NarrowAw; floo_narrow_aw.hdr.atop = axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE; - floo_narrow_aw.aw = axi_narrow_aw_queue; + floo_narrow_aw.payload = axi_narrow_aw_queue; end always_comb begin @@ -704,7 +688,7 @@ module floo_narrow_wide_chimney floo_narrow_w.hdr.src_id = id_i; floo_narrow_w.hdr.last = axi_narrow_req_in.w.last; floo_narrow_w.hdr.axi_ch = NarrowW; - floo_narrow_w.w = axi_narrow_req_in.w; + floo_narrow_w.payload = axi_narrow_req_in.w; end always_comb begin @@ -715,33 +699,33 @@ module floo_narrow_wide_chimney floo_narrow_ar.hdr.src_id = id_i; floo_narrow_ar.hdr.last = 1'b1; floo_narrow_ar.hdr.axi_ch = NarrowAr; - floo_narrow_ar.ar = axi_narrow_ar_queue; + floo_narrow_ar.payload = axi_narrow_ar_queue; end always_comb begin floo_narrow_b = '0; - floo_narrow_b.hdr.rob_req = narrow_aw_out_data_out.rob_req; - floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_out_data_out.rob_idx); + floo_narrow_b.hdr.rob_req = narrow_aw_buf_hdr_out.hdr.rob_req; + floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_buf_hdr_out.hdr.rob_idx); floo_narrow_b.hdr.dst_id = dst_id[NarrowB]; floo_narrow_b.hdr.src_id = id_i; floo_narrow_b.hdr.last = 1'b1; floo_narrow_b.hdr.axi_ch = NarrowB; - floo_narrow_b.hdr.atop = narrow_aw_out_data_out.atop; - floo_narrow_b.b = axi_narrow_meta_buf_rsp_out.b; - floo_narrow_b.b.id = narrow_aw_out_data_out.id; + floo_narrow_b.hdr.atop = narrow_aw_buf_hdr_out.hdr.atop; + floo_narrow_b.payload = axi_narrow_meta_buf_rsp_out.b; + floo_narrow_b.payload.id = narrow_aw_buf_hdr_out.id; end always_comb begin floo_narrow_r = '0; - floo_narrow_r.hdr.rob_req = narrow_ar_out_data_out.rob_req; - floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_out_data_out.rob_idx); + floo_narrow_r.hdr.rob_req = narrow_ar_buf_hdr_out.hdr.rob_req; + floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_buf_hdr_out.hdr.rob_idx); floo_narrow_r.hdr.dst_id = dst_id[NarrowR]; floo_narrow_r.hdr.src_id = id_i; floo_narrow_r.hdr.axi_ch = NarrowR; floo_narrow_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts - floo_narrow_r.hdr.atop = narrow_ar_out_data_out.atop; - floo_narrow_r.r = axi_narrow_meta_buf_rsp_out.r; - floo_narrow_r.r.id = narrow_ar_out_data_out.id; + floo_narrow_r.hdr.atop = narrow_ar_buf_hdr_out.hdr.atop; + floo_narrow_r.payload = axi_narrow_meta_buf_rsp_out.r; + floo_narrow_r.payload.id = narrow_ar_buf_hdr_out.id; end always_comb begin @@ -752,7 +736,7 @@ module floo_narrow_wide_chimney floo_wide_aw.hdr.src_id = id_i; floo_wide_aw.hdr.last = 1'b0; // AW and W need to be sent together floo_wide_aw.hdr.axi_ch = WideAw; - floo_wide_aw.aw = axi_wide_aw_queue; + floo_wide_aw.payload = axi_wide_aw_queue; end always_comb begin @@ -763,7 +747,7 @@ module floo_narrow_wide_chimney floo_wide_w.hdr.src_id = id_i; floo_wide_w.hdr.last = axi_wide_req_in.w.last; floo_wide_w.hdr.axi_ch = WideW; - floo_wide_w.w = axi_wide_req_in.w; + floo_wide_w.payload = axi_wide_req_in.w; end always_comb begin @@ -774,31 +758,31 @@ module floo_narrow_wide_chimney floo_wide_ar.hdr.src_id = id_i; floo_wide_ar.hdr.last = 1'b1; floo_wide_ar.hdr.axi_ch = WideAr; - floo_wide_ar.ar = axi_wide_ar_queue; + floo_wide_ar.payload = axi_wide_ar_queue; end always_comb begin floo_wide_b = '0; - floo_wide_b.hdr.rob_req = wide_aw_out_data_out.rob_req; - floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_out_data_out.rob_idx); + floo_wide_b.hdr.rob_req = wide_aw_buf_hdr_out.hdr.rob_req; + floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_buf_hdr_out.hdr.rob_idx); floo_wide_b.hdr.dst_id = dst_id[WideB]; floo_wide_b.hdr.src_id = id_i; floo_wide_b.hdr.last = 1'b1; floo_wide_b.hdr.axi_ch = WideB; - floo_wide_b.b = axi_wide_meta_buf_rsp_out.b; - floo_wide_b.b.id = wide_aw_out_data_out.id; + floo_wide_b.payload = axi_wide_meta_buf_rsp_out.b; + floo_wide_b.payload.id = wide_aw_buf_hdr_out.id; end always_comb begin floo_wide_r = '0; - floo_wide_r.hdr.rob_req = wide_ar_out_data_out.rob_req; - floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_out_data_out.rob_idx); + floo_wide_r.hdr.rob_req = wide_ar_buf_hdr_out.hdr.rob_req; + floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_buf_hdr_out.hdr.rob_idx); floo_wide_r.hdr.dst_id = dst_id[WideR]; floo_wide_r.hdr.src_id = id_i; floo_wide_r.hdr.axi_ch = WideR; floo_wide_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts - floo_wide_r.r = axi_wide_meta_buf_rsp_out.r; - floo_wide_r.r.id = wide_ar_out_data_out.id; + floo_wide_r.payload = axi_wide_meta_buf_rsp_out.r; + floo_wide_r.payload.id = wide_ar_buf_hdr_out.id; end always_comb begin @@ -926,16 +910,16 @@ module floo_narrow_wide_chimney assign b_sel_atop = is_atop_b_rsp && !b_rob_pending_q; assign r_sel_atop = is_atop_r_rsp && !r_rob_pending_q; - assign axi_narrow_unpack_aw = floo_req_in.narrow_aw.aw; - assign axi_narrow_unpack_w = floo_req_in.narrow_w.w; - assign axi_narrow_unpack_ar = floo_req_in.narrow_ar.ar; - assign axi_narrow_unpack_r = floo_rsp_in.narrow_r.r; - assign axi_narrow_unpack_b = floo_rsp_in.narrow_b.b; - assign axi_wide_unpack_aw = floo_wide_in.wide_aw.aw; - assign axi_wide_unpack_w = floo_wide_in.wide_w.w; - assign axi_wide_unpack_ar = floo_req_in.wide_ar.ar; - assign axi_wide_unpack_r = floo_wide_in.wide_r.r; - assign axi_wide_unpack_b = floo_rsp_in.wide_b.b; + assign axi_narrow_unpack_aw = floo_req_in.narrow_aw.payload; + assign axi_narrow_unpack_w = floo_req_in.narrow_w.payload; + assign axi_narrow_unpack_ar = floo_req_in.narrow_ar.payload; + assign axi_narrow_unpack_r = floo_rsp_in.narrow_r.payload; + assign axi_narrow_unpack_b = floo_rsp_in.narrow_b.payload; + assign axi_wide_unpack_aw = floo_wide_in.wide_aw.payload; + assign axi_wide_unpack_w = floo_wide_in.wide_w.payload; + assign axi_wide_unpack_ar = floo_req_in.wide_ar.payload; + assign axi_wide_unpack_r = floo_wide_in.wide_r.payload; + assign axi_wide_unpack_b = floo_rsp_in.wide_b.payload; assign floo_req_unpack_generic = floo_req_in.generic; assign floo_rsp_unpack_generic = floo_rsp_in.generic; assign floo_wide_unpack_generic = floo_wide_in.generic; @@ -949,17 +933,17 @@ module floo_narrow_wide_chimney (floo_req_unpack_generic.hdr.axi_ch == NarrowAr); assign axi_valid_in[WideAr] = floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAr); - assign axi_valid_in[NarrowB] = EnNarrowMgrPort && floo_rsp_in_valid && + assign axi_valid_in[NarrowB] = ChimneyCfgN.EnMgrPort && floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowB); - assign axi_valid_in[NarrowR] = EnNarrowMgrPort && floo_rsp_in_valid && + assign axi_valid_in[NarrowR] = ChimneyCfgN.EnMgrPort && floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowR); - assign axi_valid_in[WideB] = EnWideMgrPort && floo_rsp_in_valid && + assign axi_valid_in[WideB] = ChimneyCfgW.EnMgrPort && floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == WideB); assign axi_valid_in[WideAw] = floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideAw); assign axi_valid_in[WideW] = floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideW); - assign axi_valid_in[WideR] = EnWideMgrPort && floo_wide_in_valid && + assign axi_valid_in[WideR] = ChimneyCfgW.EnMgrPort && floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideR); assign axi_ready_out[NarrowAw] = axi_narrow_meta_buf_rsp_out.aw_ready; @@ -1035,44 +1019,34 @@ module floo_narrow_wide_chimney assign atop_has_r_rsp = AtopSupport && axi_valid_in[NarrowAw] && axi_narrow_unpack_aw.atop[axi_pkg::ATOP_R_RESP]; - assign narrow_aw_out_data_in = '{ + assign narrow_aw_buf_hdr_in = '{ id: axi_narrow_unpack_aw.id, - rob_req: floo_req_in.narrow_aw.hdr.rob_req, - rob_idx: floo_req_in.narrow_aw.hdr.rob_idx, - src_id: floo_req_in.narrow_aw.hdr.src_id, - atop: floo_req_in.narrow_aw.hdr.atop + hdr: floo_req_unpack_generic.hdr }; - assign narrow_ar_out_data_in = '{ + assign narrow_ar_buf_hdr_in = '{ id: (is_atop && atop_has_r_rsp)? axi_narrow_unpack_aw.id : axi_narrow_unpack_ar.id, - rob_req: floo_req_in.narrow_ar.hdr.rob_req, - rob_idx: floo_req_in.narrow_ar.hdr.rob_idx, - src_id: floo_req_in.narrow_ar.hdr.src_id, - atop: floo_req_in.narrow_ar.hdr.atop + hdr: floo_req_unpack_generic.hdr }; - assign wide_aw_out_data_in = '{ + assign wide_aw_buf_hdr_in = '{ id: axi_wide_unpack_aw.id, - rob_req: floo_wide_in.wide_aw.hdr.rob_req, - rob_idx: floo_wide_in.wide_aw.hdr.rob_idx, - src_id: floo_wide_in.wide_aw.hdr.src_id + hdr: floo_wide_unpack_generic.hdr }; - assign wide_ar_out_data_in = '{ + assign wide_ar_buf_hdr_in = '{ id: axi_wide_unpack_ar.id, - rob_req: floo_req_in.wide_ar.hdr.rob_req, - rob_idx: floo_req_in.wide_ar.hdr.rob_idx, - src_id: floo_req_in.wide_ar.hdr.src_id + hdr: floo_req_unpack_generic.hdr }; - if (EnNarrowSbrPort) begin : gen_narrow_mgr_port + if (ChimneyCfgN.EnSbrPort) begin : gen_narrow_mgr_port floo_meta_buffer #( - .MaxTxns ( NarrowMaxTxns ), - .MaxUniqueIds ( NarrowMaxUniqueIds ), - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( MaxAtomicTxns ), - .buf_t ( narrow_id_out_buf_t ), - .axi_in_req_t ( axi_narrow_in_req_t ), - .axi_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_out_req_t ( axi_narrow_out_req_t ), - .axi_out_rsp_t ( axi_narrow_out_rsp_t ) + .MaxTxns ( ChimneyCfgN.MaxTxns ), + .MaxUniqueIds ( ChimneyCfgN.MaxUniqueIds ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .buf_t ( narrow_meta_buf_t ), + .axi_in_req_t ( axi_narrow_in_req_t ), + .axi_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_out_req_t ( axi_narrow_out_req_t ), + .axi_out_rsp_t ( axi_narrow_out_rsp_t ) ) i_narrow_meta_buffer ( .clk_i, .rst_ni, @@ -1081,17 +1055,17 @@ module floo_narrow_wide_chimney .axi_rsp_o ( axi_narrow_meta_buf_rsp_out ), .axi_req_o ( axi_narrow_out_req_o ), .axi_rsp_i ( axi_narrow_out_rsp_i ), - .aw_buf_i ( narrow_aw_out_data_in ), - .ar_buf_i ( narrow_ar_out_data_in ), - .r_buf_o ( narrow_ar_out_data_out ), - .b_buf_o ( narrow_aw_out_data_out ) + .aw_buf_i ( narrow_aw_buf_hdr_in ), + .ar_buf_i ( narrow_ar_buf_hdr_in ), + .r_buf_o ( narrow_ar_buf_hdr_out ), + .b_buf_o ( narrow_aw_buf_hdr_out ) ); end else begin : gen_no_narrow_mgr_port axi_err_slv #( - .AxiIdWidth ( AxiNarrowInIdWidth ), - .ATOPs ( AtopSupport ), - .axi_req_t ( axi_narrow_in_req_t ), - .axi_resp_t ( axi_narrow_in_rsp_t ) + .AxiIdWidth ( AxiCfgN.InIdWidth ), + .ATOPs ( AtopSupport ), + .axi_req_t ( axi_narrow_req_t ), + .axi_resp_t ( axi_narrow_rsp_t ) ) i_axi_err_slv ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -1100,21 +1074,21 @@ module floo_narrow_wide_chimney .slv_resp_o ( axi_narrow_meta_buf_rsp_out ) ); assign axi_narrow_out_req_o = '0; - assign narrow_ar_out_data_out = '0; - assign narrow_aw_out_data_out = '0; + assign narrow_ar_buf_hdr_out = '0; + assign narrow_aw_buf_hdr_out = '0; end - if (EnWideSbrPort) begin : gen_wide_mgr_port + if (ChimneyCfgW.EnSbrPort) begin : gen_wide_mgr_port floo_meta_buffer #( - .MaxTxns ( WideMaxTxns ), - .MaxUniqueIds ( WideMaxUniqueIds ), - .AtopSupport ( 1'b0 ), - .MaxAtomicTxns ( '0 ), - .buf_t ( wide_id_out_buf_t ), - .axi_in_req_t ( axi_wide_in_req_t ), - .axi_in_rsp_t ( axi_wide_in_rsp_t ), - .axi_out_req_t ( axi_wide_out_req_t ), - .axi_out_rsp_t ( axi_wide_out_rsp_t ) + .MaxTxns ( ChimneyCfgW.MaxTxns ), + .MaxUniqueIds ( ChimneyCfgW.MaxUniqueIds ), + .AtopSupport ( 1'b0 ), + .MaxAtomicTxns ( '0 ), + .buf_t ( wide_meta_buf_t ), + .axi_in_req_t ( axi_wide_in_req_t ), + .axi_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_out_req_t ( axi_wide_out_req_t ), + .axi_out_rsp_t ( axi_wide_out_rsp_t ) ) i_wide_meta_buffer ( .clk_i, .rst_ni, @@ -1123,14 +1097,14 @@ module floo_narrow_wide_chimney .axi_rsp_o ( axi_wide_meta_buf_rsp_out ), .axi_req_o ( axi_wide_out_req_o ), .axi_rsp_i ( axi_wide_out_rsp_i ), - .aw_buf_i ( wide_aw_out_data_in ), - .ar_buf_i ( wide_ar_out_data_in ), - .r_buf_o ( wide_ar_out_data_out ), - .b_buf_o ( wide_aw_out_data_out ) + .aw_buf_i ( wide_aw_buf_hdr_in ), + .ar_buf_i ( wide_ar_buf_hdr_in ), + .r_buf_o ( wide_ar_buf_hdr_out ), + .b_buf_o ( wide_aw_buf_hdr_out ) ); end else begin : gen_no_wide_mgr_port axi_err_slv #( - .AxiIdWidth ( AxiWideInIdWidth ), + .AxiIdWidth ( AxiCfgW.InIdWidth ), .ATOPs ( 1'b1 ), .axi_req_t ( axi_wide_in_req_t ), .axi_resp_t ( axi_wide_in_rsp_t ) @@ -1142,8 +1116,8 @@ module floo_narrow_wide_chimney .slv_resp_o ( axi_wide_meta_buf_rsp_out ) ); assign axi_wide_out_req_o = '0; - assign wide_ar_out_data_out = '0; - assign wide_aw_out_data_out = '0; + assign wide_ar_buf_hdr_out = '0; + assign wide_aw_buf_hdr_out = '0; end // Registers @@ -1155,18 +1129,23 @@ module floo_narrow_wide_chimney // ASSERTIONS // ///////////////// + // Check that the Address Width of the narrow and Wide interfaces are the same + `ASSERT_INIT(AddrWidthMatch, AxiCfgN.AddrWidth == AxiCfgW.AddrWidth) + + // `CutRsp` of the narrow and wide config must be the same + `ASSERT_INIT(CutRspMatch, ChimneyCfgN.CutRsp == ChimneyCfgW.CutRsp) + // Multiple outstanding atomics need to use different IDs // Non-atomic transactions all use the same ID - `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**AxiNarrowOutIdWidth) + `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**AxiCfgN.OutIdWidth) // If Network Interface has no subordinate port, make sure that `RoBType` is `NoRoB` - `ASSERT_INIT(NoNarrowMgrPortRobType, EnNarrowMgrPort || (NarrowRoBType == NoRoB)) - `ASSERT_INIT(NoWideMgrPortRobType, EnWideMgrPort || (WideRoBType == NoRoB)) - - // Check that all addresses have the same width - `ASSERT_INIT(SameAddrWidth1, AxiNarrowInAddrWidth == AxiNarrowOutAddrWidth) - `ASSERT_INIT(SameAddrWidth2, AxiWideInAddrWidth == AxiNarrowOutAddrWidth) - `ASSERT_INIT(SameAddrWidth3, AxiWideInAddrWidth == AxiWideOutAddrWidth) + `ASSERT_INIT(NoNarrowMgrPortRobType, ChimneyCfgN.EnMgrPort || + (ChimneyCfgN.BRoBType == floo_pkg::NoRoB && + ChimneyCfgN.RRoBType == floo_pkg::NoRoB)) + `ASSERT_INIT(NoWideMgrPortRobType, ChimneyCfgW.EnMgrPort || + (ChimneyCfgW.BRoBType == floo_pkg::NoRoB && + ChimneyCfgW.RRoBType == floo_pkg::NoRoB)) // Data and valid signals must be stable/asserted when ready is low `ASSERT(NarrowReqOutStableValid, floo_req_o.valid && @@ -1183,26 +1162,26 @@ module floo_narrow_wide_chimney !floo_wide_o.ready |=> floo_wide_i.valid) // Network Interface cannot accept any B and R responses if `En*MgrPort` are not set - `ASSERT(NoNarrowMgrPortBResponse, EnNarrowMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoNarrowMgrPortBResponse, ChimneyCfgN.EnMgrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowB))) - `ASSERT(NoNarrowMgrPortRResponse, EnNarrowMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoNarrowMgrPortRResponse, ChimneyCfgN.EnMgrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowR))) - `ASSERT(NoWideMgrPortBResponse, EnWideMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoWideMgrPortBResponse, ChimneyCfgW.EnMgrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == WideB))) - `ASSERT(NoWideMgrPortRResponse, EnWideMgrPort || !(floo_wide_in_valid && + `ASSERT(NoWideMgrPortRResponse, ChimneyCfgW.EnMgrPort || !(floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideR))) // Network Interface cannot accept any AW, AR and W requests if `En*SbrPort` is not set - `ASSERT(NoNarrowSbrPortAwRequest, EnNarrowSbrPort || !(floo_req_in_valid && + `ASSERT(NoNarrowSbrPortAwRequest, ChimneyCfgN.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowAw))) - `ASSERT(NoNarrowSbrPortArRequest, EnNarrowSbrPort || !(floo_req_in_valid && + `ASSERT(NoNarrowSbrPortArRequest, ChimneyCfgN.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowAr))) - `ASSERT(NoNarrowSbrPortWRequest, EnNarrowSbrPort || !(floo_req_in_valid && + `ASSERT(NoNarrowSbrPortWRequest, ChimneyCfgN.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowW))) - `ASSERT(NoWideSbrPortAwRequest, EnWideSbrPort || !(floo_req_in_valid && + `ASSERT(NoWideSbrPortAwRequest, ChimneyCfgW.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAw))) - `ASSERT(NoWideSbrPortArRequest, EnWideSbrPort || !(floo_req_in_valid && + `ASSERT(NoWideSbrPortArRequest, ChimneyCfgW.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAr))) - `ASSERT(NoWideSbrPortWRequest, EnWideSbrPort || !(floo_wide_in_valid && + `ASSERT(NoWideSbrPortWRequest, ChimneyCfgW.EnSbrPort || !(floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideW))) endmodule diff --git a/hw/floo_narrow_wide_join.sv b/hw/floo_nw_join.sv similarity index 99% rename from hw/floo_narrow_wide_join.sv rename to hw/floo_nw_join.sv index 752947d3..79881685 100644 --- a/hw/floo_narrow_wide_join.sv +++ b/hw/floo_nw_join.sv @@ -11,7 +11,7 @@ /// This module is intended to be used for instance in front /// of an HBM controller to enable access from both the /// narrow and the wide AXI bus. -module floo_narrow_wide_join #( +module floo_nw_join #( /// Filter Atops on the Narrow AXI bus parameter bit FilterNarrowAtops = 1'b0, /// Filter Atops on the Wide AXI bus diff --git a/hw/floo_narrow_wide_router.sv b/hw/floo_nw_router.sv similarity index 66% rename from hw/floo_narrow_wide_router.sv rename to hw/floo_nw_router.sv index 033e7211..a08ff55b 100644 --- a/hw/floo_narrow_wide_router.sv +++ b/hw/floo_nw_router.sv @@ -4,24 +4,30 @@ // // Author: Tim Fischer +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" + /// Wrapper of a multi-link router for narrow and wide links -module floo_narrow_wide_router - import floo_pkg::*; - import floo_narrow_wide_pkg::*; - #( - parameter int unsigned NumRoutes = NumDirections, - parameter int unsigned NumInputs = NumRoutes, - parameter int unsigned NumOutputs = NumRoutes, - parameter int unsigned ChannelFifoDepth = 0, - parameter int unsigned OutputFifoDepth = 0, - parameter route_algo_e RouteAlgo = XYRouting, - parameter bit XYRouteOpt = 1'b1, - /// Used for ID-based and XY routing - parameter int unsigned IdWidth = 0, - parameter type id_t = logic[IdWidth-1:0], - /// Used for ID-based routing - parameter int unsigned NumAddrRules = 0, - parameter type addr_rule_t = logic +module floo_nw_router #( + parameter floo_pkg::axi_cfg_t AxiCfgN = '0, + parameter floo_pkg::axi_cfg_t AxiCfgW = '0, + parameter floo_pkg::route_algo_e RouteAlgo = floo_pkg::XYRouting, + parameter int unsigned NumRoutes = 0, + parameter int unsigned NumInputs = NumRoutes, + parameter int unsigned NumOutputs = NumRoutes, + parameter int unsigned InFifoDepth = 0, + parameter int unsigned OutFifoDepth = 0, + parameter bit XYRouteOpt = 1'b1, + /// Used for ID-based and XY routing + parameter int unsigned IdWidth = 0, + parameter type id_t = logic[IdWidth-1:0], + parameter type hdr_t = logic, + /// Used for ID-based routing + parameter int unsigned NumAddrRules = 0, + parameter type addr_rule_t = logic, + parameter type floo_req_t = logic, + parameter type floo_rsp_t = logic, + parameter type floo_wide_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -34,10 +40,27 @@ module floo_narrow_wide_router input floo_rsp_t [NumOutputs-1:0] floo_rsp_i, output floo_req_t [NumOutputs-1:0] floo_req_o, output floo_rsp_t [NumInputs-1:0] floo_rsp_o, - input floo_wide_t [NumRoutes-1:0] floo_wide_i, - output floo_wide_t [NumRoutes-1:0] floo_wide_o + input floo_wide_t [NumRoutes-1:0] floo_wide_i, + output floo_wide_t [NumRoutes-1:0] floo_wide_o ); + typedef logic [AxiCfgN.AddrWidth-1:0] axi_addr_t; + typedef logic [AxiCfgN.InIdWidth-1:0] axi_narrow_in_id_t; + typedef logic [AxiCfgN.UserWidth-1:0] axi_narrow_user_t; + typedef logic [AxiCfgN.DataWidth-1:0] axi_narrow_data_t; + typedef logic [AxiCfgN.DataWidth/8-1:0] axi_narrow_strb_t; + typedef logic [AxiCfgW.InIdWidth-1:0] axi_wide_in_id_t; + typedef logic [AxiCfgW.UserWidth-1:0] axi_wide_user_t; + typedef logic [AxiCfgW.DataWidth-1:0] axi_wide_data_t; + typedef logic [AxiCfgW.DataWidth/8-1:0] axi_wide_strb_t; + + // (Re-) definitons of `axi_in` and `floo` types, for transport + `AXI_TYPEDEF_ALL_CT(axi_narrow, axi_narrow_req_t, axi_narrow_rsp_t, axi_addr_t, + axi_narrow_in_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_narrow_user_t) + `AXI_TYPEDEF_ALL_CT(axi_wide, axi_wide_req_t, axi_wide_rsp_t, axi_addr_t, + axi_wide_in_id_t, axi_wide_data_t, axi_wide_strb_t, axi_wide_user_t) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow, axi_wide, AxiCfgN, AxiCfgW, hdr_t) + floo_req_chan_t [NumInputs-1:0] req_in; floo_rsp_chan_t [NumInputs-1:0] rsp_out; floo_req_chan_t [NumOutputs-1:0] req_out; @@ -83,8 +106,8 @@ module floo_narrow_wide_router .NumInput ( NumInputs ), .NumOutput ( NumOutputs ), .flit_t ( floo_req_generic_flit_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), + .InFifoDepth ( InFifoDepth ), + .OutFifoDepth ( OutFifoDepth ), .RouteAlgo ( RouteAlgo ), .XYRouteOpt ( XYRouteOpt ), .IdWidth ( IdWidth ), @@ -111,8 +134,8 @@ module floo_narrow_wide_router .NumVirtChannels ( 1 ), .NumInput ( NumInputs ), .NumOutput ( NumOutputs ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), + .InFifoDepth ( InFifoDepth ), + .OutFifoDepth ( OutFifoDepth ), .RouteAlgo ( RouteAlgo ), .XYRouteOpt ( XYRouteOpt ), .IdWidth ( IdWidth ), @@ -140,8 +163,8 @@ module floo_narrow_wide_router .NumVirtChannels ( 1 ), .NumRoutes ( NumRoutes ), .flit_t ( floo_wide_generic_flit_t ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), + .InFifoDepth ( InFifoDepth ), + .OutFifoDepth ( OutFifoDepth ), .RouteAlgo ( RouteAlgo ), .XYRouteOpt ( XYRouteOpt ), .IdWidth ( IdWidth ), diff --git a/hw/floo_vc_narrow_wide_chimney.sv b/hw/floo_nw_vc_chimney.sv similarity index 75% rename from hw/floo_vc_narrow_wide_chimney.sv rename to hw/floo_nw_vc_chimney.sv index da7ac272..a030868e 100644 --- a/hw/floo_vc_narrow_wide_chimney.sv +++ b/hw/floo_nw_vc_chimney.sv @@ -7,25 +7,19 @@ `include "common_cells/registers.svh" `include "common_cells/assertions.svh" -`include "axi/assign.svh" +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" /// A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC -module floo_vc_narrow_wide_chimney - import floo_pkg::*; - import floo_vc_narrow_wide_pkg::*; -#( - /// FlooNoC defines subordinate ports as requests that go out - /// of the NoC to AXI subordinates (i.e. memories) that return - /// a response, and manager ports as requests that come into the - /// NoC from AXI managers (i.e. cores) - /// Enable the subordinate port of the Narrow AXI4 interface - parameter bit EnNarrowSbrPort = 1'b1, - /// Enable the manager port of the Narrow AXI4 interface - parameter bit EnNarrowMgrPort = 1'b1, - /// Enable the subordinate port of the Wide AXI4 interface - parameter bit EnWideSbrPort = 1'b1, - /// Enable the manager port of the Wide AXI4 interface - parameter bit EnWideMgrPort = 1'b1, +module floo_nw_vc_chimney #( + /// AXI parameter config + parameter floo_pkg::axi_cfg_t AxiCfgN = '0, + parameter floo_pkg::axi_cfg_t AxiCfgW = '0, + // Chimney configs + parameter floo_pkg::chimney_cfg_t ChimneyCfgN = floo_pkg::ChimneyDefaultCfg, + parameter floo_pkg::chimney_cfg_t ChimneyCfgW = floo_pkg::ChimneyDefaultCfg, + /// Route config + parameter floo_pkg::route_cfg_t RouteCfg = floo_pkg::RouteDefaultCfg, /// Atomic operation support, currently only implemented for /// the narrow network! parameter bit AtopSupport = 1'b1, @@ -34,38 +28,29 @@ module floo_vc_narrow_wide_chimney /// Every atomic transactions needs to have a unique ID /// and one ID is reserved for non-atomic transactions parameter int unsigned MaxAtomicTxns = 1, - /// Number of maximum oustanding requests on the narrow network - parameter int unsigned NarrowMaxTxns = 32, - /// Number of maximum oustanding requests on the wide network - parameter int unsigned WideMaxTxns = 32, - /// The number of unique IDs that can be used to send out - /// requests on the narrow network - parameter int unsigned NarrowMaxUniqueIds = 1, - /// The number of unique IDs that can be used to send out - /// requests on the wide network - parameter int unsigned WideMaxUniqueIds = 1, - /// Maximum number of outstanding requests per ID on the narrow network - parameter int unsigned NarrowMaxTxnsPerId = NarrowMaxTxns, - /// Maximum number of outstanding requests per ID on the wide network - parameter int unsigned WideMaxTxnsPerId = WideMaxTxns, - /// Type of the narrow reorder buffer - parameter rob_type_e NarrowRoBType = NoRoB, - /// Type of the wide reorder buffer - parameter rob_type_e WideRoBType = NoRoB, - /// Capacity of the narrow reorder buffers - parameter int unsigned NarrowReorderBufferSize = 256, - /// Capacity of the wide reorder buffers - parameter int unsigned WideReorderBufferSize = 256, - /// Cut timing paths of outgoing requests to the NoC - parameter bit CutAx = 1'b1, - /// Cut timing paths of incoming responses from the NoC - parameter bit CutRsp = 1'b1, /// Type for implementation inputs and outputs - parameter type sram_cfg_t = logic, - /// Used for ID-based and XY routing - parameter int unsigned IdWidth = 0, + parameter type sam_rule_t = logic, + parameter type hdr_t = logic, + parameter sam_rule_t [RouteCfg.SamNumRules-1:0] Sam = '0, + parameter type axi_narrow_in_req_t = logic, + parameter type axi_narrow_in_rsp_t = logic, + parameter type axi_narrow_out_req_t = logic, + parameter type axi_narrow_out_rsp_t = logic, + parameter type axi_wide_in_req_t = logic, + parameter type axi_wide_in_rsp_t = logic, + parameter type axi_wide_out_req_t = logic, + parameter type axi_wide_out_rsp_t = logic, + parameter type rob_idx_t = logic, + parameter type id_t = logic, + parameter type vc_id_t = logic, + parameter type route_t = logic, + parameter type addr_rule_t = logic, + parameter type floo_vc_req_t = logic, + parameter type floo_vc_rsp_t = logic, + parameter type floo_vc_wide_t = logic, + parameter type sram_cfg_t = logic, //on which port the chimney is connected to the router (as seen from the router) - parameter route_direction_e OutputDir = Eject, + parameter floo_pkg::route_direction_e OutputDir = floo_pkg::Eject, parameter int NumVC = 4, // as seen from chimney parameter int NumVCWidth = NumVC > 1 ? $clog2(NumVC) : 1, @@ -75,18 +60,7 @@ module floo_vc_narrow_wide_chimney parameter int VCDepth = 2, parameter int FixedWormholeVC = 1, // if 1, force wormhole flits to wormholeVCId parameter int WormholeVCId = 0, - parameter int WormholeVCDepth = 3, - /// Used for ID-based routing - parameter int unsigned NumAddrRules = 0, - parameter type addr_rule_t = logic, - /// Number of System Address Map Rules - parameter int unsigned SamNumRules = 0, - /// Type of System Address Map Rule - parameter type sam_rule_t = logic, - /// System Address Map - parameter sam_rule_t [SamNumRules-1:0] Sam = '0, - /// Number of routes in the routing table - parameter int unsigned NumRoutes = 0 + parameter int WormholeVCDepth = 3 ) ( input logic clk_i, input logic rst_ni, @@ -104,9 +78,8 @@ module floo_vc_narrow_wide_chimney /// Coordinates/ID of the current tile input id_t id_i, /// Routing table for the current tile - input route_t [NumRoutes-1:0] route_table_i, - input addr_rule_t [NumAddrRules-1:0] id_route_map_i, - + input route_t [RouteCfg.NumRoutes-1:0] route_table_i, + input addr_rule_t [RouteCfg.NumAddrRules-1:0] id_route_map_i, /// Output to NoC output floo_vc_req_t floo_req_o, output floo_vc_rsp_t floo_rsp_o, @@ -117,18 +90,37 @@ module floo_vc_narrow_wide_chimney input floo_vc_wide_t floo_wide_i ); + import floo_pkg::*; + + typedef logic [AxiCfgN.AddrWidth-1:0] axi_addr_t; + typedef logic [AxiCfgN.InIdWidth-1:0] axi_narrow_in_id_t; + typedef logic [AxiCfgN.UserWidth-1:0] axi_narrow_user_t; + typedef logic [AxiCfgN.DataWidth-1:0] axi_narrow_data_t; + typedef logic [AxiCfgN.DataWidth/8-1:0] axi_narrow_strb_t; + typedef logic [AxiCfgW.InIdWidth-1:0] axi_wide_in_id_t; + typedef logic [AxiCfgW.UserWidth-1:0] axi_wide_user_t; + typedef logic [AxiCfgW.DataWidth-1:0] axi_wide_data_t; + typedef logic [AxiCfgW.DataWidth/8-1:0] axi_wide_strb_t; + + // (Re-) definitons of `axi_in` and `floo` types, for transport + `AXI_TYPEDEF_ALL_CT(axi_narrow, axi_narrow_req_t, axi_narrow_rsp_t, axi_addr_t, + axi_narrow_in_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_narrow_user_t) + `AXI_TYPEDEF_ALL_CT(axi_wide, axi_wide_req_t, axi_wide_rsp_t, axi_addr_t, + axi_wide_in_id_t, axi_wide_data_t, axi_wide_strb_t, axi_wide_user_t) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow, axi_wide, AxiCfgN, AxiCfgW, hdr_t) + // Duplicate AXI port signals to degenerate ports // in case they are not used - axi_narrow_in_req_t axi_narrow_req_in; - axi_narrow_in_rsp_t axi_narrow_rsp_out; - axi_wide_in_req_t axi_wide_req_in; - axi_wide_in_rsp_t axi_wide_rsp_out; + axi_narrow_req_t axi_narrow_req_in; + axi_narrow_rsp_t axi_narrow_rsp_out; + axi_wide_req_t axi_wide_req_in; + axi_wide_rsp_t axi_wide_rsp_out; // AX queue - axi_narrow_in_aw_chan_t axi_narrow_aw_queue; - axi_narrow_in_ar_chan_t axi_narrow_ar_queue; - axi_wide_in_aw_chan_t axi_wide_aw_queue; - axi_wide_in_ar_chan_t axi_wide_ar_queue; + axi_narrow_aw_chan_t axi_narrow_aw_queue; + axi_narrow_ar_chan_t axi_narrow_ar_queue; + axi_wide_aw_chan_t axi_wide_aw_queue; + axi_wide_ar_chan_t axi_wide_ar_queue; logic axi_narrow_aw_queue_valid_out, axi_narrow_aw_queue_ready_in; logic axi_narrow_ar_queue_valid_out, axi_narrow_ar_queue_ready_in; logic axi_wide_aw_queue_valid_out, axi_wide_aw_queue_ready_in; @@ -147,19 +139,19 @@ module floo_vc_narrow_wide_chimney floo_wide_chan_t floo_wide_in; logic floo_req_in_valid, floo_rsp_in_valid, floo_wide_in_valid; logic floo_req_out_ready, floo_rsp_out_ready, floo_wide_out_ready; - logic [NumAxiChannels-1:0] axi_valid_in, axi_ready_out; + logic [NumNWAxiChannels-1:0] axi_valid_in, axi_ready_out; // Flit packing - floo_narrow_aw_flit_t floo_narrow_aw; - floo_narrow_ar_flit_t floo_narrow_ar; - floo_narrow_w_flit_t floo_narrow_w; - floo_narrow_b_flit_t floo_narrow_b; - floo_narrow_r_flit_t floo_narrow_r; - floo_wide_aw_flit_t floo_wide_aw; - floo_wide_ar_flit_t floo_wide_ar; - floo_wide_w_flit_t floo_wide_w; - floo_wide_b_flit_t floo_wide_b; - floo_wide_r_flit_t floo_wide_r; + floo_axi_narrow_aw_flit_t floo_narrow_aw; + floo_axi_narrow_ar_flit_t floo_narrow_ar; + floo_axi_narrow_w_flit_t floo_narrow_w; + floo_axi_narrow_b_flit_t floo_narrow_b; + floo_axi_narrow_r_flit_t floo_narrow_r; + floo_axi_wide_aw_flit_t floo_wide_aw; + floo_axi_wide_ar_flit_t floo_wide_ar; + floo_axi_wide_w_flit_t floo_wide_w; + floo_axi_wide_b_flit_t floo_wide_b; + floo_axi_wide_r_flit_t floo_wide_r; // Flit arbitration typedef enum logic {SelAw, SelW} aw_w_sel_e; @@ -193,16 +185,16 @@ module floo_vc_narrow_wide_chimney floo_wide_wormhole_detected, floo_wide_wh_valid_d, floo_wide_wh_valid; // Flit unpacking - axi_narrow_in_aw_chan_t axi_narrow_unpack_aw; - axi_narrow_in_w_chan_t axi_narrow_unpack_w; - axi_narrow_in_b_chan_t axi_narrow_unpack_b; - axi_narrow_in_ar_chan_t axi_narrow_unpack_ar; - axi_narrow_in_r_chan_t axi_narrow_unpack_r; - axi_wide_in_aw_chan_t axi_wide_unpack_aw; - axi_wide_in_w_chan_t axi_wide_unpack_w; - axi_wide_in_b_chan_t axi_wide_unpack_b; - axi_wide_in_ar_chan_t axi_wide_unpack_ar; - axi_wide_in_r_chan_t axi_wide_unpack_r; + axi_narrow_aw_chan_t axi_narrow_unpack_aw; + axi_narrow_w_chan_t axi_narrow_unpack_w; + axi_narrow_b_chan_t axi_narrow_unpack_b; + axi_narrow_ar_chan_t axi_narrow_unpack_ar; + axi_narrow_r_chan_t axi_narrow_unpack_r; + axi_wide_aw_chan_t axi_wide_unpack_aw; + axi_wide_w_chan_t axi_wide_unpack_w; + axi_wide_b_chan_t axi_wide_unpack_b; + axi_wide_ar_chan_t axi_wide_unpack_ar; + axi_wide_r_chan_t axi_wide_unpack_r; floo_req_generic_flit_t floo_req_unpack_generic; floo_rsp_generic_flit_t floo_rsp_unpack_generic; floo_wide_generic_flit_t floo_wide_unpack_generic; @@ -216,43 +208,38 @@ module floo_vc_narrow_wide_chimney // ID tracking typedef struct packed { axi_narrow_in_id_t id; - logic rob_req; - rob_idx_t rob_idx; - id_t src_id; - logic atop; - } narrow_id_out_buf_t; + hdr_t hdr; + } narrow_meta_buf_t; typedef struct packed { axi_wide_in_id_t id; - logic rob_req; - rob_idx_t rob_idx; - id_t src_id; - } wide_id_out_buf_t; + hdr_t hdr; + } wide_meta_buf_t; // Routing - dst_t [NumAxiChannels-1:0] dst_id; - dst_t narrow_aw_id_q, wide_aw_id_q; - route_t [NumAxiChannels-1:0] route_out; - id_t [NumAxiChannels-1:0] id_out; + id_t [NumNWAxiChannels-1:0] dst_id; + id_t narrow_aw_id_q, wide_aw_id_q; + route_t [NumNWAxiChannels-1:0] route_out; + id_t [NumNWAxiChannels-1:0] id_out; - narrow_id_out_buf_t narrow_aw_out_data_in, narrow_aw_out_data_out; - narrow_id_out_buf_t narrow_ar_out_data_in, narrow_ar_out_data_out; - wide_id_out_buf_t wide_aw_out_data_in, wide_aw_out_data_out; - wide_id_out_buf_t wide_ar_out_data_in, wide_ar_out_data_out; + narrow_meta_buf_t narrow_aw_buf_hdr_in, narrow_aw_buf_hdr_out; + narrow_meta_buf_t narrow_ar_buf_hdr_in, narrow_ar_buf_hdr_out; + wide_meta_buf_t wide_aw_buf_hdr_in, wide_aw_buf_hdr_out; + wide_meta_buf_t wide_ar_buf_hdr_in, wide_ar_buf_hdr_out; /////////////////////// // Spill registers // /////////////////////// - if (EnNarrowMgrPort) begin : gen_narrow_sbr_port + if (ChimneyCfgN.EnMgrPort) begin : gen_narrow_sbr_port assign axi_narrow_req_in = axi_narrow_in_req_i; assign axi_narrow_in_rsp_o = axi_narrow_rsp_out; - if (CutAx) begin : gen_ax_cuts + if (ChimneyCfgN.CutAx) begin : gen_ax_cuts spill_register #( - .T ( axi_narrow_in_aw_chan_t ) + .T ( axi_narrow_aw_chan_t ) ) i_narrow_aw_queue ( .clk_i, .rst_ni, @@ -265,7 +252,7 @@ module floo_vc_narrow_wide_chimney ); spill_register #( - .T ( axi_narrow_in_ar_chan_t ) + .T ( axi_narrow_ar_chan_t ) ) i_narrow_ar_queue ( .clk_i, .rst_ni, @@ -288,7 +275,7 @@ module floo_vc_narrow_wide_chimney end else begin : gen_narrow_err_slv_port axi_err_slv #( - .AxiIdWidth ( AxiNarrowInIdWidth ), + .AxiIdWidth ( AxiCfgN.InIdWidth ), .ATOPs ( AtopSupport ), .axi_req_t ( axi_narrow_in_req_t ), .axi_resp_t ( axi_narrow_in_rsp_t ) @@ -306,14 +293,14 @@ module floo_vc_narrow_wide_chimney assign axi_narrow_ar_queue_valid_out = 1'b0; end - if (EnWideMgrPort) begin : gen_wide_sbr_port + if (ChimneyCfgW.EnMgrPort) begin : gen_wide_sbr_port assign axi_wide_req_in = axi_wide_in_req_i; assign axi_wide_in_rsp_o = axi_wide_rsp_out; - if (CutAx) begin : gen_ax_cuts + if (ChimneyCfgW.CutAx) begin : gen_ax_cuts spill_register #( - .T ( axi_wide_in_aw_chan_t ) + .T ( axi_wide_aw_chan_t ) ) i_wide_aw_queue ( .clk_i, .rst_ni, @@ -326,7 +313,7 @@ module floo_vc_narrow_wide_chimney ); spill_register #( - .T ( axi_wide_in_ar_chan_t ) + .T ( axi_wide_ar_chan_t ) ) i_wide_ar_queue ( .clk_i, .rst_ni, @@ -347,7 +334,7 @@ module floo_vc_narrow_wide_chimney end end else begin : gen_wide_err_slv_port axi_err_slv #( - .AxiIdWidth ( AxiWideInIdWidth ), + .AxiIdWidth ( AxiCfgW.InIdWidth ), .ATOPs ( AtopSupport ), .axi_req_t ( axi_wide_in_req_t ), .axi_resp_t ( axi_wide_in_rsp_t ) @@ -365,7 +352,7 @@ module floo_vc_narrow_wide_chimney assign axi_wide_ar_queue_valid_out = 1'b0; end - if (CutRsp) begin : gen_floo_input_fifos + if (ChimneyCfgN.CutRsp && ChimneyCfgW.CutRsp) begin : gen_floo_input_fifos floo_input_fifo #( .Depth ( InputFifoDepth ), .type_t ( floo_req_chan_t ) @@ -414,14 +401,14 @@ module floo_vc_narrow_wide_chimney /////////////////////// // AW/B RoB - axi_narrow_in_b_chan_t axi_narrow_b_rob_out, axi_narrow_b_rob_in; + axi_narrow_b_chan_t axi_narrow_b_rob_out, axi_narrow_b_rob_in; logic narrow_aw_rob_req_out; rob_idx_t narrow_aw_rob_idx_out; logic narrow_aw_rob_valid_out, narrow_aw_rob_ready_in; logic narrow_aw_rob_valid_in, narrow_aw_rob_ready_out; logic narrow_b_rob_valid_in, narrow_b_rob_ready_out; logic narrow_b_rob_valid_out, narrow_b_rob_ready_in; - axi_wide_in_b_chan_t axi_wide_b_rob_out, axi_wide_b_rob_in; + axi_wide_b_chan_t axi_wide_b_rob_out, axi_wide_b_rob_in; logic wide_aw_rob_req_out; rob_idx_t wide_aw_rob_idx_out; logic wide_aw_rob_valid_out, wide_aw_rob_ready_in; @@ -429,13 +416,13 @@ module floo_vc_narrow_wide_chimney logic wide_b_rob_valid_out, wide_b_rob_ready_in; // AR/R RoB - axi_narrow_in_r_chan_t axi_narrow_r_rob_out, axi_narrow_r_rob_in; + axi_narrow_r_chan_t axi_narrow_r_rob_out, axi_narrow_r_rob_in; logic narrow_ar_rob_req_out; rob_idx_t narrow_ar_rob_idx_out; logic narrow_ar_rob_valid_out, narrow_ar_rob_ready_in; logic narrow_r_rob_valid_in, narrow_r_rob_ready_out; logic narrow_r_rob_valid_out, narrow_r_rob_ready_in; - axi_wide_in_r_chan_t axi_wide_r_rob_out, axi_wide_r_rob_in; + axi_wide_r_chan_t axi_wide_r_rob_out, axi_wide_r_rob_in; logic wide_ar_rob_req_out; rob_idx_t wide_ar_rob_idx_out; logic wide_ar_rob_valid_out, wide_ar_rob_ready_in; @@ -463,17 +450,17 @@ module floo_vc_narrow_wide_chimney end floo_rob_wrapper #( - .RoBType ( NarrowRoBType ), - .ReorderBufferSize ( NarrowReorderBufferSize ), - .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), - .OnlyMetaData ( 1'b1 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_narrow_in_id_t ), - .rsp_chan_t ( axi_narrow_in_b_chan_t ), - .rsp_meta_t ( axi_narrow_in_b_chan_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgN.BRoBType ), + .RoBDepth ( ChimneyCfgN.BRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgN.MaxTxnsPerId ), + .OnlyMetaData ( 1'b1 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_narrow_in_id_t ), + .rsp_chan_t ( axi_narrow_b_chan_t ), + .rsp_meta_t ( axi_narrow_b_chan_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_narrow_b_rob ( .clk_i, .rst_ni, @@ -506,17 +493,17 @@ module floo_vc_narrow_wide_chimney assign wide_b_rob_last = floo_rsp_in.wide_b.hdr.last; floo_rob_wrapper #( - .RoBType ( WideRoBType ), - .ReorderBufferSize ( WideReorderBufferSize ), - .MaxRoTxnsPerId ( WideMaxTxnsPerId ), - .OnlyMetaData ( 1'b1 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_wide_in_id_t ), - .rsp_chan_t ( axi_wide_in_b_chan_t ), - .rsp_meta_t ( axi_wide_in_b_chan_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgW.BRoBType ), + .RoBDepth ( ChimneyCfgW.BRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgW.MaxTxnsPerId ), + .OnlyMetaData ( 1'b1 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_wide_in_id_t ), + .rsp_chan_t ( axi_wide_b_chan_t ), + .rsp_meta_t ( axi_wide_b_chan_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_wide_b_rob ( .clk_i, .rst_ni, @@ -542,17 +529,17 @@ module floo_vc_narrow_wide_chimney ); typedef struct packed { - axi_narrow_in_id_t id; - axi_narrow_in_user_t user; - axi_pkg::resp_t resp; - logic last; + axi_narrow_in_id_t id; + axi_narrow_user_t user; + axi_pkg::resp_t resp; + logic last; } narrow_meta_t; typedef struct packed { - axi_wide_in_id_t id; - axi_wide_in_user_t user; - axi_pkg::resp_t resp; - logic last; + axi_wide_in_id_t id; + axi_wide_user_t user; + axi_pkg::resp_t resp; + logic last; } wide_meta_t; logic narrow_r_rob_rob_req; @@ -560,21 +547,21 @@ module floo_vc_narrow_wide_chimney rob_idx_t narrow_r_rob_rob_idx; assign narrow_r_rob_rob_req = floo_rsp_in.narrow_r.hdr.rob_req; assign narrow_r_rob_rob_idx = floo_rsp_in.narrow_r.hdr.rob_idx; - assign narrow_r_rob_last = floo_rsp_in.narrow_r.r.last; + assign narrow_r_rob_last = floo_rsp_in.narrow_r.payload.last; floo_rob_wrapper #( - .RoBType ( NarrowRoBType ), - .ReorderBufferSize ( NarrowReorderBufferSize ), - .MaxRoTxnsPerId ( NarrowMaxTxnsPerId ), - .OnlyMetaData ( 1'b0 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_narrow_in_id_t ), - .rsp_chan_t ( axi_narrow_in_r_chan_t ), - .rsp_data_t ( axi_narrow_in_data_t ), - .rsp_meta_t ( narrow_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgN.RRoBType ), + .RoBDepth ( ChimneyCfgN.RRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgN.MaxTxnsPerId ), + .OnlyMetaData ( 1'b0 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_narrow_in_id_t ), + .rsp_chan_t ( axi_narrow_r_chan_t ), + .rsp_data_t ( axi_narrow_data_t ), + .rsp_meta_t ( narrow_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_narrow_r_rob ( .clk_i, .rst_ni, @@ -604,21 +591,21 @@ module floo_vc_narrow_wide_chimney rob_idx_t wide_r_rob_rob_idx; assign wide_r_rob_rob_req = floo_wide_in.wide_r.hdr.rob_req; assign wide_r_rob_rob_idx = floo_wide_in.wide_r.hdr.rob_idx; - assign wide_r_rob_last = floo_wide_in.wide_r.r.last; + assign wide_r_rob_last = floo_wide_in.wide_r.payload.last; floo_rob_wrapper #( - .RoBType ( WideRoBType ), - .ReorderBufferSize ( WideReorderBufferSize ), - .MaxRoTxnsPerId ( WideMaxTxnsPerId ), - .OnlyMetaData ( 1'b0 ), - .ax_len_t ( axi_pkg::len_t ), - .ax_id_t ( axi_wide_in_id_t ), - .rsp_chan_t ( axi_wide_in_r_chan_t ), - .rsp_data_t ( axi_wide_in_data_t ), - .rsp_meta_t ( wide_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( id_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBType ( ChimneyCfgW.RRoBType ), + .RoBDepth ( ChimneyCfgW.RRoBDepth ), + .MaxRoTxnsPerId ( ChimneyCfgW.MaxTxnsPerId ), + .OnlyMetaData ( 1'b0 ), + .ax_len_t ( axi_pkg::len_t ), + .ax_id_t ( axi_wide_in_id_t ), + .rsp_chan_t ( axi_wide_r_chan_t ), + .rsp_data_t ( axi_wide_data_t ), + .rsp_meta_t ( wide_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( id_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_wide_r_rob ( .clk_i, .rst_ni, @@ -647,20 +634,14 @@ module floo_vc_narrow_wide_chimney // ROUTING // ///////////////// - typedef axi_narrow_in_addr_t addr_t; + typedef axi_addr_t addr_t; floo_route_comp #( - .RouteAlgo ( RouteAlgo ), - .UseIdTable ( UseIdTable ), - .XYAddrOffsetX ( XYAddrOffsetX ), - .XYAddrOffsetY ( XYAddrOffsetY ), - .IdAddrOffset ( IdAddrOffset ), - .NumAddrRules ( SamNumRules ), - .NumRoutes ( NumRoutes ), - .id_t ( id_t ), - .addr_t ( addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) + .RouteCfg ( RouteCfg ), + .id_t ( id_t ), + .addr_t ( addr_t ), + .addr_rule_t ( sam_rule_t ), + .route_t ( route_t ) ) i_floo_req_route_comp [3:0] ( .clk_i, .rst_ni, @@ -675,12 +656,10 @@ module floo_vc_narrow_wide_chimney .id_o ({id_out[NarrowAw], id_out[NarrowAr],id_out[WideAw], id_out[WideAr]} ) ); - if (RouteAlgo == SourceRouting) begin : gen_route_field + if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field floo_route_comp #( - .RouteAlgo ( RouteAlgo ), - .UseIdTable ( 1'b0 ), - .NumAddrRules ( SamNumRules ), - .NumRoutes ( NumRoutes ), + .RouteCfg ( RouteCfg ), + .UseIdTable ( 1'b0 ), // Overwrite `RouteCfg` .id_t ( id_t ), .addr_t ( addr_t ), .addr_rule_t ( sam_rule_t ), @@ -692,8 +671,8 @@ module floo_vc_narrow_wide_chimney .addr_i ( '0 ), .addr_map_i ( '0 ), .id_i ({ - narrow_aw_out_data_out.src_id, narrow_ar_out_data_out.src_id, - wide_aw_out_data_out.src_id, wide_ar_out_data_out.src_id + narrow_aw_buf_hdr_out.hdr.src_id, narrow_ar_buf_hdr_out.hdr.src_id, + wide_aw_buf_hdr_out.hdr.src_id, wide_ar_buf_hdr_out.hdr.src_id }), .route_o ({route_out[NarrowB], route_out[NarrowR], route_out[WideB], route_out[WideR]} ), .id_o ({id_out[NarrowB], id_out[NarrowR], id_out[WideB], id_out[WideR]} ) @@ -706,10 +685,10 @@ module floo_vc_narrow_wide_chimney assign dst_id[NarrowAr] = id_out[NarrowAr]; assign dst_id[WideAw] = id_out[WideAw]; assign dst_id[WideAr] = id_out[WideAr]; - assign dst_id[NarrowB] = narrow_aw_out_data_out.src_id; - assign dst_id[NarrowR] = narrow_ar_out_data_out.src_id; - assign dst_id[WideB] = wide_aw_out_data_out.src_id; - assign dst_id[WideR] = wide_ar_out_data_out.src_id; + assign dst_id[NarrowB] = narrow_aw_buf_hdr_out.hdr.src_id; + assign dst_id[NarrowR] = narrow_ar_buf_hdr_out.hdr.src_id; + assign dst_id[WideB] = wide_aw_buf_hdr_out.hdr.src_id; + assign dst_id[WideR] = wide_ar_buf_hdr_out.hdr.src_id; assign dst_id[NarrowW] = narrow_aw_id_q; assign dst_id[WideW] = wide_aw_id_q; end @@ -735,7 +714,7 @@ module floo_vc_narrow_wide_chimney floo_narrow_aw.hdr.last = 1'b0; // AW and W need to be sent together floo_narrow_aw.hdr.axi_ch = NarrowAw; floo_narrow_aw.hdr.atop = axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE; - floo_narrow_aw.aw = axi_narrow_aw_queue; + floo_narrow_aw.payload = axi_narrow_aw_queue; end always_comb begin @@ -747,7 +726,7 @@ module floo_vc_narrow_wide_chimney floo_narrow_w.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_narrow_w.hdr.last = axi_narrow_req_in.w.last; floo_narrow_w.hdr.axi_ch = NarrowW; - floo_narrow_w.w = axi_narrow_req_in.w; + floo_narrow_w.payload = axi_narrow_req_in.w; end always_comb begin @@ -759,35 +738,35 @@ module floo_vc_narrow_wide_chimney floo_narrow_ar.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_narrow_ar.hdr.last = 1'b1; floo_narrow_ar.hdr.axi_ch = NarrowAr; - floo_narrow_ar.ar = axi_narrow_ar_queue; + floo_narrow_ar.payload = axi_narrow_ar_queue; end always_comb begin floo_narrow_b = '0; - floo_narrow_b.hdr.rob_req = narrow_aw_out_data_out.rob_req; - floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_out_data_out.rob_idx); + floo_narrow_b.hdr.rob_req = narrow_aw_buf_hdr_out.hdr.rob_req; + floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_buf_hdr_out.hdr.rob_idx); floo_narrow_b.hdr.dst_id = dst_id[NarrowB]; floo_narrow_b.hdr.src_id = id_i; floo_narrow_b.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_narrow_b.hdr.last = 1'b1; floo_narrow_b.hdr.axi_ch = NarrowB; - floo_narrow_b.hdr.atop = narrow_aw_out_data_out.atop; - floo_narrow_b.b = axi_narrow_meta_buf_rsp_out.b; - floo_narrow_b.b.id = narrow_aw_out_data_out.id; + floo_narrow_b.hdr.atop = narrow_aw_buf_hdr_out.hdr.atop; + floo_narrow_b.payload = axi_narrow_meta_buf_rsp_out.b; + floo_narrow_b.payload.id = narrow_aw_buf_hdr_out.id; end always_comb begin floo_narrow_r = '0; - floo_narrow_r.hdr.rob_req = narrow_ar_out_data_out.rob_req; - floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_out_data_out.rob_idx); + floo_narrow_r.hdr.rob_req = narrow_ar_buf_hdr_out.hdr.rob_req; + floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_buf_hdr_out.hdr.rob_idx); floo_narrow_r.hdr.dst_id = dst_id[NarrowR]; floo_narrow_r.hdr.src_id = id_i; floo_narrow_r.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_narrow_r.hdr.axi_ch = NarrowR; floo_narrow_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts - floo_narrow_r.hdr.atop = narrow_ar_out_data_out.atop; - floo_narrow_r.r = axi_narrow_meta_buf_rsp_out.r; - floo_narrow_r.r.id = narrow_ar_out_data_out.id; + floo_narrow_r.hdr.atop = narrow_ar_buf_hdr_out.hdr.atop; + floo_narrow_r.payload = axi_narrow_meta_buf_rsp_out.r; + floo_narrow_r.payload.id = narrow_ar_buf_hdr_out.id; end always_comb begin @@ -799,7 +778,7 @@ module floo_vc_narrow_wide_chimney floo_wide_aw.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_wide_aw.hdr.last = 1'b0; // AW and W need to be sent together floo_wide_aw.hdr.axi_ch = WideAw; - floo_wide_aw.aw = axi_wide_aw_queue; + floo_wide_aw.payload = axi_wide_aw_queue; end always_comb begin @@ -811,7 +790,7 @@ module floo_vc_narrow_wide_chimney floo_wide_w.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_wide_w.hdr.last = axi_wide_req_in.w.last; floo_wide_w.hdr.axi_ch = WideW; - floo_wide_w.w = axi_wide_req_in.w; + floo_wide_w.payload = axi_wide_req_in.w; end always_comb begin @@ -823,33 +802,33 @@ module floo_vc_narrow_wide_chimney floo_wide_ar.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_wide_ar.hdr.last = 1'b1; floo_wide_ar.hdr.axi_ch = WideAr; - floo_wide_ar.ar = axi_wide_ar_queue; + floo_wide_ar.payload = axi_wide_ar_queue; end always_comb begin floo_wide_b = '0; - floo_wide_b.hdr.rob_req = wide_aw_out_data_out.rob_req; - floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_out_data_out.rob_idx); + floo_wide_b.hdr.rob_req = wide_aw_buf_hdr_out.hdr.rob_req; + floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_buf_hdr_out.hdr.rob_idx); floo_wide_b.hdr.dst_id = dst_id[WideB]; floo_wide_b.hdr.src_id = id_i; floo_wide_b.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_wide_b.hdr.last = 1'b1; floo_wide_b.hdr.axi_ch = WideB; - floo_wide_b.b = axi_wide_meta_buf_rsp_out.b; - floo_wide_b.b.id = wide_aw_out_data_out.id; + floo_wide_b.payload = axi_wide_meta_buf_rsp_out.b; + floo_wide_b.payload.id = wide_aw_buf_hdr_out.id; end always_comb begin floo_wide_r = '0; - floo_wide_r.hdr.rob_req = wide_ar_out_data_out.rob_req; - floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_out_data_out.rob_idx); + floo_wide_r.hdr.rob_req = wide_ar_buf_hdr_out.hdr.rob_req; + floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_buf_hdr_out.hdr.rob_idx); floo_wide_r.hdr.dst_id = dst_id[WideR]; floo_wide_r.hdr.src_id = id_i; floo_wide_r.hdr.lookahead = ChimneyOutDir; // such that lookahead calculates correctly floo_wide_r.hdr.axi_ch = WideR; floo_wide_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts - floo_wide_r.r = axi_wide_meta_buf_rsp_out.r; - floo_wide_r.r.id = wide_ar_out_data_out.id; + floo_wide_r.payload = axi_wide_meta_buf_rsp_out.r; + floo_wide_r.payload.id = wide_ar_buf_hdr_out.id; end always_comb begin @@ -971,56 +950,53 @@ module floo_vc_narrow_wide_chimney /////////////////////// floo_look_ahead_routing #( - .NumRoutes ( NumRoutes ), - .hdr_t ( hdr_t ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( SamNumRules ), - .addr_rule_t ( sam_rule_t ) + .NumRoutes ( RouteCfg.NumRoutes ), + .hdr_t ( hdr_t ), + .RouteAlgo ( RouteCfg.RouteAlgo ), + .id_t ( id_t ), + .NumAddrRules ( RouteCfg.SamNumRules ), + .addr_rule_t ( sam_rule_t ) ) i_floo_req_look_ahead_routing ( .clk_i, .rst_ni, + .id_route_map_i, .hdr_i ( floo_req_arb_sel_hdr ), .hdr_o ( floo_req_sel_hdr ), .la_route_o ( floo_req_lookahead ), - .id_route_map_i, .xy_id_i ( id_i ) ); floo_look_ahead_routing #( - .NumRoutes ( NumRoutes ), - .hdr_t ( hdr_t ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( SamNumRules ), - .addr_rule_t ( sam_rule_t ) + .NumRoutes ( RouteCfg.NumRoutes ), + .hdr_t ( hdr_t ), + .RouteAlgo ( RouteCfg.RouteAlgo ), + .id_t ( id_t ), + .NumAddrRules ( RouteCfg.SamNumRules ), + .addr_rule_t ( sam_rule_t ) ) i_floo_rsp_look_ahead_routing ( .clk_i, .rst_ni, + .id_route_map_i, .hdr_i ( floo_rsp_arb_sel_hdr ), .hdr_o ( floo_rsp_sel_hdr ), .la_route_o ( floo_rsp_lookahead ), - .id_route_map_i, .xy_id_i ( id_i ) ); floo_look_ahead_routing #( - .NumRoutes ( NumRoutes ), - .hdr_t ( hdr_t ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( SamNumRules ), - .addr_rule_t ( sam_rule_t ) + .NumRoutes ( RouteCfg.NumRoutes ), + .hdr_t ( hdr_t ), + .RouteAlgo ( RouteCfg.RouteAlgo ), + .id_t ( id_t ), + .NumAddrRules ( RouteCfg.SamNumRules ), + .addr_rule_t ( sam_rule_t ) ) i_floo_wide_look_ahead_routing ( .clk_i, .rst_ni, + .id_route_map_i, .hdr_i ( floo_wide_arb_sel_hdr ), .hdr_o ( floo_wide_sel_hdr ), .la_route_o ( floo_wide_lookahead ), - .id_route_map_i, .xy_id_i ( id_i ) ); @@ -1289,16 +1265,16 @@ module floo_vc_narrow_wide_chimney assign b_sel_atop = is_atop_b_rsp && !b_rob_pending_q; assign r_sel_atop = is_atop_r_rsp && !r_rob_pending_q; - assign axi_narrow_unpack_aw = floo_req_in.narrow_aw.aw; - assign axi_narrow_unpack_w = floo_req_in.narrow_w.w; - assign axi_narrow_unpack_ar = floo_req_in.narrow_ar.ar; - assign axi_narrow_unpack_r = floo_rsp_in.narrow_r.r; - assign axi_narrow_unpack_b = floo_rsp_in.narrow_b.b; - assign axi_wide_unpack_aw = floo_wide_in.wide_aw.aw; - assign axi_wide_unpack_w = floo_wide_in.wide_w.w; - assign axi_wide_unpack_ar = floo_req_in.wide_ar.ar; - assign axi_wide_unpack_r = floo_wide_in.wide_r.r; - assign axi_wide_unpack_b = floo_rsp_in.wide_b.b; + assign axi_narrow_unpack_aw = floo_req_in.narrow_aw.payload; + assign axi_narrow_unpack_w = floo_req_in.narrow_w.payload; + assign axi_narrow_unpack_ar = floo_req_in.narrow_ar.payload; + assign axi_narrow_unpack_r = floo_rsp_in.narrow_r.payload; + assign axi_narrow_unpack_b = floo_rsp_in.narrow_b.payload; + assign axi_wide_unpack_aw = floo_wide_in.wide_aw.payload; + assign axi_wide_unpack_w = floo_wide_in.wide_w.payload; + assign axi_wide_unpack_ar = floo_req_in.wide_ar.payload; + assign axi_wide_unpack_r = floo_wide_in.wide_r.payload; + assign axi_wide_unpack_b = floo_rsp_in.wide_b.payload; assign floo_req_unpack_generic = floo_req_in.generic; assign floo_rsp_unpack_generic = floo_rsp_in.generic; assign floo_wide_unpack_generic = floo_wide_in.generic; @@ -1312,17 +1288,17 @@ module floo_vc_narrow_wide_chimney (floo_req_unpack_generic.hdr.axi_ch == NarrowAr); assign axi_valid_in[WideAr] = floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAr); - assign axi_valid_in[NarrowB] = EnNarrowMgrPort && floo_rsp_in_valid && + assign axi_valid_in[NarrowB] = ChimneyCfgN.EnMgrPort && floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowB); - assign axi_valid_in[NarrowR] = EnNarrowMgrPort && floo_rsp_in_valid && + assign axi_valid_in[NarrowR] = ChimneyCfgN.EnMgrPort && floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowR); - assign axi_valid_in[WideB] = EnWideMgrPort && floo_rsp_in_valid && + assign axi_valid_in[WideB] = ChimneyCfgW.EnMgrPort && floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == WideB); assign axi_valid_in[WideAw] = floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideAw); assign axi_valid_in[WideW] = floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideW); - assign axi_valid_in[WideR] = EnWideMgrPort && floo_wide_in_valid && + assign axi_valid_in[WideR] = ChimneyCfgW.EnMgrPort && floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideR); assign axi_ready_out[NarrowAw] = axi_narrow_meta_buf_rsp_out.aw_ready; @@ -1398,44 +1374,34 @@ module floo_vc_narrow_wide_chimney assign atop_has_r_rsp = AtopSupport && axi_valid_in[NarrowAw] && axi_narrow_unpack_aw.atop[axi_pkg::ATOP_R_RESP]; - assign narrow_aw_out_data_in = '{ + assign narrow_aw_buf_hdr_in = '{ id: axi_narrow_unpack_aw.id, - rob_req: floo_req_in.narrow_aw.hdr.rob_req, - rob_idx: floo_req_in.narrow_aw.hdr.rob_idx, - src_id: floo_req_in.narrow_aw.hdr.src_id, - atop: floo_req_in.narrow_aw.hdr.atop + hdr: floo_req_unpack_generic.hdr }; - assign narrow_ar_out_data_in = '{ + assign narrow_ar_buf_hdr_in = '{ id: (is_atop && atop_has_r_rsp)? axi_narrow_unpack_aw.id : axi_narrow_unpack_ar.id, - rob_req: floo_req_in.narrow_ar.hdr.rob_req, - rob_idx: floo_req_in.narrow_ar.hdr.rob_idx, - src_id: floo_req_in.narrow_ar.hdr.src_id, - atop: floo_req_in.narrow_ar.hdr.atop + hdr: floo_req_unpack_generic.hdr }; - assign wide_aw_out_data_in = '{ + assign wide_aw_buf_hdr_in = '{ id: axi_wide_unpack_aw.id, - rob_req: floo_wide_in.wide_aw.hdr.rob_req, - rob_idx: floo_wide_in.wide_aw.hdr.rob_idx, - src_id: floo_wide_in.wide_aw.hdr.src_id + hdr: floo_wide_unpack_generic.hdr }; - assign wide_ar_out_data_in = '{ + assign wide_ar_buf_hdr_in = '{ id: axi_wide_unpack_ar.id, - rob_req: floo_req_in.wide_ar.hdr.rob_req, - rob_idx: floo_req_in.wide_ar.hdr.rob_idx, - src_id: floo_req_in.wide_ar.hdr.src_id + hdr: floo_req_unpack_generic.hdr }; - if (EnNarrowSbrPort) begin : gen_narrow_mgr_port + if (ChimneyCfgN.EnSbrPort) begin : gen_narrow_mgr_port floo_meta_buffer #( - .MaxTxns ( NarrowMaxTxns ), - .MaxUniqueIds ( NarrowMaxUniqueIds ), - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( MaxAtomicTxns ), - .buf_t ( narrow_id_out_buf_t ), - .axi_in_req_t ( axi_narrow_in_req_t ), - .axi_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_out_req_t ( axi_narrow_out_req_t ), - .axi_out_rsp_t ( axi_narrow_out_rsp_t ) + .MaxTxns ( ChimneyCfgN.MaxTxns ), + .MaxUniqueIds ( ChimneyCfgN.MaxUniqueIds ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .buf_t ( narrow_meta_buf_t ), + .axi_in_req_t ( axi_narrow_in_req_t ), + .axi_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_out_req_t ( axi_narrow_out_req_t ), + .axi_out_rsp_t ( axi_narrow_out_rsp_t ) ) i_narrow_meta_buffer ( .clk_i, .rst_ni, @@ -1444,14 +1410,14 @@ module floo_vc_narrow_wide_chimney .axi_rsp_o ( axi_narrow_meta_buf_rsp_out ), .axi_req_o ( axi_narrow_out_req_o ), .axi_rsp_i ( axi_narrow_out_rsp_i ), - .aw_buf_i ( narrow_aw_out_data_in ), - .ar_buf_i ( narrow_ar_out_data_in ), - .r_buf_o ( narrow_ar_out_data_out ), - .b_buf_o ( narrow_aw_out_data_out ) + .aw_buf_i ( narrow_aw_buf_hdr_in ), + .ar_buf_i ( narrow_ar_buf_hdr_in ), + .r_buf_o ( narrow_ar_buf_hdr_out ), + .b_buf_o ( narrow_aw_buf_hdr_out ) ); end else begin : gen_no_narrow_mgr_port axi_err_slv #( - .AxiIdWidth ( AxiNarrowInIdWidth ), + .AxiIdWidth ( AxiCfgN.InIdWidth ), .ATOPs ( AtopSupport ), .axi_req_t ( axi_narrow_in_req_t ), .axi_resp_t ( axi_narrow_in_rsp_t ) @@ -1463,21 +1429,21 @@ module floo_vc_narrow_wide_chimney .slv_resp_o ( axi_narrow_meta_buf_rsp_out ) ); assign axi_narrow_out_req_o = '0; - assign narrow_ar_out_data_out = '0; - assign narrow_aw_out_data_out = '0; + assign narrow_ar_buf_hdr_out = '0; + assign narrow_aw_buf_hdr_out = '0; end - if (EnWideSbrPort) begin : gen_wide_mgr_port + if (ChimneyCfgW.EnSbrPort) begin : gen_wide_mgr_port floo_meta_buffer #( - .MaxTxns ( WideMaxTxns ), - .MaxUniqueIds ( WideMaxUniqueIds ), - .AtopSupport ( 1'b0 ), - .MaxAtomicTxns ( '0 ), - .buf_t ( wide_id_out_buf_t ), - .axi_in_req_t ( axi_wide_in_req_t ), - .axi_in_rsp_t ( axi_wide_in_rsp_t ), - .axi_out_req_t ( axi_wide_out_req_t ), - .axi_out_rsp_t ( axi_wide_out_rsp_t ) + .MaxTxns ( ChimneyCfgW.MaxTxns ), + .MaxUniqueIds ( ChimneyCfgW.MaxUniqueIds ), + .AtopSupport ( 1'b0 ), + .MaxAtomicTxns ( '0 ), + .buf_t ( wide_meta_buf_t ), + .axi_in_req_t ( axi_wide_in_req_t ), + .axi_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_out_req_t ( axi_wide_out_req_t ), + .axi_out_rsp_t ( axi_wide_out_rsp_t ) ) i_wide_meta_buffer ( .clk_i, .rst_ni, @@ -1486,14 +1452,14 @@ module floo_vc_narrow_wide_chimney .axi_rsp_o ( axi_wide_meta_buf_rsp_out ), .axi_req_o ( axi_wide_out_req_o ), .axi_rsp_i ( axi_wide_out_rsp_i ), - .aw_buf_i ( wide_aw_out_data_in ), - .ar_buf_i ( wide_ar_out_data_in ), - .r_buf_o ( wide_ar_out_data_out ), - .b_buf_o ( wide_aw_out_data_out ) + .aw_buf_i ( wide_aw_buf_hdr_in ), + .ar_buf_i ( wide_ar_buf_hdr_in ), + .r_buf_o ( wide_ar_buf_hdr_out ), + .b_buf_o ( wide_aw_buf_hdr_out ) ); end else begin : gen_no_wide_mgr_port axi_err_slv #( - .AxiIdWidth ( AxiWideInIdWidth ), + .AxiIdWidth ( AxiCfgN.InIdWidth ), .ATOPs ( 1'b1 ), .axi_req_t ( axi_wide_in_req_t ), .axi_resp_t ( axi_wide_in_rsp_t ) @@ -1505,8 +1471,8 @@ module floo_vc_narrow_wide_chimney .slv_resp_o ( axi_wide_meta_buf_rsp_out ) ); assign axi_wide_out_req_o = '0; - assign wide_ar_out_data_out = '0; - assign wide_aw_out_data_out = '0; + assign wide_ar_buf_hdr_out = '0; + assign wide_aw_buf_hdr_out = '0; end // Registers @@ -1518,40 +1484,42 @@ module floo_vc_narrow_wide_chimney // ASSERTIONS // ///////////////// + // Check that the Address Width of the narrow and Wide interfaces are the same + `ASSERT_INIT(AddrWidthMatch, AxiCfgN.AddrWidth == AxiCfgW.AddrWidth) + // Multiple outstanding atomics need to use different IDs // Non-atomic transactions all use the same ID - `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**AxiNarrowOutIdWidth) + `ASSERT_INIT(ToSmallIdWidth, 1 + AtopSupport * MaxAtomicTxns <= 2**AxiCfgN.OutIdWidth) // If Network Interface has no subordinate port, make sure that `RoBType` is `NoRoB` - `ASSERT_INIT(NoNarrowMgrPortRobType, EnNarrowMgrPort || (NarrowRoBType == NoRoB)) - `ASSERT_INIT(NoWideMgrPortRobType, EnWideMgrPort || (WideRoBType == NoRoB)) - - // Check that all addresses have the same width - `ASSERT_INIT(SameAddrWidth1, AxiNarrowInAddrWidth == AxiNarrowOutAddrWidth) - `ASSERT_INIT(SameAddrWidth2, AxiWideInAddrWidth == AxiNarrowOutAddrWidth) - `ASSERT_INIT(SameAddrWidth3, AxiWideInAddrWidth == AxiWideOutAddrWidth) + `ASSERT_INIT(NoNarrowMgrPortRobType, ChimneyCfgN.EnMgrPort || + (ChimneyCfgN.BRoBType == floo_pkg::NoRoB && + ChimneyCfgN.RRoBType == floo_pkg::NoRoB)) + `ASSERT_INIT(NoWideMgrPortRobType, ChimneyCfgW.EnMgrPort || + (ChimneyCfgW.BRoBType == floo_pkg::NoRoB && + ChimneyCfgW.RRoBType == floo_pkg::NoRoB)) // Network Interface cannot accept any B and R responses if `En*MgrPort` are not set - `ASSERT(NoNarrowMgrPortBResponse, EnNarrowMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoNarrowMgrPortBResponse, ChimneyCfgN.EnMgrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowB))) - `ASSERT(NoNarrowMgrPortRResponse, EnNarrowMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoNarrowMgrPortRResponse, ChimneyCfgN.EnMgrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowR))) - `ASSERT(NoWideMgrPortBResponse, EnWideMgrPort || !(floo_rsp_in_valid && + `ASSERT(NoWideMgrPortBResponse, ChimneyCfgW.EnMgrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == WideB))) - `ASSERT(NoWideMgrPortRResponse, EnWideMgrPort || !(floo_wide_in_valid && + `ASSERT(NoWideMgrPortRResponse, ChimneyCfgW.EnMgrPort || !(floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideR))) // Network Interface cannot accept any AW, AR and W requests if `En*SbrPort` is not set - `ASSERT(NoNarrowSbrPortAwRequest, EnNarrowSbrPort || !(floo_req_in_valid && + `ASSERT(NoNarrowSbrPortAwRequest, ChimneyCfgN.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowAw))) - `ASSERT(NoNarrowSbrPortArRequest, EnNarrowSbrPort || !(floo_req_in_valid && + `ASSERT(NoNarrowSbrPortArRequest, ChimneyCfgN.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowAr))) - `ASSERT(NoNarrowSbrPortWRequest, EnNarrowSbrPort || !(floo_req_in_valid && + `ASSERT(NoNarrowSbrPortWRequest, ChimneyCfgN.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowW))) - `ASSERT(NoWideSbrPortAwRequest, EnWideSbrPort || !(floo_req_in_valid && + `ASSERT(NoWideSbrPortAwRequest, ChimneyCfgW.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAw))) - `ASSERT(NoWideSbrPortArRequest, EnWideSbrPort || !(floo_req_in_valid && + `ASSERT(NoWideSbrPortArRequest, ChimneyCfgW.EnSbrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAr))) - `ASSERT(NoWideSbrPortWRequest, EnWideSbrPort || !(floo_wide_in_valid && + `ASSERT(NoWideSbrPortWRequest, ChimneyCfgW.EnSbrPort || !(floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideW))) // all inputs need to go to vc 0 since there is only one vc `ASSERT(OnlyVC0Req, floo_req_i.req.generic.hdr.vc_id == '0 || !floo_req_i.valid) diff --git a/hw/floo_vc_narrow_wide_router.sv b/hw/floo_nw_vc_router.sv similarity index 72% rename from hw/floo_vc_narrow_wide_router.sv rename to hw/floo_nw_vc_router.sv index 2b5a7695..52e11479 100644 --- a/hw/floo_vc_narrow_wide_router.sv +++ b/hw/floo_nw_vc_router.sv @@ -5,46 +5,55 @@ // Tim Fischer // Lukas Berner +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" + /// Wrapper of a multi-link router for narrow and wide links -module floo_vc_narrow_wide_router +module floo_nw_vc_router import floo_pkg::*; - import floo_vc_narrow_wide_pkg::*; - #( - parameter int NumPorts = 5, - parameter int NumLocalPorts = NumPorts - 4, - parameter int NumVC [NumPorts] = - {1+NumLocalPorts, 3+NumLocalPorts, 1+NumLocalPorts, 3+NumLocalPorts, 4+NumLocalPorts-1}, - // Num VC from dir N,E,S,W,L0(,L1,L2,L3): 1313 for XY routing - parameter int NumVCMax = NumPorts - 1, - // NumVCWidth: needs to be 3 in routers with more than 1 local ports - parameter int NumVCWidth = 3, - // set this to 3 towards routers with more than 1 local ports: towards N,E,S,W,L0(,L1,L2,L3) - parameter int NumVCToOut [NumPorts] = {2,4,2,4,1}, - parameter int NumVCToOutMax = 4, - parameter int NumVCWidthToOutMax = 2, - - parameter int NumInputSaGlobal[NumPorts] = - {3+NumLocalPorts, 1+NumLocalPorts, 3+NumLocalPorts, 1+NumLocalPorts, 4+NumLocalPorts-1}, - // to dir N,E,S,W,L0(,L1,L2,L3) - parameter int VCDepth = 2, - parameter int VCDepthWidth = $clog2(VCDepth+1), - parameter int CreditShortcut = 1, // not used if SingleStage - parameter int AllowVCOverflow = 1, // 1: FVADA, 0: fixed VC per direction - parameter int FixedWormholeVC = 1, - parameter int WormholeVCId [NumPorts] = {0,1,0,2,0}, // as seen from output port - parameter int WormholeVCDepth = 3, - parameter int AllowOverflowFromDeeperVC = 1, //overriden if AllowVCOverflow is 0 - parameter int UpdateRRArbIfNotSent = 0, - parameter int SingleStage = 0, // 0: standard 2 stage, 1: single stage - - // Route Algorithm stuff - parameter route_algo_e RouteAlgo = XYRouting, - /// Used for ID-based and XY routing - parameter int unsigned IdWidth = 1, - parameter type id_t = logic[IdWidth-1:0], - /// Used for ID-based routing - parameter int unsigned NumAddrRules = 0, - parameter type addr_rule_t = logic +#( + parameter floo_pkg::axi_cfg_t AxiCfgN = '0, + parameter floo_pkg::axi_cfg_t AxiCfgW = '0, + parameter int NumPorts = 5, + parameter int NumLocalPorts = NumPorts - 4, + parameter int NumVC [NumPorts] = + {1+NumLocalPorts, 3+NumLocalPorts, 1+NumLocalPorts, 3+NumLocalPorts, 4+NumLocalPorts-1}, + // Num VC from dir N,E,S,W,L0(,L1,L2,L3): 1313 for XY routing + parameter int NumVCMax = NumPorts - 1, + // NumVCWidth: needs to be 3 in routers with more than 1 local ports + parameter int NumVCWidth = 3, + // set this to 3 towards routers with more than 1 local ports: towards N,E,S,W,L0(,L1,L2,L3) + parameter int NumVCToOut [NumPorts] = {2,4,2,4,1}, + parameter int NumVCToOutMax = 4, + parameter int NumVCWidthToOutMax = 2, + + parameter int NumInputSaGlobal[NumPorts] = + {3+NumLocalPorts, 1+NumLocalPorts, 3+NumLocalPorts, 1+NumLocalPorts, 4+NumLocalPorts-1}, + // to dir N,E,S,W,L0(,L1,L2,L3) + parameter int VCDepth = 2, + parameter int VCDepthWidth = $clog2(VCDepth+1), + parameter int CreditShortcut = 1, // not used if SingleStage + parameter int AllowVCOverflow = 1, // 1: FVADA, 0: fixed VC per direction + parameter int FixedWormholeVC = 1, + parameter int WormholeVCId [NumPorts] = {0,1,0,2,0}, // as seen from output port + parameter int WormholeVCDepth = 3, + parameter int AllowOverflowFromDeeperVC = 1, //overriden if AllowVCOverflow is 0 + parameter int UpdateRRArbIfNotSent = 0, + parameter int SingleStage = 0, // 0: standard 2 stage, 1: single stage + + // Route Algorithm stuff + parameter route_algo_e RouteAlgo = XYRouting, + /// Used for ID-based and XY routing + parameter int unsigned IdWidth = 1, + parameter type id_t = logic[IdWidth-1:0], + parameter type hdr_t = logic, + parameter type vc_id_t = logic, + /// Used for ID-based routing + parameter int unsigned NumAddrRules = 0, + parameter type addr_rule_t = logic, + parameter type floo_vc_req_t = logic, + parameter type floo_vc_rsp_t = logic, + parameter type floo_vc_wide_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -60,6 +69,23 @@ module floo_vc_narrow_wide_router output floo_vc_wide_t [NumPorts-1:0] floo_wide_o ); + typedef logic [AxiCfgN.AddrWidth-1:0] axi_addr_t; + typedef logic [AxiCfgN.InIdWidth-1:0] axi_narrow_in_id_t; + typedef logic [AxiCfgN.UserWidth-1:0] axi_narrow_user_t; + typedef logic [AxiCfgN.DataWidth-1:0] axi_narrow_data_t; + typedef logic [AxiCfgN.DataWidth/8-1:0] axi_narrow_strb_t; + typedef logic [AxiCfgW.InIdWidth-1:0] axi_wide_in_id_t; + typedef logic [AxiCfgW.UserWidth-1:0] axi_wide_user_t; + typedef logic [AxiCfgW.DataWidth-1:0] axi_wide_data_t; + typedef logic [AxiCfgW.DataWidth/8-1:0] axi_wide_strb_t; + + // (Re-) definitons of `axi_in` and `floo` types, for transport + `AXI_TYPEDEF_ALL_CT(axi_narrow, axi_narrow_req_t, axi_narrow_rsp_t, axi_addr_t, + axi_narrow_in_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_narrow_user_t) + `AXI_TYPEDEF_ALL_CT(axi_wide, axi_wide_req_t, axi_wide_rsp_t, axi_addr_t, + axi_wide_in_id_t, axi_wide_data_t, axi_wide_strb_t, axi_wide_user_t) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow, axi_wide, AxiCfgN, AxiCfgW, hdr_t) + floo_req_chan_t [NumPorts-1:0] req_in, req_out; floo_rsp_chan_t [NumPorts-1:0] rsp_in, rsp_out; floo_wide_chan_t [NumPorts-1:0] wide_in, wide_out; diff --git a/hw/floo_pkg.sv b/hw/floo_pkg.sv index bf399fcb..c43f67c5 100644 --- a/hw/floo_pkg.sv +++ b/hw/floo_pkg.sv @@ -9,6 +9,7 @@ /// Currently only contains useful functions and some constants and typedefs package floo_pkg; + // Support Routing Algorithms typedef enum logic[1:0] { IdIsPort, IdTable, @@ -38,4 +39,181 @@ package floo_pkg; NoRoB } rob_type_e; + typedef enum logic [2:0] { + AxiAw = 3'd0, + AxiW = 3'd1, + AxiAr = 3'd2, + AxiB = 3'd3, + AxiR = 3'd4, + NumAxiChannels = 3'd5 + } axi_ch_e; + + typedef enum logic [3:0] { + NarrowAw = 4'd0, + NarrowW = 4'd1, + NarrowAr = 4'd2, + WideAr = 4'd3, + NarrowB = 4'd4, + NarrowR = 4'd5, + WideB = 4'd6, + WideAw = 4'd7, + WideW = 4'd8, + WideR = 4'd9, + NumNWAxiChannels = 4'd10 + } nw_ch_e; + + typedef enum logic [1:0] { + FlooReq = 2'd0, + FlooRsp = 2'd1, + FlooWide = 2'd2 + } floo_chan_e; + + typedef struct packed { + int unsigned AddrWidth; + int unsigned DataWidth; + int unsigned UserWidth; + int unsigned InIdWidth; + int unsigned OutIdWidth; + } axi_cfg_t; + + typedef struct packed { + route_algo_e RouteAlgo; + bit UseIdTable; + int unsigned XYAddrOffsetX; + int unsigned XYAddrOffsetY; + int unsigned IdAddrOffset; + int unsigned NumAddrRules; + int unsigned SamNumRules; + int unsigned NumRoutes; + } route_cfg_t; + + typedef struct packed { + bit EnSbrPort; + bit EnMgrPort; + int unsigned MaxTxns; + int unsigned MaxUniqueIds; + int unsigned MaxTxnsPerId; + rob_type_e BRoBType; + int unsigned BRoBDepth; + rob_type_e RRoBType; + int unsigned RRoBDepth; + bit CutAx; + bit CutRsp; + } chimney_cfg_t; + + localparam chimney_cfg_t ChimneyDefaultCfg = '{ + EnSbrPort: 1'b1, + EnMgrPort: 1'b1, + MaxTxns: 32, + MaxUniqueIds: 1, + MaxTxnsPerId: 32, + BRoBType: NoRoB, + BRoBDepth: 0, + RRoBType: NoRoB, + RRoBDepth: 0, + CutAx: 1'b0, + CutRsp: 1'b0 + }; + + localparam route_cfg_t RouteDefaultCfg = '{ + RouteAlgo: XYRouting, + UseIdTable: 1'b0, + XYAddrOffsetX: 0, + XYAddrOffsetY: 0, + IdAddrOffset: 0, + NumAddrRules: 0, + SamNumRules: 0, + NumRoutes: 0 + }; + + function automatic floo_chan_e axi_chan_mapping(axi_ch_e ch); + if (ch == AxiAw || ch == AxiW || ch == AxiAr) begin + return FlooReq; + end else begin + return FlooRsp; + end + endfunction + + function automatic floo_chan_e nw_chan_mapping(nw_ch_e ch); + if (ch == NarrowAw || ch == NarrowW || ch == NarrowAr || ch == WideAr) begin + return FlooReq; + end else if (ch == WideAw || ch == WideW || ch == WideR) begin + return FlooWide; + end else begin + return FlooRsp; + end + endfunction + + function automatic axi_cfg_t axi_cfg_swap_iw(axi_cfg_t cfg); + return '{ + AddrWidth: cfg.AddrWidth, + DataWidth: cfg.DataWidth, + UserWidth: cfg.UserWidth, + InIdWidth: cfg.OutIdWidth, + OutIdWidth: cfg.InIdWidth + }; + endfunction + + function automatic int unsigned get_axi_chan_width(axi_cfg_t cfg, axi_ch_e ch); + case (ch) + AxiAw: return axi_pkg::aw_width(cfg.AddrWidth, cfg.InIdWidth, cfg.UserWidth); + AxiW: return axi_pkg::w_width(cfg.DataWidth, cfg.UserWidth); + AxiB: return axi_pkg::b_width(cfg.InIdWidth, cfg.UserWidth); + AxiAr: return axi_pkg::ar_width(cfg.AddrWidth, cfg.InIdWidth, cfg.UserWidth); + AxiR: return axi_pkg::r_width(cfg.DataWidth, cfg.InIdWidth, cfg.UserWidth); + default: $error("Invalid AXI channel"); + endcase + endfunction + + function automatic int unsigned get_nw_chan_width(axi_cfg_t cfg_n, axi_cfg_t cfg_w, nw_ch_e ch); + case (ch) + NarrowAw: return axi_pkg::aw_width(cfg_n.AddrWidth, cfg_n.InIdWidth, cfg_n.UserWidth); + NarrowW: return axi_pkg::w_width(cfg_n.DataWidth, cfg_n.UserWidth); + NarrowAr: return axi_pkg::ar_width(cfg_n.AddrWidth, cfg_n.InIdWidth, cfg_n.UserWidth); + NarrowB: return axi_pkg::b_width(cfg_n.InIdWidth, cfg_n.UserWidth); + NarrowR: return axi_pkg::r_width(cfg_n.DataWidth, cfg_n.InIdWidth, cfg_n.UserWidth); + WideAw: return axi_pkg::aw_width(cfg_w.AddrWidth, cfg_w.InIdWidth, cfg_w.UserWidth); + WideW: return axi_pkg::w_width(cfg_w.DataWidth, cfg_w.UserWidth); + WideR: return axi_pkg::r_width(cfg_w.DataWidth, cfg_w.InIdWidth, cfg_w.UserWidth); + WideAr: return axi_pkg::ar_width(cfg_w.AddrWidth, cfg_w.InIdWidth, cfg_w.UserWidth); + WideB: return axi_pkg::b_width(cfg_w.InIdWidth, cfg_w.UserWidth); + default: $error("Invalid AXI channel"); + endcase + endfunction + + function automatic int unsigned get_max_axi_payload_bits(axi_cfg_t cfg, floo_chan_e ch); + int unsigned max_payload_bits = 0; + for (int unsigned i = 0; i < NumAxiChannels; i++) begin + if (axi_chan_mapping(axi_ch_e'(i)) == ch) begin + if (get_axi_chan_width(cfg, axi_ch_e'(i)) > max_payload_bits) begin + max_payload_bits = get_axi_chan_width(cfg, axi_ch_e'(i)); + end + end + end + return max_payload_bits + 1; // +1 because we need at least one `rsvd` bit + endfunction + + function automatic int unsigned get_max_nw_payload_bits( + axi_cfg_t cfg_n, axi_cfg_t cfg_w, floo_chan_e ch); + int unsigned max_payload_bits = 0; + for (int unsigned i = 0; i < NumNWAxiChannels; i++) begin + if (nw_chan_mapping(nw_ch_e'(i)) == ch) begin + if (get_nw_chan_width(cfg_n, cfg_w, nw_ch_e'(i)) > max_payload_bits) begin + max_payload_bits = get_nw_chan_width(cfg_n, cfg_w, nw_ch_e'(i)); + end + end + end + return max_payload_bits + 1; // +1 because we need at least one `rsvd` bit + endfunction + + function automatic int unsigned get_axi_rsvd_bits(axi_cfg_t cfg, axi_ch_e ch); + return get_max_axi_payload_bits(cfg, axi_chan_mapping(ch)) - + get_axi_chan_width(cfg, ch); + endfunction + + function automatic int unsigned get_nw_rsvd_bits(axi_cfg_t cfg_n, axi_cfg_t cfg_w, nw_ch_e ch); + return get_max_nw_payload_bits(cfg_n, cfg_w, nw_chan_mapping(ch)) - + get_nw_chan_width(cfg_n, cfg_w, ch); + endfunction + endpackage diff --git a/hw/floo_rob.sv b/hw/floo_rob.sv index 1041de18..548a76b7 100644 --- a/hw/floo_rob.sv +++ b/hw/floo_rob.sv @@ -15,7 +15,7 @@ module floo_rob #( /// metadata will be stored in normal FFs parameter bit OnlyMetaData = 1'b0, /// Size of the reorder buffer - parameter int unsigned ReorderBufferSize = 32'd64, + parameter int unsigned RoBDepth = 32'd64, /// Data type of response to be reordered parameter type ax_len_t = logic, parameter type ax_id_t = logic, @@ -54,7 +54,7 @@ module floo_rob #( localparam int unsigned NumIds = 2**AxiIdWidth; typedef logic[AxiIdWidth-1:0] axi_id_t; typedef logic[$clog2(NumIds)-1:0] num_id_t; - typedef logic[ReorderBufferSize-1:0] rob_flag_t; + typedef logic[RoBDepth-1:0] rob_flag_t; ///////////////////////// // Transaction Table // @@ -121,10 +121,10 @@ module floo_rob #( if (!OnlyMetaData) begin : gen_rob_sram tc_sram_impl #( - .NumWords (ReorderBufferSize), - .DataWidth ($bits(rsp_data_t)), - .NumPorts ( 1 ), - .impl_in_t ( sram_cfg_t ) + .NumWords ( RoBDepth ), + .DataWidth ( $bits(rsp_data_t) ), + .NumPorts ( 1 ), + .impl_in_t ( sram_cfg_t ) ) i_reorder_buffer ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -141,7 +141,7 @@ module floo_rob #( assign rob_rdata = '0; end - rsp_meta_t [ReorderBufferSize-1:0] rob_meta_q, rob_meta_d; + rsp_meta_t [RoBDepth-1:0] rob_meta_q, rob_meta_d; rob_flag_t rob_valid_q, rob_valid_d; rob_flag_t rob_alloc_q, rob_alloc_d; rob_idx_t rob_free_space; @@ -152,11 +152,11 @@ module floo_rob #( `FF(rsp_out_valid_q, rsp_out_valid_d, '0) `FFL(rob_meta_q, rob_meta_d, rob_req && rob_wen, '0) - assign rob_next_free_idx = ReorderBufferSize - rob_free_space; + assign rob_next_free_idx = RoBDepth - rob_free_space; lzc #( - .WIDTH ( ReorderBufferSize ), - .MODE ( 1'b1 ) + .WIDTH ( RoBDepth ), + .MODE ( 1'b1 ) ) i_lzc ( .in_i ( rob_alloc_q ), .cnt_o ( rob_free_space ), @@ -277,7 +277,9 @@ module floo_rob #( // If the peeked ID has a valid entry and there is data in the RoB, // we can release the response from the RoB to make place for new requests - if (st_peek_valid && rob_valid_q[st_peek_rob_idx + read_rob_idx_offset_q[st_rob_peek_id_q]]) begin + if (st_peek_valid && rob_valid_q[st_peek_rob_idx + + read_rob_idx_offset_q[st_rob_peek_id_q]]) + begin rob_state_d = RoBRead; // Don't forward the current response, since we are releasing one from the RoB rsp_valid_o = 1'b0; @@ -322,7 +324,8 @@ module floo_rob #( rsp_ready_o = 1'b1; rob_valid_d[rob_addr] = 1'b1; rob_meta_d[rob_addr] = rob_meta; - write_rob_idx_offset_d[st_rsp_out_id] = (rsp_last_i)? '0 : write_rob_idx_offset_q[st_rsp_out_id] + 1; + write_rob_idx_offset_d[st_rsp_out_id] = (rsp_last_i)? + '0 : write_rob_idx_offset_q[st_rsp_out_id] + 1; end end end diff --git a/hw/floo_rob_wrapper.sv b/hw/floo_rob_wrapper.sv index 855c3358..f96f5602 100644 --- a/hw/floo_rob_wrapper.sv +++ b/hw/floo_rob_wrapper.sv @@ -17,7 +17,7 @@ module floo_rob_wrapper /// metadata will be stored in normal FFs parameter bit OnlyMetaData = 1'b0, /// Size of the reorder buffer - parameter int unsigned ReorderBufferSize = 32'd64, + parameter int unsigned RoBDepth = 32'd64, /// Data type of response to be reordered parameter type ax_len_t = logic, parameter type ax_id_t = logic, @@ -54,17 +54,17 @@ module floo_rob_wrapper if (RoBType == NormalRoB) begin : gen_normal_rob floo_rob #( - .ReorderBufferSize ( ReorderBufferSize ), - .MaxRoTxnsPerId ( MaxRoTxnsPerId ), - .OnlyMetaData ( OnlyMetaData ), - .ax_len_t ( ax_len_t ), - .ax_id_t ( ax_id_t ), - .rsp_chan_t ( rsp_chan_t ), - .rsp_data_t ( rsp_data_t ), - .rsp_meta_t ( rsp_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( dest_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBDepth ( RoBDepth ), + .MaxRoTxnsPerId ( MaxRoTxnsPerId ), + .OnlyMetaData ( OnlyMetaData ), + .ax_len_t ( ax_len_t ), + .ax_id_t ( ax_id_t ), + .rsp_chan_t ( rsp_chan_t ), + .rsp_data_t ( rsp_data_t ), + .rsp_meta_t ( rsp_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( dest_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_rob ( .clk_i, .rst_ni, @@ -91,16 +91,16 @@ module floo_rob_wrapper end else if (RoBType == SimpleRoB) begin : gen_simpl_rob floo_simple_rob #( - .ReorderBufferSize ( ReorderBufferSize ), - .MaxRoTxnsPerId ( MaxRoTxnsPerId ), - .OnlyMetaData ( OnlyMetaData ), - .ax_len_t ( ax_len_t ), - .rsp_chan_t ( rsp_chan_t ), - .rsp_data_t ( rsp_data_t ), - .rsp_meta_t ( rsp_meta_t ), - .rob_idx_t ( rob_idx_t ), - .dest_t ( dest_t ), - .sram_cfg_t ( sram_cfg_t ) + .RoBDepth ( RoBDepth ), + .MaxRoTxnsPerId ( MaxRoTxnsPerId ), + .OnlyMetaData ( OnlyMetaData ), + .ax_len_t ( ax_len_t ), + .rsp_chan_t ( rsp_chan_t ), + .rsp_data_t ( rsp_data_t ), + .rsp_meta_t ( rsp_meta_t ), + .rob_idx_t ( rob_idx_t ), + .dest_t ( dest_t ), + .sram_cfg_t ( sram_cfg_t ) ) i_rob ( .clk_i, .rst_ni, diff --git a/hw/floo_route_comp.sv b/hw/floo_route_comp.sv index 4ce7aa1b..a52f3614 100644 --- a/hw/floo_route_comp.sv +++ b/hw/floo_route_comp.sv @@ -9,23 +9,9 @@ module floo_route_comp import floo_pkg::*; #( - /// The type of routing algorithms to use - parameter route_algo_e RouteAlgo = IdTable, - /// Whether to use a routing table with address decoder - /// In case of XY Routing or the coordinates should be - /// directly read from the request address - parameter bit UseIdTable = 1'b1, - /// The offset bit to read the X coordinate from - parameter int unsigned XYAddrOffsetX = 0, - /// The offset bit to read the Y coordinate from - parameter int unsigned XYAddrOffsetY = 0, - /// The offset bit to read the ID from - parameter int unsigned IdAddrOffset = 0, - /// The number of possible rules - parameter int unsigned NumAddrRules = 0, - /// The number of possible routes - parameter int unsigned NumRoutes = 0, - /// The type of the coordinates or IDs + /// The route config + parameter floo_pkg::route_cfg_t RouteCfg = '0, + parameter bit UseIdTable = RouteCfg.UseIdTable, parameter type id_t = logic, /// The type of the address parameter type addr_t = logic, @@ -38,8 +24,8 @@ module floo_route_comp input logic rst_ni, input id_t id_i, input addr_t addr_i, - input addr_rule_t [NumAddrRules-1:0] addr_map_i, - input route_t [NumRoutes-1:0] route_table_i, + input addr_rule_t [RouteCfg.NumAddrRules-1:0] addr_map_i, + input route_t [RouteCfg.NumRoutes-1:0] route_table_i, output route_t route_o, output id_t id_o ); @@ -51,9 +37,9 @@ module floo_route_comp // The reason for that is that a request destination is given by a physical address, while the // response destination is given by the ID of the source. if (UseIdTable && - ((RouteAlgo == IdTable) || - (RouteAlgo == XYRouting) || - (RouteAlgo == SourceRouting))) + ((RouteCfg.RouteAlgo == IdTable) || + (RouteCfg.RouteAlgo == XYRouting) || + (RouteCfg.RouteAlgo == SourceRouting))) begin : gen_table_routing logic dec_error; @@ -63,7 +49,7 @@ module floo_route_comp addr_decode #( .NoIndices ( MaxPossibleId ), - .NoRules ( NumAddrRules ), + .NoRules ( RouteCfg.NumAddrRules ), .addr_t ( addr_t ), .rule_t ( addr_rule_t ), .idx_t ( id_t ) @@ -78,18 +64,18 @@ module floo_route_comp ); `ASSERT(DecodeError, !dec_error) - end else if (RouteAlgo == XYRouting) begin : gen_xy_bits_routing + end else if (RouteCfg.RouteAlgo == XYRouting) begin : gen_xy_bits_routing assign id_o.port_id = '0; - assign id_o.x = addr_i[XYAddrOffsetX +: $bits(id_o.x)]; - assign id_o.y = addr_i[XYAddrOffsetY +: $bits(id_o.y)]; - end else if (RouteAlgo == IdTable) begin : gen_id_bits_routing - assign id_o = addr_i[IdAddrOffset +: $bits(id_o)]; - end else if (RouteAlgo == SourceRouting) begin : gen_source_routing + assign id_o.x = addr_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)]; + assign id_o.y = addr_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)]; + end else if (RouteCfg.RouteAlgo == IdTable) begin : gen_id_bits_routing + assign id_o = addr_i[RouteCfg.IdAddrOffset +: $bits(id_o)]; + end else if (RouteCfg.RouteAlgo == SourceRouting) begin : gen_source_routing // Nothing to do here end else begin : gen_error $fatal(1, "Routing algorithm not implemented"); end - if (RouteAlgo == SourceRouting) begin : gen_route + if (RouteCfg.RouteAlgo == SourceRouting) begin : gen_route assign route_o = (UseIdTable)? route_table_i[id_o] : route_table_i[id_i]; end else begin : gen_no_route assign route_o = '0; diff --git a/hw/floo_router.sv b/hw/floo_router.sv index 1a6ffdab..966c90f8 100644 --- a/hw/floo_router.sv +++ b/hw/floo_router.sv @@ -7,13 +7,15 @@ `include "common_cells/assertions.svh" /// A simple router with configurable number of ports, physical and virtual channels, and input/output buffers -module floo_router import floo_pkg::*; #( +module floo_router + import floo_pkg::*; +#( parameter int unsigned NumRoutes = 0, parameter int unsigned NumVirtChannels = 0, parameter int unsigned NumPhysChannels = 1, parameter type flit_t = logic, - parameter int unsigned ChannelFifoDepth = 0, - parameter int unsigned OutputFifoDepth = 0, + parameter int unsigned InFifoDepth = 0, + parameter int unsigned OutFifoDepth = 0, parameter route_algo_e RouteAlgo = IdTable, /// Used for ID-based and XY routing parameter int unsigned IdWidth = 0, @@ -65,7 +67,7 @@ module floo_router import floo_pkg::*; #( (* ungroup *) stream_fifo_optimal_wrap #( - .Depth ( ChannelFifoDepth ), + .Depth ( InFifoDepth ), .type_t ( flit_t ) ) i_stream_fifo ( .clk_i ( clk_i ), @@ -169,10 +171,10 @@ module floo_router import floo_pkg::*; #( .data_o ( out_data [out_route][v_chan] ) ); - if (OutputFifoDepth > 0) begin : gen_out_fifo + if (OutFifoDepth > 0) begin : gen_out_fifo (* ungroup *) stream_fifo_optimal_wrap #( - .Depth ( OutputFifoDepth ), + .Depth ( OutFifoDepth ), .type_t ( flit_t ) ) i_stream_fifo ( .clk_i ( clk_i ), diff --git a/hw/floo_simple_rob.sv b/hw/floo_simple_rob.sv index af51d734..70d33f10 100644 --- a/hw/floo_simple_rob.sv +++ b/hw/floo_simple_rob.sv @@ -19,17 +19,17 @@ module floo_simple_rob #( /// metadata will be stored in SCMs parameter bit OnlyMetaData = 1'b0, /// Size of the reorder buffer - parameter int unsigned ReorderBufferSize = 32'd64, + parameter int unsigned RoBDepth = 32'd64, /// Data type of response to be reordered parameter type ax_len_t = logic, parameter type rsp_chan_t = logic, parameter type rsp_data_t = logic, parameter type rsp_meta_t = logic, - parameter type rob_idx_t = logic[$clog2(ReorderBufferSize)-1:0], + parameter type rob_idx_t = logic[$clog2(RoBDepth)-1:0], parameter type dest_t = logic, parameter type sram_cfg_t = logic, // Dependent parameters, DO NOT OVERRIDE! - localparam type rob_flag_t = logic[ReorderBufferSize-1:0] + localparam type rob_flag_t = logic[RoBDepth-1:0] ) ( input logic clk_i, input logic rst_ni, @@ -55,9 +55,9 @@ module floo_simple_rob #( rob_idx_t read_pointer_q, read_pointer_d; rob_idx_t write_pointer_q, write_pointer_d; - logic [$clog2(ReorderBufferSize):0] status_cnt_q, status_cnt_d; - logic [$clog2(ReorderBufferSize):0] free_entries; - rsp_meta_t [ReorderBufferSize-1:0] rob_meta_q, rob_meta_d; + logic [$clog2(RoBDepth):0] status_cnt_q, status_cnt_d; + logic [$clog2(RoBDepth):0] free_entries; + rsp_meta_t [RoBDepth-1:0] rob_meta_q, rob_meta_d; rsp_meta_t rob_meta; rob_idx_t rsp_burst_cnt_q, rsp_burst_cnt_d; rob_flag_t rob_valid_q, rob_valid_d; @@ -80,10 +80,10 @@ module floo_simple_rob #( if (!OnlyMetaData) begin : gen_rob_sram tc_sram_impl #( - .NumWords (ReorderBufferSize), - .DataWidth ($bits(rsp_data_t)), - .NumPorts ( 1 ), - .impl_in_t ( sram_cfg_t ) + .NumWords ( RoBDepth ), + .DataWidth ( $bits(rsp_data_t) ), + .NumPorts ( 1 ), + .impl_in_t ( sram_cfg_t ) ) i_reorder_buffer ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -101,7 +101,7 @@ module floo_simple_rob #( end - assign free_entries = ReorderBufferSize - status_cnt_q; + assign free_entries = RoBDepth - status_cnt_q; assign ax_len = (OnlyMetaData)? 1 : ax_len_i + 1'b1; always_comb begin @@ -132,8 +132,8 @@ module floo_simple_rob #( if (ax_ready_i) begin ax_ready_o = 1'b1; // Increment write and status counter - if (write_pointer_q + ax_len >= ReorderBufferSize) begin - write_pointer_d = write_pointer_q + ax_len - ReorderBufferSize; + if (write_pointer_q + ax_len >= RoBDepth) begin + write_pointer_d = write_pointer_q + ax_len - RoBDepth; end else begin write_pointer_d = write_pointer_q + ax_len; end @@ -172,8 +172,8 @@ module floo_simple_rob #( rsp_out_valid_d = 1'b1; if (rsp_valid_o && rsp_ready_i) begin rob_valid_d[read_pointer_q] = 1'b0; - if (read_pointer_q + 1'b1 >= ReorderBufferSize) begin - read_pointer_d = read_pointer_q + 1'b1 - ReorderBufferSize; + if (read_pointer_q + 1'b1 >= RoBDepth) begin + read_pointer_d = read_pointer_q + 1'b1 - RoBDepth; end else begin read_pointer_d = read_pointer_q + 1'b1; end diff --git a/hw/floo_vc_axi_pkg.sv b/hw/floo_vc_axi_pkg.sv deleted file mode 100644 index cf960b1e..00000000 --- a/hw/floo_vc_axi_pkg.sv +++ /dev/null @@ -1,184 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// This file is auto-generated. Do not edit! Edit the template file instead - -`include "axi/typedef.svh" - -package floo_vc_axi_pkg; - - import floo_pkg::*; - - //////////////////////// - // AXI Parameters // - //////////////////////// - - typedef enum logic [2:0] { - AxiAw = 3'd0, - AxiW = 3'd1, - AxiAr = 3'd2, - AxiB = 3'd3, - AxiR = 3'd4, - NumAxiChannels = 3'd5 - } axi_ch_e; - - - localparam int unsigned AxiInAddrWidth = 32; - localparam int unsigned AxiInDataWidth = 64; - localparam int unsigned AxiInIdWidth = 3; - localparam int unsigned AxiInUserWidth = 1; - - - localparam int unsigned AxiOutAddrWidth = 32; - localparam int unsigned AxiOutDataWidth = 64; - localparam int unsigned AxiOutIdWidth = 3; - localparam int unsigned AxiOutUserWidth = 1; - - - typedef logic [31:0] axi_in_addr_t; - typedef logic [63:0] axi_in_data_t; - typedef logic [7:0] axi_in_strb_t; - typedef logic [2:0] axi_in_id_t; - typedef logic [0:0] axi_in_user_t; - `AXI_TYPEDEF_ALL_CT(axi_in, axi_in_req_t, axi_in_rsp_t, axi_in_addr_t, axi_in_id_t, axi_in_data_t, - axi_in_strb_t, axi_in_user_t) - - - typedef logic [31:0] axi_out_addr_t; - typedef logic [63:0] axi_out_data_t; - typedef logic [7:0] axi_out_strb_t; - typedef logic [2:0] axi_out_id_t; - typedef logic [0:0] axi_out_user_t; - `AXI_TYPEDEF_ALL_CT(axi_out, axi_out_req_t, axi_out_rsp_t, axi_out_addr_t, axi_out_id_t, - axi_out_data_t, axi_out_strb_t, axi_out_user_t) - - - - ///////////////////////// - // Header Typedefs // - ///////////////////////// - - localparam route_algo_e RouteAlgo = XYRouting; - localparam bit UseIdTable = 1'b0; - localparam int unsigned NumXBits = 3; - localparam int unsigned NumYBits = 3; - localparam int unsigned XYAddrOffsetX = 16; - localparam int unsigned XYAddrOffsetY = 19; - localparam int unsigned IdAddrOffset = 0; - - - typedef logic [0:0] rob_idx_t; - typedef logic [1:0] port_id_t; - typedef logic [2:0] x_bits_t; - typedef logic [2:0] y_bits_t; - typedef struct packed { - x_bits_t x; - y_bits_t y; - port_id_t port_id; - } id_t; - - typedef logic route_t; - typedef id_t dst_t; - typedef logic [2:0] vc_id_t; - - - typedef struct packed { - logic rob_req; - rob_idx_t rob_idx; - dst_t dst_id; - id_t src_id; - logic last; - logic atop; - axi_ch_e axi_ch; - vc_id_t vc_id; - route_direction_e lookahead; - } hdr_t; - - - - //////////////////////// - // Flits Typedefs // - //////////////////////// - - typedef struct packed { - hdr_t hdr; - axi_in_aw_chan_t aw; - logic [2:0] rsvd; - } floo_axi_aw_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_w_chan_t w; - } floo_axi_w_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_b_chan_t b; - logic [64:0] rsvd; - } floo_axi_b_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_ar_chan_t ar; - logic [8:0] rsvd; - } floo_axi_ar_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_in_r_chan_t r; - } floo_axi_r_flit_t; - - typedef logic [73:0] floo_req_payload_t; - typedef struct packed { - hdr_t hdr; - floo_req_payload_t payload; - } floo_req_generic_flit_t; - - typedef logic [70:0] floo_rsp_payload_t; - typedef struct packed { - hdr_t hdr; - floo_rsp_payload_t payload; - } floo_rsp_generic_flit_t; - - - - ////////////////////////// - // Channel Typedefs // - ////////////////////////// - - typedef union packed { - floo_axi_aw_flit_t axi_aw; - floo_axi_w_flit_t axi_w; - floo_axi_ar_flit_t axi_ar; - floo_req_generic_flit_t generic; - } floo_req_chan_t; - - typedef union packed { - floo_axi_b_flit_t axi_b; - floo_axi_r_flit_t axi_r; - floo_rsp_generic_flit_t generic; - } floo_rsp_chan_t; - - - - /////////////////////// - // Link Typedefs // - /////////////////////// - - typedef struct packed { - logic valid; - logic credit_v; - vc_id_t credit_id; - floo_req_chan_t req; - } floo_vc_req_t; - - typedef struct packed { - logic valid; - logic credit_v; - vc_id_t credit_id; - floo_rsp_chan_t rsp; - } floo_vc_rsp_t; - - -endpackage diff --git a/hw/floo_vc_narrow_wide_pkg.sv b/hw/floo_vc_narrow_wide_pkg.sv deleted file mode 100644 index 56233d68..00000000 --- a/hw/floo_vc_narrow_wide_pkg.sv +++ /dev/null @@ -1,273 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// This file is auto-generated. Do not edit! Edit the template file instead - -`include "axi/typedef.svh" - -package floo_vc_narrow_wide_pkg; - - import floo_pkg::*; - - //////////////////////// - // AXI Parameters // - //////////////////////// - - typedef enum logic [3:0] { - NarrowAw = 4'd0, - NarrowW = 4'd1, - NarrowAr = 4'd2, - WideAr = 4'd3, - NarrowB = 4'd4, - NarrowR = 4'd5, - WideB = 4'd6, - WideAw = 4'd7, - WideW = 4'd8, - WideR = 4'd9, - NumAxiChannels = 4'd10 - } axi_ch_e; - - - localparam int unsigned AxiNarrowInAddrWidth = 48; - localparam int unsigned AxiNarrowInDataWidth = 64; - localparam int unsigned AxiNarrowInIdWidth = 4; - localparam int unsigned AxiNarrowInUserWidth = 1; - - - localparam int unsigned AxiNarrowOutAddrWidth = 48; - localparam int unsigned AxiNarrowOutDataWidth = 64; - localparam int unsigned AxiNarrowOutIdWidth = 2; - localparam int unsigned AxiNarrowOutUserWidth = 1; - - - localparam int unsigned AxiWideInAddrWidth = 48; - localparam int unsigned AxiWideInDataWidth = 512; - localparam int unsigned AxiWideInIdWidth = 3; - localparam int unsigned AxiWideInUserWidth = 1; - - - localparam int unsigned AxiWideOutAddrWidth = 48; - localparam int unsigned AxiWideOutDataWidth = 512; - localparam int unsigned AxiWideOutIdWidth = 1; - localparam int unsigned AxiWideOutUserWidth = 1; - - - typedef logic [47:0] axi_narrow_in_addr_t; - typedef logic [63:0] axi_narrow_in_data_t; - typedef logic [7:0] axi_narrow_in_strb_t; - typedef logic [3:0] axi_narrow_in_id_t; - typedef logic [0:0] axi_narrow_in_user_t; - `AXI_TYPEDEF_ALL_CT(axi_narrow_in, axi_narrow_in_req_t, axi_narrow_in_rsp_t, axi_narrow_in_addr_t, - axi_narrow_in_id_t, axi_narrow_in_data_t, axi_narrow_in_strb_t, - axi_narrow_in_user_t) - - - typedef logic [47:0] axi_narrow_out_addr_t; - typedef logic [63:0] axi_narrow_out_data_t; - typedef logic [7:0] axi_narrow_out_strb_t; - typedef logic [1:0] axi_narrow_out_id_t; - typedef logic [0:0] axi_narrow_out_user_t; - `AXI_TYPEDEF_ALL_CT(axi_narrow_out, axi_narrow_out_req_t, axi_narrow_out_rsp_t, - axi_narrow_out_addr_t, axi_narrow_out_id_t, axi_narrow_out_data_t, - axi_narrow_out_strb_t, axi_narrow_out_user_t) - - - typedef logic [47:0] axi_wide_in_addr_t; - typedef logic [511:0] axi_wide_in_data_t; - typedef logic [63:0] axi_wide_in_strb_t; - typedef logic [2:0] axi_wide_in_id_t; - typedef logic [0:0] axi_wide_in_user_t; - `AXI_TYPEDEF_ALL_CT(axi_wide_in, axi_wide_in_req_t, axi_wide_in_rsp_t, axi_wide_in_addr_t, - axi_wide_in_id_t, axi_wide_in_data_t, axi_wide_in_strb_t, axi_wide_in_user_t) - - - typedef logic [47:0] axi_wide_out_addr_t; - typedef logic [511:0] axi_wide_out_data_t; - typedef logic [63:0] axi_wide_out_strb_t; - typedef logic [0:0] axi_wide_out_id_t; - typedef logic [0:0] axi_wide_out_user_t; - `AXI_TYPEDEF_ALL_CT(axi_wide_out, axi_wide_out_req_t, axi_wide_out_rsp_t, axi_wide_out_addr_t, - axi_wide_out_id_t, axi_wide_out_data_t, axi_wide_out_strb_t, - axi_wide_out_user_t) - - - - ///////////////////////// - // Header Typedefs // - ///////////////////////// - - localparam route_algo_e RouteAlgo = XYRouting; - localparam bit UseIdTable = 1'b0; - localparam int unsigned NumXBits = 3; - localparam int unsigned NumYBits = 3; - localparam int unsigned XYAddrOffsetX = 16; - localparam int unsigned XYAddrOffsetY = 19; - localparam int unsigned IdAddrOffset = 0; - - - typedef logic [0:0] rob_idx_t; - typedef logic [1:0] port_id_t; - typedef logic [2:0] x_bits_t; - typedef logic [2:0] y_bits_t; - typedef struct packed { - x_bits_t x; - y_bits_t y; - port_id_t port_id; - } id_t; - - typedef logic route_t; - typedef id_t dst_t; - typedef logic [2:0] vc_id_t; - - - typedef struct packed { - logic rob_req; - rob_idx_t rob_idx; - dst_t dst_id; - id_t src_id; - logic last; - logic atop; - axi_ch_e axi_ch; - vc_id_t vc_id; - route_direction_e lookahead; - } hdr_t; - - - - //////////////////////// - // Flits Typedefs // - //////////////////////// - - typedef struct packed { - hdr_t hdr; - axi_narrow_in_aw_chan_t aw; - } floo_narrow_aw_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_narrow_in_w_chan_t w; - logic [13:0] rsvd; - } floo_narrow_w_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_narrow_in_b_chan_t b; - logic [64:0] rsvd; - } floo_narrow_b_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_narrow_in_ar_chan_t ar; - logic [5:0] rsvd; - } floo_narrow_ar_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_narrow_in_r_chan_t r; - } floo_narrow_r_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_wide_in_aw_chan_t aw; - logic [490:0] rsvd; - } floo_wide_aw_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_wide_in_w_chan_t w; - } floo_wide_w_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_wide_in_b_chan_t b; - logic [65:0] rsvd; - } floo_wide_b_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_wide_in_ar_chan_t ar; - logic [6:0] rsvd; - } floo_wide_ar_flit_t; - - typedef struct packed { - hdr_t hdr; - axi_wide_in_r_chan_t r; - logic [58:0] rsvd; - } floo_wide_r_flit_t; - - typedef logic [87:0] floo_req_payload_t; - typedef struct packed { - hdr_t hdr; - floo_req_payload_t payload; - } floo_req_generic_flit_t; - - typedef logic [71:0] floo_rsp_payload_t; - typedef struct packed { - hdr_t hdr; - floo_rsp_payload_t payload; - } floo_rsp_generic_flit_t; - - typedef logic [577:0] floo_wide_payload_t; - typedef struct packed { - hdr_t hdr; - floo_wide_payload_t payload; - } floo_wide_generic_flit_t; - - - - ////////////////////////// - // Channel Typedefs // - ////////////////////////// - - typedef union packed { - floo_narrow_aw_flit_t narrow_aw; - floo_narrow_w_flit_t narrow_w; - floo_narrow_ar_flit_t narrow_ar; - floo_wide_ar_flit_t wide_ar; - floo_req_generic_flit_t generic; - } floo_req_chan_t; - - typedef union packed { - floo_narrow_b_flit_t narrow_b; - floo_narrow_r_flit_t narrow_r; - floo_wide_b_flit_t wide_b; - floo_rsp_generic_flit_t generic; - } floo_rsp_chan_t; - - typedef union packed { - floo_wide_aw_flit_t wide_aw; - floo_wide_w_flit_t wide_w; - floo_wide_r_flit_t wide_r; - floo_wide_generic_flit_t generic; - } floo_wide_chan_t; - - - - /////////////////////// - // Link Typedefs // - /////////////////////// - - typedef struct packed { - logic valid; - logic credit_v; - vc_id_t credit_id; - floo_req_chan_t req; - } floo_vc_req_t; - - typedef struct packed { - logic valid; - logic credit_v; - vc_id_t credit_id; - floo_rsp_chan_t rsp; - } floo_vc_rsp_t; - - typedef struct packed { - logic valid; - logic credit_v; - vc_id_t credit_id; - floo_wide_chan_t wide; - } floo_vc_wide_t; - - -endpackage diff --git a/hw/include/floo_noc/typedef.svh b/hw/include/floo_noc/typedef.svh index 7c06e548..769f11fb 100644 --- a/hw/include/floo_noc/typedef.svh +++ b/hw/include/floo_noc/typedef.svh @@ -1,36 +1,405 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Michael Rogenmoser +// Authors: +// - Tim Fischer +// - Michael Rogenmoser + +// Macros to define the FlooNoC data types `ifndef FLOO_NOC_TYPEDEF_SVH_ `define FLOO_NOC_TYPEDEF_SVH_ -`define FLOO_NOC_TYPEDEF_FLIT_T(flit_t, FlitWidth) \ - typedef struct packed { \ - logic [FlitWidth-1:0] data; \ - logic last; \ - } flit_t; - -`define FLOO_NOC_TYPEDEF_ID_FLIT_T(flit_t, IdWidth, FlitWidth) \ - typedef struct packed { \ - logic [FlitWidth-1:0] data; \ - logic [IdWidth-1:0] dst_id; \ - logic last; \ - } flit_t; - -`define FLOO_NOC_TYPEDEF_XY_ID_T(xy_id_t, NumX, NumY) \ - typedef struct packed { \ - logic [$clog2(NumX)-1:0] x; \ - logic [$clog2(NumY)-1:0] y; \ - } xy_id_t; - -`define FLOO_NOC_TYPEDEF_XY_FLIT_T(flit_t, xy_id_t, FlitWidth) \ - typedef struct packed { \ - logic [FlitWidth-1:0] data; \ - xy_id_t dst_id; \ - logic last; \ - } flit_t; +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Node ID for XY coordinates +// +// Arguments: +// - name: Name of the ID struct type +// - x_bits_t: Type of the X coordinate +// - y_bits_t: Type of the Y coordinate +// - port_id_t: Type of the port ID +// +// Usage Example: +// typedef logic [$clog2(NumX)-1:0] x_bits_t; +// typedef logic [$clog2(NumY)-1:0] y_bits_t; +// typedef logic port_id_t; +// `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, port_id_t) +`define FLOO_TYPEDEF_XY_NODE_ID_T(name, x_bits_t, y_bits_t, p_bits_t) \ + typedef struct packed { \ + x_bits_t x; \ + y_bits_t y; \ + p_bits_t port_id; \ + } name; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Header definition +// +// Arguments: +// - hdr_t: Name of the header struct type +// - dst_t: Type of the destination ID +// - src_t: Type of the source ID (Usually `dst_t`) +// - ch_t: Identifier type for the payload +// - rob_idx_t: Type of the RoB index +// +// Usage Example: +// `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, ...) +// `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, logic) +// +// For `SourceRouting`: +// `FLOO_TYPEDEF_HDR_T(hdr_t, route_t, id_t, floo_pkg::axi_ch_e, logic) +`define FLOO_TYPEDEF_HDR_T(hdr_t, dst_t, src_t, ch_t, rob_idx_t) \ + typedef struct packed { \ + logic rob_req; \ + rob_idx_t rob_idx; \ + dst_t dst_id; \ + src_t src_id; \ + logic last; \ + logic atop; \ + ch_t axi_ch; \ + } hdr_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Header definition for virtual channel and lookahead routing +// +// Arguments: +// - hdr_t: Name of the header struct type +// - dst_t: Type of the destination ID +// - src_t: Type of the source ID (Usually `dst_t`) +// - ch_t: Identifier type for the payload +// - rob_idx_t: Type of the RoB index +// - vc_id_t: Type of the virtual channel ID +// +// Usage Example: +// `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, ...) +// `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, logic) +// +// For `SourceRouting`: +// `FLOO_TYPEDEF_HDR_T(hdr_t, route_t, id_t, floo_pkg::axi_ch_e, logic) +`define FLOO_TYPEDEF_VC_HDR_T(hdr_t, dst_t, src_t, ch_t, rob_idx_t, vc_id_t) \ + typedef struct packed { \ + logic rob_req; \ + rob_idx_t rob_idx; \ + dst_t dst_id; \ + src_t src_id; \ + logic last; \ + logic atop; \ + ch_t axi_ch; \ + vc_id_t vc_id; \ + floo_pkg::route_direction_e lookahead; \ + } hdr_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Flit definition of a specific AXI Channel. +// +// Arguments: +// - name: Name of the flit type +// - hdr_t: Type of the header +// - payload_t: Type of the payload +// - rsvd_bits: Number of reserved bits that are not used by the payload +// +// Usage Example: +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_FLIT_T(my_payload, hdr_t, my_payload_t, 13) +`define FLOO_TYPEDEF_FLIT_T(name, hdr_t, payload_t, rsvd_bits) \ + typedef struct packed { \ + hdr_t hdr; \ + payload_t payload; \ + logic [rsvd_bits-1:0] rsvd; \ + } floo_``name``_flit_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Flit definition of a generic flit. +// +// Arguments: +// - name: Name of the flit type +// - hdr_t: Type of the header +// - payload_t: Type of the payload +// +// Usage Example: +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_GENERIC_FLIT_T(req, hdr_t, logic [63:0]) +`define FLOO_TYPEDEF_GENERIC_FLIT_T(name, hdr_t, payload_t) \ + typedef payload_t floo_``name``_payload_t ; \ + typedef struct packed { \ + hdr_t hdr; \ + floo_``name``_payload_t payload; \ + } floo_``name``_generic_flit_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines AXI channel types based on a `floo_pkg::AxiCfg`. +// Both incoming and outgoing channel are defined with the `name_in` and `name_out` suffix +// +// Arguments: +// - name: Prefix for the AXI channel types +// - cfg: AxiCfg struct type defining AddrWidth, DataWidth, User Width and +// IdWidth for in and out direction (see `floo_pkg::AxiCfg`) +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfg = '{ +// AddrWidth: 32, +// DataWidth: 64, +// UserWidth: 1, +// InIdWidth: 4, +// OutIdWidth: 2 +// }; +// `FLOO_TYPEDEF_AXI_FROM_CFG(axi, AxiCfg) +`define FLOO_TYPEDEF_AXI_FROM_CFG(name, cfg) \ + typedef logic [cfg.AddrWidth-1:0] ``name``_addr_t; \ + typedef logic [cfg.InIdWidth-1:0] ``name``_in_id_t; \ + typedef logic [cfg.OutIdWidth-1:0] ``name``_out_id_t; \ + typedef logic [cfg.UserWidth-1:0] ``name``_user_t; \ + typedef logic [cfg.DataWidth-1:0] ``name``_data_t; \ + typedef logic [cfg.DataWidth/8-1:0] ``name``_strb_t; \ + `AXI_TYPEDEF_ALL_CT(``name``_in, ``name``_in_req_t, ``name``_in_rsp_t, ``name``_addr_t, ``name``_in_id_t, ``name``_data_t, ``name``_strb_t, ``name``_user_t) \ + `AXI_TYPEDEF_ALL_CT(``name``_out, ``name``_out_req_t, ``name``_out_rsp_t, ``name``_addr_t, ``name``_out_id_t, ``name``_data_t, ``name``_strb_t, ``name``_user_t) + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the flit types and physical channel for configuration +// with a single AXI interface and two physical channels `req` and `rsp`. +// It also defines `unions` named as `chan_t`, which can be used +// to represent multiple different flit types in a single variable. +// +// Arguments: +// - name: Name of flit types +// - req: Name of the `req` flit type +// - rsp: Name of the `rsp` flit type +// - axi_name: Prefix for the AXI channel types +// - cfg: AxiCfg struct type defining AddrWidth, DataWidth, User Width and +// IdWidth for in and out direction (see `floo_pkg::AxiCfg`) +// - hdr_t: Type of the header +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfg = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi, AxiCfg) +// `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, my_axi, AxiCfg, hdr_t) +`define FLOO_TYPEDEF_AXI_CHAN_ALL(name, req, rsp, axi_name, cfg, hdr_t) \ + `FLOO_TYPEDEF_FLIT_T(``name``_aw, hdr_t, ``axi_name``_aw_chan_t, floo_pkg::get_axi_rsvd_bits(cfg, floo_pkg::AxiAw)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_w, hdr_t, ``axi_name``_w_chan_t, floo_pkg::get_axi_rsvd_bits(cfg, floo_pkg::AxiW)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_ar, hdr_t, ``axi_name``_ar_chan_t, floo_pkg::get_axi_rsvd_bits(cfg, floo_pkg::AxiAr)) \ + `FLOO_TYPEDEF_GENERIC_FLIT_T(req, hdr_t, logic [floo_pkg::get_max_axi_payload_bits(cfg, floo_pkg::FlooReq)-1:0]) \ + \ + `FLOO_TYPEDEF_FLIT_T(``name``_b, hdr_t, ``axi_name``_b_chan_t, floo_pkg::get_axi_rsvd_bits(cfg, floo_pkg::AxiB)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_r, hdr_t, ``axi_name``_r_chan_t, floo_pkg::get_axi_rsvd_bits(cfg, floo_pkg::AxiR)) \ + `FLOO_TYPEDEF_GENERIC_FLIT_T(rsp, hdr_t, logic [floo_pkg::get_max_axi_payload_bits(cfg, floo_pkg::FlooRsp)-1:0]) \ + \ + typedef union packed { \ + floo_``name``_aw_flit_t axi_aw; \ + floo_``name``_w_flit_t axi_w; \ + floo_``name``_ar_flit_t axi_ar; \ + floo_``req``_generic_flit_t generic; \ + } floo_``req``_chan_t; \ + \ + typedef union packed { \ + floo_``name``_b_flit_t axi_b; \ + floo_``name``_r_flit_t axi_r; \ + floo_``rsp``_generic_flit_t generic; \ + } floo_``rsp``_chan_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the flit types and physical channel for configuration +// with a narrow and a wide AXI interface and three physical channels `req`, `rsp` and `wide`. +// It also defines `unions` named as `chan_t`, which can be used +// to represent multiple different flit types in a single variable. +// +// Arguments: +// - name: Name of flit types +// - req: Name of the `req` flit type +// - rsp: Name of the `rsp` flit type +// - wide: Name of the `wide` flit type +// - axi_narrow_name: Prefix for the AXI narrow channel types +// - axi_wide_name: Prefix for the AXI wide channel types +// - cfg_n: AxiCfg struct type for the narrow AXI interface, +// defining AddrWidth, DataWidth, User Width and +// IdWidth for in and out direction (see `floo_pkg::AxiCfg`) +// - cfg_w: AxiCfg struct type for the wide AXI interface, +// defining AddrWidth, DataWidth, User Width and +// IdWidth for in and out direction (see `floo_pkg::AxiCfg`) +// - hdr_t: Type of the header +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfgN = '{...}; +// localparam floo_pkg::axi_cfg_t AxiCfgW = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi_narrow, AxiCfgN) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi_wide, AxiCfgW) +// `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, my_axi_narrow_in, my_axi_wide_in, AxiCfgN, AxiCfgW, hdr_t) +`define FLOO_TYPEDEF_NW_CHAN_ALL(name, req, rsp, wide, axi_narrow_name, axi_wide_name, cfg_n, cfg_w, hdr_t) \ + `AXI_TYPEDEF_ALL(__``name``_narrow, logic [cfg_n.AddrWidth-1:0], logic [cfg_n.InIdWidth-1:0], logic [cfg_n.DataWidth-1:0], logic [cfg_n.DataWidth/8-1:0], logic [cfg_n.UserWidth-1:0]) \ + `AXI_TYPEDEF_ALL(__``name``_wide, logic [cfg_w.AddrWidth-1:0], logic [cfg_w.InIdWidth-1:0], logic [cfg_w.DataWidth-1:0], logic [cfg_w.DataWidth/8-1:0], logic [cfg_w.UserWidth-1:0]) \ + `FLOO_TYPEDEF_FLIT_T(``name``_narrow_aw, hdr_t, ``axi_narrow_name``_aw_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::NarrowAw)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_narrow_w, hdr_t, ``axi_narrow_name``_w_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::NarrowW)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_narrow_ar, hdr_t, ``axi_narrow_name``_ar_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::NarrowAr)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_wide_ar, hdr_t, ``axi_wide_name``_ar_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::WideAr)) \ + `FLOO_TYPEDEF_GENERIC_FLIT_T(req, hdr_t, logic [floo_pkg::get_max_nw_payload_bits(cfg_n, cfg_w, floo_pkg::FlooReq)-1:0]) \ + \ + `FLOO_TYPEDEF_FLIT_T(``name``_narrow_b, hdr_t, ``axi_narrow_name``_b_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::NarrowB)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_narrow_r, hdr_t, ``axi_narrow_name``_r_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::NarrowR)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_wide_b, hdr_t, ``axi_wide_name``_b_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::WideB)) \ + `FLOO_TYPEDEF_GENERIC_FLIT_T(rsp, hdr_t, logic [floo_pkg::get_max_nw_payload_bits(cfg_n, cfg_w, floo_pkg::FlooRsp)-1:0]) \ + \ + `FLOO_TYPEDEF_FLIT_T(``name``_wide_aw, hdr_t, ``axi_wide_name``_aw_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::WideAw)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_wide_w, hdr_t, ``axi_wide_name``_w_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::WideW)) \ + `FLOO_TYPEDEF_FLIT_T(``name``_wide_r, hdr_t, ``axi_wide_name``_r_chan_t, floo_pkg::get_nw_rsvd_bits(cfg_n, cfg_w, floo_pkg::WideR)) \ + `FLOO_TYPEDEF_GENERIC_FLIT_T(wide, hdr_t, logic [floo_pkg::get_max_nw_payload_bits(cfg_n, cfg_w, floo_pkg::FlooWide)-1:0]) \ + \ + typedef union packed { \ + floo_``name``_narrow_aw_flit_t narrow_aw; \ + floo_``name``_narrow_w_flit_t narrow_w; \ + floo_``name``_narrow_ar_flit_t narrow_ar; \ + floo_``name``_wide_ar_flit_t wide_ar; \ + floo_``req``_generic_flit_t generic; \ + } floo_``req``_chan_t; \ + \ + typedef union packed { \ + floo_``name``_narrow_b_flit_t narrow_b; \ + floo_``name``_narrow_r_flit_t narrow_r; \ + floo_``name``_wide_b_flit_t wide_b; \ + floo_``rsp``_generic_flit_t generic; \ + } floo_``rsp``_chan_t; \ + \ + typedef union packed { \ + floo_``name``_wide_aw_flit_t wide_aw; \ + floo_``name``_wide_w_flit_t wide_w; \ + floo_``name``_wide_r_flit_t wide_r; \ + floo_``wide``_generic_flit_t generic; \ + } floo_``wide``_chan_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the link types with a ready-valid handshaking interface +// +// Arguments: +// - name: Name of the link type +// - chan_name: Name of the channel type to transport +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfg = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi, AxiCfg) +// `FLOO_TYPEDEF_AXI_CHAN_ALL(my_axi, req, rsp, my_axi_in, AxiCfg, hdr_t) +// FLOO_TYPEDEF_LINK_T(req, my_axi) +`define FLOO_TYPEDEF_LINK_T(name, chan_name) \ + typedef struct packed { \ + logic valid; \ + logic ready; \ + floo_``chan_name``_chan_t ``chan_name``; \ + } floo_``name``_t; + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the link types with credit-based flow control interface +// for use with virtual channels +// +// Arguments: +// - name: Name of the link type +// - chan_name: Name of the channel type to transport +// - vc_id_t: Type of the virtual channel ID +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfg = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi, AxiCfg) +// `FLOO_TYPEDEF_AXI_CHAN_ALL(my_axi, req, rsp, my_axi_in, AxiCfg, hdr_t) +// FLOO_TYPEDEF_LINK_T(vc_req, my_axi) +`define FLOO_TYPEDEF_VC_LINK_T(name, chan_name, vc_id_t) \ + typedef struct packed { \ + logic valid; \ + logic credit_v; \ + vc_id_t credit_id; \ + floo_``chan_name``_chan_t ``chan_name``; \ + } floo_``name``_t; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the link types with ready-valid handshaking interface +// for a single AXI interface configuration +// +// Arguments: +// - req: Name of the `req` link type +// - rsp: Name of the `rsp` link type +// - req_chan: Name of the `req` channel type to transport +// - rsp_chan: Name of the `rsp` channel type to transport +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfg = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi, AxiCfg) +// `FLOO_TYPEDEF_AXI_CHAN_ALL(my_axi, my_req, my_rsp, my_axi_in, AxiCfg, hdr_t) +// `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, my_req, my_rsp) +`define FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req_chan, rsp_chan) \ + `FLOO_TYPEDEF_LINK_T(req, req_chan) \ + `FLOO_TYPEDEF_LINK_T(rsp, rsp_chan) \ + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the link types with ready-valid handshaking interface +// for a narrow-wide AXI interface configuration +// +// Arguments: +// - req: Name of the `req` link type +// - rsp: Name of the `rsp` link type +// - wide: Name of the `wide` link type +// - req_chan: Name of the `req` channel type to transport +// - rsp_chan: Name of the `rsp` channel type to transport +// - wide_chan: Name of the `wide` channel type to transport +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfgN = '{...}; +// localparam floo_pkg::axi_cfg_t AxiCfgW = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_narrow_axi, AxiCfgN) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_wide_axi, AxiCfgW) +// `FLOO_TYPEDEF_NW_CHAN_ALL(axi, my_req, my_rsp, my_wide, my_axi_narrow_in, my_axi_wide_in, AxiCfgN, AxiCfgW, hdr_t) +// `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, my_req, my_rsp, my_wide) +`define FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req_chan, rsp_chan, wide_chan) \ + `FLOO_TYPEDEF_LINK_T(req, req_chan) \ + `FLOO_TYPEDEF_LINK_T(rsp, rsp_chan) \ + `FLOO_TYPEDEF_LINK_T(wide, wide_chan) + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the link types with credit-based flow control interface +// for a single AXI interface configuration +// +// Arguments: +// - req: Name of the `req` link type +// - rsp: Name of the `rsp` link type +// - req_chan: Name of the `req` channel type to transport +// - rsp_chan: Name of the `rsp` channel type to transport +// - vc_id_t: Type of the virtual channel ID +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfg = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_axi, AxiCfg) +// `FLOO_TYPEDEF_AXI_CHAN_ALL(my_axi, my_req, my_rsp, my_axi_in, AxiCfg, hdr_t) +// `FLOO_TYPEDEF_VC_AXI_LINK_ALL(vc_req, vc_rsp, my_req, my_rsp) +`define FLOO_TYPEDEF_VC_AXI_LINK_ALL(req, rsp, req_chan, rsp_chan, vc_id_t) \ + `FLOO_TYPEDEF_VC_LINK_T(req, req_chan, vc_id_t) \ + `FLOO_TYPEDEF_VC_LINK_T(rsp, rsp_chan, vc_id_t) \ + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// Defines the all the link types with credit-based flow control interface +// for a narrow-wide AXI interface configuration +// +// Arguments: +// - req: Name of the `req` link type +// - rsp: Name of the `rsp` link type +// - wide: Name of the `wide` link type +// - req_chan: Name of the `req` channel type to transport +// - rsp_chan: Name of the `rsp` channel type to transport +// - wide_chan: Name of the `wide` channel type to transport +// - vc_id_t: Type of the virtual channel ID +// +// Usage Example: +// localparam floo_pkg::axi_cfg_t AxiCfgN = '{...}; +// localparam floo_pkg::axi_cfg_t AxiCfgW = '{...}; +// `FLOO_TYPEDEF_HDR_T(hdr_t, ...) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_narrow_axi, AxiCfgN) +// `FLOO_TYPEDEF_AXI_FROM_CFG(my_wide_axi, AxiCfgW) +// `FLOO_TYPEDEF_NW_CHAN_ALL(axi, my_req, my_rsp, my_wide, my_axi_narrow_in, my_axi_wide_in, AxiCfgN, AxiCfgW, hdr_t) +// `FLOO_TYPEDEF_NW_LINK_ALL(vc_req, vc_rsp, vc_wide, my_req, my_rsp, my_wide) +`define FLOO_TYPEDEF_VC_NW_LINK_ALL(req, rsp, wide, req_chan, rsp_chan, wide_chan, vc_id_t) \ + `FLOO_TYPEDEF_VC_LINK_T(req, req_chan, vc_id_t) \ + `FLOO_TYPEDEF_VC_LINK_T(rsp, rsp_chan, vc_id_t) \ + `FLOO_TYPEDEF_VC_LINK_T(wide, wide_chan, vc_id_t) `endif // FLOO_NOC_TYPEDEF_SVH_ diff --git a/hw/tb/tb_floo_axi_chimney.sv b/hw/tb/tb_floo_axi_chimney.sv index f7ca26eb..8047304a 100644 --- a/hw/tb/tb_floo_axi_chimney.sv +++ b/hw/tb/tb_floo_axi_chimney.sv @@ -10,9 +10,6 @@ module tb_floo_axi_chimney; - import floo_pkg::*; - import floo_axi_pkg::*; - localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; localparam time TestTime = 8ns; @@ -22,16 +19,18 @@ module tb_floo_axi_chimney; localparam int unsigned NumReads1 = 1000; localparam int unsigned NumWrites1 = 1000; - localparam bit AtopSupport = 1'b1; - localparam int unsigned NumTargets = 2; - localparam int unsigned ReorderBufferSize = 64; - localparam int unsigned MaxTxns = 32; - localparam int unsigned MaxTxnsPerId = 32; - logic clk, rst_n; + typedef logic [1:0] x_bits_t; + typedef logic [1:0] y_bits_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, logic) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi, floo_test_pkg::AxiCfg) + `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_in, floo_test_pkg::AxiCfg, hdr_t) + `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) + axi_in_req_t [NumTargets-1:0] node_man_req; axi_in_rsp_t [NumTargets-1:0] node_man_rsp; @@ -60,8 +59,8 @@ module tb_floo_axi_chimney; ); typedef struct packed { - logic [AxiInAddrWidth-1:0] start_addr; - logic [AxiInAddrWidth-1:0] end_addr; + logic [floo_test_pkg::AxiCfg.AddrWidth-1:0] start_addr; + logic [floo_test_pkg::AxiCfg.AddrWidth-1:0] end_addr; } node_addr_region_t; localparam int unsigned NumAddrRegions = 1; @@ -70,24 +69,19 @@ module tb_floo_axi_chimney; }; floo_axi_test_node #( - .AxiAddrWidth ( AxiInAddrWidth ), - .AxiDataWidth ( AxiInDataWidth ), - .AxiIdOutWidth ( AxiInIdWidth ), - .AxiIdInWidth ( AxiOutIdWidth ), - .AxiUserWidth ( AxiInUserWidth ), - .mst_req_t ( axi_in_req_t ), - .mst_rsp_t ( axi_in_rsp_t ), - .slv_req_t ( axi_out_req_t ), - .slv_rsp_t ( axi_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( AtopSupport ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NumReads0 ), - .NumWrites ( NumWrites0 ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .mst_req_t ( axi_in_req_t ), + .mst_rsp_t ( axi_in_rsp_t ), + .slv_req_t ( axi_out_req_t ), + .slv_rsp_t ( axi_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( floo_test_pkg::AtopSupport ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( NumReads0 ), + .NumWrites ( NumWrites0 ) ) i_test_node_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -99,15 +93,15 @@ module tb_floo_axi_chimney; ); axi_reorder_remap_compare #( - .AxiInIdWidth ( AxiInIdWidth ), - .AxiOutIdWidth ( AxiOutIdWidth ), - .aw_chan_t ( axi_in_aw_chan_t ), - .w_chan_t ( axi_in_w_chan_t ), - .b_chan_t ( axi_in_b_chan_t ), - .ar_chan_t ( axi_in_ar_chan_t ), - .r_chan_t ( axi_in_r_chan_t ), - .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_rsp_t ) + .AxiInIdWidth ( floo_test_pkg::AxiCfg.InIdWidth ), + .AxiOutIdWidth ( floo_test_pkg::AxiCfg.OutIdWidth ), + .aw_chan_t ( axi_in_aw_chan_t ), + .w_chan_t ( axi_in_w_chan_t ), + .b_chan_t ( axi_in_b_chan_t ), + .ar_chan_t ( axi_in_ar_chan_t ), + .r_chan_t ( axi_in_r_chan_t ), + .req_t ( axi_in_req_t ), + .rsp_t ( axi_in_rsp_t ) ) i_axi_chan_compare_0 ( .clk_i ( clk ), .mon_mst_req_i ( node_man_req[0] ), @@ -118,11 +112,19 @@ module tb_floo_axi_chimney; ); floo_axi_chimney #( - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( 4 ), - .MaxTxns ( MaxTxns ), - .MaxTxnsPerId ( MaxTxnsPerId ), - .ReorderBufferSize ( ReorderBufferSize ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .ChimneyCfg ( floo_test_pkg::ChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( floo_test_pkg::AtopSupport ), + .MaxAtomicTxns ( floo_test_pkg::MaxAtomicTxns ), + .hdr_t ( hdr_t ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .id_t ( id_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ) ) i_floo_axi_chimney_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -141,11 +143,19 @@ module tb_floo_axi_chimney; ); floo_axi_chimney #( - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( 4 ), - .MaxTxns ( MaxTxns ), - .MaxTxnsPerId ( MaxTxnsPerId ), - .ReorderBufferSize ( ReorderBufferSize ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .ChimneyCfg ( floo_test_pkg::ChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( floo_test_pkg::AtopSupport ), + .MaxAtomicTxns ( floo_test_pkg::MaxAtomicTxns ), + .hdr_t ( hdr_t ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .id_t ( id_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ) ) i_floo_axi_chimney_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -164,15 +174,15 @@ module tb_floo_axi_chimney; ); axi_reorder_remap_compare #( - .AxiInIdWidth ( AxiInIdWidth ), - .AxiOutIdWidth ( AxiOutIdWidth ), - .aw_chan_t ( axi_in_aw_chan_t ), - .w_chan_t ( axi_in_w_chan_t ), - .b_chan_t ( axi_in_b_chan_t ), - .ar_chan_t ( axi_in_ar_chan_t ), - .r_chan_t ( axi_in_r_chan_t ), - .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_rsp_t ) + .AxiInIdWidth ( floo_test_pkg::AxiCfg.InIdWidth ), + .AxiOutIdWidth ( floo_test_pkg::AxiCfg.OutIdWidth ), + .aw_chan_t ( axi_in_aw_chan_t ), + .w_chan_t ( axi_in_w_chan_t ), + .b_chan_t ( axi_in_b_chan_t ), + .ar_chan_t ( axi_in_ar_chan_t ), + .r_chan_t ( axi_in_r_chan_t ), + .req_t ( axi_in_req_t ), + .rsp_t ( axi_in_rsp_t ) ) i_axi_chan_compare_1 ( .clk_i ( clk ), .mon_mst_req_i ( node_man_req[1] ), @@ -183,24 +193,19 @@ module tb_floo_axi_chimney; ); floo_axi_test_node #( - .AxiAddrWidth ( AxiInAddrWidth ), - .AxiDataWidth ( AxiInDataWidth ), - .AxiIdInWidth ( AxiOutIdWidth ), - .AxiIdOutWidth ( AxiInIdWidth ), - .AxiUserWidth ( AxiInUserWidth ), - .mst_req_t ( axi_in_req_t ), - .mst_rsp_t ( axi_in_rsp_t ), - .slv_req_t ( axi_out_req_t ), - .slv_rsp_t ( axi_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( AtopSupport ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NumReads1 ), - .NumWrites ( NumWrites1 ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .mst_req_t ( axi_in_req_t ), + .mst_rsp_t ( axi_in_rsp_t ), + .slv_req_t ( axi_out_req_t ), + .slv_rsp_t ( axi_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( floo_test_pkg::AtopSupport ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( NumReads1 ), + .NumWrites ( NumWrites1 ) ) i_test_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -212,9 +217,9 @@ module tb_floo_axi_chimney; ); axi_bw_monitor #( - .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_rsp_t ), - .AxiIdWidth ( AxiInIdWidth ) + .req_t ( axi_in_req_t ), + .rsp_t ( axi_in_rsp_t ), + .AxiIdWidth ( floo_test_pkg::AxiCfg.InIdWidth ) ) i_axi_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), diff --git a/hw/tb/tb_floo_dma_mesh.sv b/hw/tb/tb_floo_dma_mesh.sv index abe24098..19aa1f02 100644 --- a/hw/tb/tb_floo_dma_mesh.sv +++ b/hw/tb/tb_floo_dma_mesh.sv @@ -4,13 +4,12 @@ // // Author: Tim Fischer +`include "axi/typedef.svh" `include "floo_noc/typedef.svh" -`include "common_cells/assertions.svh" module tb_floo_dma_mesh; import floo_pkg::*; - import floo_narrow_wide_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -20,29 +19,22 @@ module tb_floo_dma_mesh; localparam int unsigned NumY = 4; localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY; + typedef logic[$clog2(NumX+2)-1:0] x_bits_t; + typedef logic[$clog2(NumY+2)-1:0] y_bits_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in, + floo_test_pkg::AxiCfgN, floo_test_pkg::AxiCfgW, hdr_t) + `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) + localparam int unsigned HBMLatency = 100; - localparam axi_narrow_in_addr_t HBMSize = 48'h10000; // 64KB - localparam axi_narrow_in_addr_t MemSize = HBMSize; - - if (RouteAlgo == XYRouting) begin : gen_asserts - `ASSERT_INIT(NotEnoughXBits, $clog2(NumX + 2) <= $bits(x_bits_t)) - `ASSERT_INIT(NotEnoughYBits, $clog2(NumY + 2) <= $bits(y_bits_t)) - `ASSERT_INIT(NotEnoughAddrOffset, $clog2(HBMSize) <= XYAddrOffsetX) - end else begin : gen_error - $fatal(1, "This testbench only supports XYRouting"); - end + localparam axi_narrow_addr_t HBMSize = 48'h10000; // 64KB + localparam axi_narrow_addr_t MemSize = HBMSize; - // Narrow Wide Chimney parameters - localparam bit CutAx = 1'b1; - localparam bit CutRsp = 1'b1; - localparam int unsigned NarrowMaxTxnsPerId = 4; - localparam int unsigned NarrowReorderBufferSize = 32'd256; - localparam int unsigned WideMaxTxnsPerId = 32; - localparam int unsigned WideReorderBufferSize = 32'd64; - localparam int unsigned NarrowMaxTxns = 32; - localparam int unsigned WideMaxTxns = 32; - localparam int unsigned ChannelFifoDepth = 2; - localparam int unsigned OutputFifoDepth = 2; + localparam int unsigned InFifoDepth = 2; + localparam int unsigned OutFifoDepth = 2; logic clk, rst_n; @@ -72,7 +64,7 @@ module tb_floo_dma_mesh; floo_req_t [NumX-1:0][NumY-1:0] narrow_chimney_man_req, narrow_chimney_sub_req; floo_rsp_t [NumX-1:0][NumY-1:0] narrow_chimney_man_rsp, narrow_chimney_sub_rsp; - floo_wide_t [NumX-1:0][NumY-1:0] wide_chimney_man, wide_chimney_sub; + floo_wide_t [NumX-1:0][NumY-1:0] wide_chimney_man, wide_chimney_sub; floo_req_t [NumX:0][NumY-1:0] req_hor_pos; floo_req_t [NumX:0][NumY-1:0] req_hor_neg; @@ -82,10 +74,10 @@ module tb_floo_dma_mesh; floo_rsp_t [NumX:0][NumY-1:0] rsp_hor_neg; floo_rsp_t [NumY:0][NumX-1:0] rsp_ver_pos; floo_rsp_t [NumY:0][NumX-1:0] rsp_ver_neg; - floo_wide_t [NumX:0][NumY-1:0] wide_hor_pos; - floo_wide_t [NumX:0][NumY-1:0] wide_hor_neg; - floo_wide_t [NumY:0][NumX-1:0] wide_ver_pos; - floo_wide_t [NumY:0][NumX-1:0] wide_ver_neg; + floo_wide_t [NumX:0][NumY-1:0] wide_hor_pos; + floo_wide_t [NumX:0][NumY-1:0] wide_hor_neg; + floo_wide_t [NumY:0][NumX-1:0] wide_ver_pos; + floo_wide_t [NumY:0][NumX-1:0] wide_ver_neg; logic [NumX-1:0][NumY-1:0][1:0] end_of_sim; @@ -103,21 +95,21 @@ module tb_floo_dma_mesh; //////////////////////////////// floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( AxiWideOutAddrWidth ), - .DataWidth ( AxiWideOutDataWidth ), - .UserWidth ( AxiWideOutUserWidth ), - .IdWidth ( AxiWideOutIdWidth ), - .axi_req_t ( axi_wide_out_req_t ), - .axi_rsp_t ( axi_wide_out_rsp_t ), - .aw_chan_t ( axi_wide_out_aw_chan_t ), - .w_chan_t ( axi_wide_out_w_chan_t ), - .b_chan_t ( axi_wide_out_b_chan_t ), - .ar_chan_t ( axi_wide_out_ar_chan_t ), - .r_chan_t ( axi_wide_out_r_chan_t ) + .TA ( ApplTime ), + .TT ( TestTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .AddrWidth ( floo_test_pkg::AxiCfgW.AddrWidth ), + .DataWidth ( floo_test_pkg::AxiCfgW.DataWidth ), + .UserWidth ( floo_test_pkg::AxiCfgW.UserWidth ), + .IdWidth ( floo_test_pkg::AxiCfgW.OutIdWidth ), + .axi_req_t ( axi_wide_out_req_t ), + .axi_rsp_t ( axi_wide_out_rsp_t ), + .aw_chan_t ( axi_wide_out_aw_chan_t ), + .w_chan_t ( axi_wide_out_w_chan_t ), + .b_chan_t ( axi_wide_out_b_chan_t ), + .ar_chan_t ( axi_wide_out_ar_chan_t ), + .r_chan_t ( axi_wide_out_r_chan_t ) ) i_floo_wide_hbm_model [West:North][NumMax-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -126,21 +118,21 @@ module tb_floo_dma_mesh; ); floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( AxiNarrowOutAddrWidth ), - .DataWidth ( AxiNarrowOutDataWidth ), - .UserWidth ( AxiNarrowOutUserWidth ), - .IdWidth ( AxiNarrowOutIdWidth ), - .axi_req_t ( axi_narrow_out_req_t ), - .axi_rsp_t ( axi_narrow_out_rsp_t ), - .aw_chan_t ( axi_narrow_out_aw_chan_t ), - .w_chan_t ( axi_narrow_out_w_chan_t ), - .b_chan_t ( axi_narrow_out_b_chan_t ), - .ar_chan_t ( axi_narrow_out_ar_chan_t ), - .r_chan_t ( axi_narrow_out_r_chan_t ) + .TA ( ApplTime ), + .TT ( TestTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .AddrWidth ( floo_test_pkg::AxiCfgN.AddrWidth ), + .DataWidth ( floo_test_pkg::AxiCfgN.DataWidth ), + .UserWidth ( floo_test_pkg::AxiCfgN.UserWidth ), + .IdWidth ( floo_test_pkg::AxiCfgN.OutIdWidth ), + .axi_req_t ( axi_narrow_out_req_t ), + .axi_rsp_t ( axi_narrow_out_rsp_t ), + .aw_chan_t ( axi_narrow_out_aw_chan_t ), + .w_chan_t ( axi_narrow_out_w_chan_t ), + .b_chan_t ( axi_narrow_out_b_chan_t ), + .ar_chan_t ( axi_narrow_out_ar_chan_t ), + .r_chan_t ( axi_narrow_out_r_chan_t ) ) i_floo_narrow_hbm_model [West:North][NumMax-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -159,7 +151,7 @@ module tb_floo_dma_mesh; if (i == North) begin : gen_north_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: j+1, y: NumY+1}; + assign xy_id_hbm[j] = '{x: j+1, y: NumY+1, port_id: 0}; end assign req_hbm_in = req_ver_pos[NumY]; assign rsp_hbm_in = rsp_ver_pos[NumY]; @@ -170,7 +162,7 @@ module tb_floo_dma_mesh; end else if (i == South) begin : gen_south_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: j+1, y: 0}; + assign xy_id_hbm[j] = '{x: j+1, y: 0, port_id: 0}; end assign req_hbm_in = req_ver_neg[0]; assign rsp_hbm_in = rsp_ver_neg[0]; @@ -181,7 +173,7 @@ module tb_floo_dma_mesh; end else if (i == East) begin : gen_east_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: NumX+1, y: j+1}; + assign xy_id_hbm[j] = '{x: NumX+1, y: j+1, port_id: 0}; end assign req_hbm_in = req_hor_pos[NumX]; assign rsp_hbm_in = rsp_hor_pos[NumX]; @@ -192,7 +184,7 @@ module tb_floo_dma_mesh; end else if (i == West) begin : gen_west_hbm_chimneys for (genvar j = 0; j < NumChimneys; j++) begin : gen_hbm_chimney_xy_id - assign xy_id_hbm[j] = '{x: 0, y: j+1}; + assign xy_id_hbm[j] = '{x: 0, y: j+1, port_id: 0}; end assign req_hbm_in = req_hor_neg[0]; assign rsp_hbm_in = rsp_hor_neg[0]; @@ -202,13 +194,25 @@ module tb_floo_dma_mesh; assign wide_hor_pos[0] = wide_hbm_out; end - floo_narrow_wide_chimney #( - .NarrowMaxTxns ( NarrowMaxTxns ), - .WideMaxTxns ( WideMaxTxns ), - .NarrowReorderBufferSize ( NarrowReorderBufferSize ), - .WideReorderBufferSize ( WideReorderBufferSize ), - .CutAx ( CutAx ), - .CutRsp ( CutRsp ) + floo_nw_chimney #( + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .ChimneyCfgN ( floo_test_pkg::ChimneyCfg ), + .ChimneyCfgW ( floo_test_pkg::ChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .hdr_t ( hdr_t ), + .id_t ( id_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) ) i_hbm_chimney [NumChimneys-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -249,26 +253,23 @@ module tb_floo_dma_mesh; floo_wide_t [NumDirections-1:0] wide_out, wide_in; localparam int unsigned Index = y * NumX + x+1; - localparam logic [AxiNarrowInAddrWidth-1:0] MemBaseAddr = - (x+1) << XYAddrOffsetX | (y+1) << XYAddrOffsetY; - assign current_id = '{x: x+1, y: y+1}; + localparam axi_narrow_addr_t MemBaseAddr = + (x+1) << floo_test_pkg::RouteCfg.XYAddrOffsetX | + (y+1) << floo_test_pkg::RouteCfg.XYAddrOffsetY; + assign current_id = '{x: x+1, y: y+1, port_id: 0}; floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiNarrowInDataWidth ), - .AddrWidth ( AxiNarrowInAddrWidth ), - .UserWidth ( AxiNarrowInUserWidth ), - .AxiIdInWidth ( AxiNarrowOutIdWidth ), - .AxiIdOutWidth ( AxiNarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*NarrowMaxTxnsPerId ), - .axi_in_req_t ( axi_narrow_out_req_t ), - .axi_in_rsp_t ( axi_narrow_out_rsp_t ), - .axi_out_req_t ( axi_narrow_in_req_t ), - .axi_out_rsp_t ( axi_narrow_in_rsp_t ), - .JobId ( 100 + Index ) + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgN) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 100 + Index ) ) i_narrow_dma_node ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -280,21 +281,17 @@ module tb_floo_dma_mesh; ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiWideInDataWidth ), - .AddrWidth ( AxiWideInAddrWidth ), - .UserWidth ( AxiWideInUserWidth ), - .AxiIdInWidth ( AxiWideOutIdWidth ), - .AxiIdOutWidth ( AxiWideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*WideMaxTxnsPerId ), - .axi_in_req_t ( axi_wide_out_req_t ), - .axi_in_rsp_t ( axi_wide_out_rsp_t ), - .axi_out_req_t ( axi_wide_in_req_t ), - .axi_out_rsp_t ( axi_wide_in_rsp_t ), - .JobId ( Index ) + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgW) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( Index ) ) i_wide_dma_node ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -306,10 +303,10 @@ module tb_floo_dma_mesh; ); axi_bw_monitor #( - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ), - .AxiIdWidth ( AxiNarrowInIdWidth ), - .Name ( NarrowDmaName ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( floo_test_pkg::AxiCfgN.InIdWidth ), + .Name ( NarrowDmaName ) ) i_axi_narrow_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), @@ -321,10 +318,10 @@ module tb_floo_dma_mesh; ); axi_bw_monitor #( - .req_t ( axi_wide_in_req_t ), - .rsp_t ( axi_wide_in_rsp_t ), - .AxiIdWidth ( AxiWideInIdWidth ), - .Name ( WideDmaName ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( floo_test_pkg::AxiCfgW.InIdWidth ), + .Name ( WideDmaName ) ) i_axi_wide_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), @@ -335,13 +332,25 @@ module tb_floo_dma_mesh; .aw_in_flight_o( ) ); - floo_narrow_wide_chimney #( - .NarrowMaxTxns ( NarrowMaxTxns ), - .WideMaxTxns ( WideMaxTxns ), - .NarrowReorderBufferSize ( NarrowReorderBufferSize ), - .WideReorderBufferSize ( WideReorderBufferSize ), - .CutAx ( CutAx ), - .CutRsp ( CutRsp ) + floo_nw_chimney #( + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .ChimneyCfgN ( floo_test_pkg::ChimneyCfg ), + .ChimneyCfgW ( floo_test_pkg::ChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .hdr_t ( hdr_t ), + .id_t ( id_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) ) i_dma_chimney ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -365,13 +374,19 @@ module tb_floo_dma_mesh; .floo_wide_o ( wide_chimney_man[x][y] ) ); - floo_narrow_wide_router #( - .NumRoutes ( NumDirections ), - .ChannelFifoDepth ( ChannelFifoDepth ), - .OutputFifoDepth ( OutputFifoDepth ), - .RouteAlgo ( RouteAlgo ), - .XYRouteOpt ( 1'b0 ), - .id_t ( id_t ) + floo_nw_router #( + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .NumRoutes ( NumDirections ), + .InFifoDepth ( InFifoDepth ), + .OutFifoDepth ( OutFifoDepth ), + .RouteAlgo ( floo_test_pkg::RouteCfg.RouteAlgo ), + .XYRouteOpt ( 1'b0 ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) ) i_router ( .clk_i ( clk ), .rst_ni ( rst_n ), diff --git a/hw/tb/tb_floo_dma_nw_chimney.sv b/hw/tb/tb_floo_dma_nw_chimney.sv deleted file mode 100644 index b23c1501..00000000 --- a/hw/tb/tb_floo_dma_nw_chimney.sv +++ /dev/null @@ -1,414 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Tim Fischer - -`include "axi/typedef.svh" -`include "axi/assign.svh" -`include "floo_noc/typedef.svh" - -module tb_floo_dma_nw_chimney; - - import floo_pkg::*; - import floo_narrow_wide_pkg::*; - - localparam time CyclTime = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - localparam int unsigned NumTargets = 2; - - localparam int unsigned ReorderBufferSize = 128; - localparam int unsigned MaxTxns = 32; - localparam int unsigned MaxTxnsPerId = 32; - - logic clk, rst_n; - - axi_narrow_in_req_t [NumTargets-1:0] narrow_man_req; - axi_narrow_in_rsp_t [NumTargets-1:0] narrow_man_rsp; - axi_wide_in_req_t [NumTargets-1:0] wide_man_req; - axi_wide_in_rsp_t [NumTargets-1:0] wide_man_rsp; - - axi_narrow_out_req_t [NumTargets-1:0] narrow_sub_req; - axi_narrow_out_rsp_t [NumTargets-1:0] narrow_sub_rsp; - axi_wide_out_req_t [NumTargets-1:0] wide_sub_req; - axi_wide_out_rsp_t [NumTargets-1:0] wide_sub_rsp; - - axi_narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; - axi_narrow_in_rsp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; - axi_wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; - axi_wide_in_rsp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; - - for (genvar i = 0; i < NumDirections; i++) begin : gen_dir - `AXI_ASSIGN_REQ_STRUCT(narrow_sub_req_id_mapped[i], narrow_sub_req[i]) - `AXI_ASSIGN_RESP_STRUCT(narrow_sub_rsp_id_mapped[i], narrow_sub_rsp[i]) - `AXI_ASSIGN_REQ_STRUCT(wide_sub_req_id_mapped[i], wide_sub_req[i]) - `AXI_ASSIGN_RESP_STRUCT(wide_sub_rsp_id_mapped[i], wide_sub_rsp[i]) - end - - floo_req_t [NumTargets-1:0] chimney_req, chimney_req_cut; - floo_rsp_t [NumTargets-1:0] chimney_rsp, chimney_rsp_cut; - floo_wide_t [NumTargets-1:0] chimney_wide, chimney_wide_cut; - - logic [NumTargets*2-1:0] end_of_sim; - - clk_rst_gen #( - .ClkPeriod ( CyclTime ), - .RstClkCycles ( 5 ) - ) i_clk_gen ( - .clk_o ( clk ), - .rst_no ( rst_n ) - ); - - typedef struct packed { - logic [AxiNarrowInAddrWidth-1:0] start_addr; - logic [AxiNarrowInAddrWidth-1:0] end_addr; - } node_addr_region_t; - - localparam int unsigned MemBaseAddr = 32'h0000_0000; - localparam int unsigned MemSize = 32'h0001_0000; - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiNarrowInDataWidth ), - .AddrWidth ( AxiNarrowInAddrWidth ), - .UserWidth ( AxiNarrowInUserWidth ), - .AxiIdInWidth ( AxiNarrowOutIdWidth ), - .AxiIdOutWidth ( AxiNarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( axi_narrow_out_req_t ), - .axi_in_rsp_t ( axi_narrow_out_rsp_t ), - .axi_out_req_t ( axi_narrow_in_req_t ), - .axi_out_rsp_t ( axi_narrow_in_rsp_t ), - .JobId ( 100 ) - ) i_narrow_dma_node_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( narrow_sub_req[0] ), - .axi_in_rsp_o ( narrow_sub_rsp[0] ), - .axi_out_req_o ( narrow_man_req[0] ), - .axi_out_rsp_i ( narrow_man_rsp[0] ), - .end_of_sim_o ( end_of_sim[0] ) - ); - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiWideInDataWidth ), - .AddrWidth ( AxiWideInAddrWidth ), - .UserWidth ( AxiWideInUserWidth ), - .AxiIdInWidth ( AxiWideOutIdWidth ), - .AxiIdOutWidth ( AxiWideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( axi_wide_out_req_t ), - .axi_in_rsp_t ( axi_wide_out_rsp_t ), - .axi_out_req_t ( axi_wide_in_req_t ), - .axi_out_rsp_t ( axi_wide_in_rsp_t ), - .JobId ( 0 ) - ) i_wide_dma_node_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( wide_sub_req[0] ), - .axi_in_rsp_o ( wide_sub_rsp[0] ), - .axi_out_req_o ( wide_man_req[0] ), - .axi_out_rsp_i ( wide_man_rsp[0] ), - .end_of_sim_o ( end_of_sim[1] ) - ); - - axi_chan_compare #( - .aw_chan_t ( axi_narrow_in_aw_chan_t ), - .w_chan_t ( axi_narrow_in_w_chan_t ), - .b_chan_t ( axi_narrow_in_b_chan_t ), - .ar_chan_t ( axi_narrow_in_ar_chan_t ), - .r_chan_t ( axi_narrow_in_r_chan_t ), - .req_t ( axi_narrow_in_req_t ), - .resp_t ( axi_narrow_in_rsp_t ) - ) i_narrow_channel_compare_0 ( - .clk_a_i ( clk ), - .clk_b_i ( clk ), - .axi_a_req ( narrow_man_req[0] ), - .axi_a_res ( narrow_man_rsp[0] ), - .axi_b_req ( narrow_sub_req_id_mapped[1] ), - .axi_b_res ( narrow_sub_rsp_id_mapped[1] ) - ); - - axi_chan_compare #( - .aw_chan_t ( axi_wide_in_aw_chan_t ), - .w_chan_t ( axi_wide_in_w_chan_t ), - .b_chan_t ( axi_wide_in_b_chan_t ), - .ar_chan_t ( axi_wide_in_ar_chan_t ), - .r_chan_t ( axi_wide_in_r_chan_t ), - .req_t ( axi_wide_in_req_t ), - .resp_t ( axi_wide_in_rsp_t ) - ) i_wide_channel_compare_0 ( - .clk_a_i ( clk ), - .clk_b_i ( clk ), - .axi_a_req ( wide_man_req[0] ), - .axi_a_res ( wide_man_rsp[0] ), - .axi_b_req ( wide_sub_req_id_mapped[1] ), - .axi_b_res ( wide_sub_rsp_id_mapped[1] ) - ); - - floo_narrow_wide_chimney #( - .NarrowMaxTxns ( MaxTxns ), - .NarrowMaxTxnsPerId ( MaxTxnsPerId ), - .NarrowReorderBufferSize ( ReorderBufferSize ), - .WideMaxTxns ( MaxTxns ), - .WideMaxTxnsPerId ( MaxTxnsPerId ), - .WideReorderBufferSize ( ReorderBufferSize ) - ) i_floo_narrow_wide_chimney_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .axi_narrow_in_req_i ( narrow_man_req[0] ), - .axi_narrow_in_rsp_o ( narrow_man_rsp[0] ), - .axi_narrow_out_req_o ( narrow_sub_req[0] ), - .axi_narrow_out_rsp_i ( narrow_sub_rsp[0] ), - .axi_wide_in_req_i ( wide_man_req[0] ), - .axi_wide_in_rsp_o ( wide_man_rsp[0] ), - .axi_wide_out_req_o ( wide_sub_req[0] ), - .axi_wide_out_rsp_i ( wide_sub_rsp[0] ), - .id_i ( '0 ), - .route_table_i ( '0 ), - .floo_req_o ( chimney_req[0] ), - .floo_rsp_o ( chimney_rsp[0] ), - .floo_wide_o ( chimney_wide[0] ), - .floo_req_i ( chimney_req_cut[1] ), - .floo_rsp_i ( chimney_rsp_cut[1] ), - .floo_wide_i ( chimney_wide_cut[1] ) - ); - - floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers - .flit_t ( floo_req_chan_t ) - ) i_floo_req_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {chimney_req[1].valid, chimney_req[0].valid} ), - .ready_o ( {chimney_req_cut[1].ready, chimney_req_cut[0].ready} ), - .data_i ( {chimney_req[1].req, chimney_req[0].req} ), - .valid_o ( {chimney_req_cut[1].valid, chimney_req_cut[0].valid} ), - .ready_i ( {chimney_req[1].ready, chimney_req[0].ready} ), - .data_o ( {chimney_req_cut[1].req, chimney_req_cut[0].req} ) - ); - - floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers - .flit_t ( floo_rsp_chan_t ) - ) i_floo_rsp_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {chimney_rsp[1].valid, chimney_rsp[0].valid} ), - .ready_o ( {chimney_rsp_cut[1].ready, chimney_rsp_cut[0].ready} ), - .data_i ( {chimney_rsp[1].rsp, chimney_rsp[0].rsp} ), - .valid_o ( {chimney_rsp_cut[1].valid, chimney_rsp_cut[0].valid} ), - .ready_i ( {chimney_rsp[1].ready, chimney_rsp[0].ready} ), - .data_o ( {chimney_rsp_cut[1].rsp, chimney_rsp_cut[0].rsp} ) - ); - - floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd4 ), // should simulate a hop with 2 routers - .flit_t ( floo_wide_chan_t ) - ) i_floo_wide_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {chimney_wide[1].valid, chimney_wide[0].valid} ), - .ready_o ( {chimney_wide_cut[1].ready, chimney_wide_cut[0].ready} ), - .data_i ( {chimney_wide[1].wide, chimney_wide[0].wide} ), - .valid_o ( {chimney_wide_cut[1].valid, chimney_wide_cut[0].valid} ), - .ready_i ( {chimney_wide[1].ready, chimney_wide[0].ready} ), - .data_o ( {chimney_wide_cut[1].wide, chimney_wide_cut[0].wide} ) - ); - - floo_narrow_wide_chimney #( - .NarrowMaxTxns ( MaxTxns ), - .NarrowMaxTxnsPerId ( MaxTxnsPerId ), - .NarrowReorderBufferSize ( ReorderBufferSize ), - .WideMaxTxns ( MaxTxns ), - .WideMaxTxnsPerId ( MaxTxnsPerId ), - .WideReorderBufferSize ( ReorderBufferSize ) - ) i_floo_narrow_wide_chimney_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .axi_narrow_in_req_i ( narrow_man_req[1] ), - .axi_narrow_in_rsp_o ( narrow_man_rsp[1] ), - .axi_narrow_out_req_o ( narrow_sub_req[1] ), - .axi_narrow_out_rsp_i ( narrow_sub_rsp[1] ), - .axi_wide_in_req_i ( wide_man_req[1] ), - .axi_wide_in_rsp_o ( wide_man_rsp[1] ), - .axi_wide_out_req_o ( wide_sub_req[1] ), - .axi_wide_out_rsp_i ( wide_sub_rsp[1] ), - .id_i ( '0 ), - .route_table_i ( '0 ), - .floo_req_o ( chimney_req[1] ), - .floo_rsp_o ( chimney_rsp[1] ), - .floo_wide_o ( chimney_wide[1] ), - .floo_req_i ( chimney_req_cut[0] ), - .floo_rsp_i ( chimney_rsp_cut[0] ), - .floo_wide_i ( chimney_wide_cut[0] ) - ); - - axi_chan_compare #( - .aw_chan_t ( axi_narrow_in_aw_chan_t ), - .w_chan_t ( axi_narrow_in_w_chan_t ), - .b_chan_t ( axi_narrow_in_b_chan_t ), - .ar_chan_t ( axi_narrow_in_ar_chan_t ), - .r_chan_t ( axi_narrow_in_r_chan_t ), - .req_t ( axi_narrow_in_req_t ), - .resp_t ( axi_narrow_in_rsp_t ) - ) i_narrow_channel_compare_1 ( - .clk_a_i ( clk ), - .clk_b_i ( clk ), - .axi_a_req ( narrow_man_req[1] ), - .axi_a_res ( narrow_man_rsp[1] ), - .axi_b_req ( narrow_sub_req_id_mapped[0] ), - .axi_b_res ( narrow_sub_rsp_id_mapped[0] ) - ); - - axi_chan_compare #( - .aw_chan_t ( axi_wide_in_aw_chan_t ), - .w_chan_t ( axi_wide_in_w_chan_t ), - .b_chan_t ( axi_wide_in_b_chan_t ), - .ar_chan_t ( axi_wide_in_ar_chan_t ), - .r_chan_t ( axi_wide_in_r_chan_t ), - .req_t ( axi_wide_in_req_t ), - .resp_t ( axi_wide_in_rsp_t ) - ) i_wide_channel_compare_1 ( - .clk_a_i ( clk ), - .clk_b_i ( clk ), - .axi_a_req ( wide_man_req[1] ), - .axi_a_res ( wide_man_rsp[1] ), - .axi_b_req ( wide_sub_req_id_mapped[0] ), - .axi_b_res ( wide_sub_rsp_id_mapped[0] ) - ); - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiNarrowInDataWidth ), - .AddrWidth ( AxiNarrowInAddrWidth ), - .UserWidth ( AxiNarrowInUserWidth ), - .AxiIdInWidth ( AxiNarrowOutIdWidth ), - .AxiIdOutWidth ( AxiNarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( axi_narrow_out_req_t ), - .axi_in_rsp_t ( axi_narrow_out_rsp_t ), - .axi_out_req_t ( axi_narrow_in_req_t ), - .axi_out_rsp_t ( axi_narrow_in_rsp_t ), - .JobId ( 101 ) - ) i_narrow_dma_node_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( narrow_sub_req[1] ), - .axi_in_rsp_o ( narrow_sub_rsp[1] ), - .axi_out_req_o ( narrow_man_req[1] ), - .axi_out_rsp_i ( narrow_man_rsp[1] ), - .end_of_sim_o ( end_of_sim[2] ) - ); - - floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiWideInDataWidth ), - .AddrWidth ( AxiWideInAddrWidth ), - .UserWidth ( AxiWideInUserWidth ), - .AxiIdInWidth ( AxiWideOutIdWidth ), - .AxiIdOutWidth ( AxiWideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( axi_wide_out_req_t ), - .axi_in_rsp_t ( axi_wide_out_rsp_t ), - .axi_out_req_t ( axi_wide_in_req_t ), - .axi_out_rsp_t ( axi_wide_in_rsp_t ), - .JobId ( 1 ) - ) i_wide_dma_node_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .axi_in_req_i ( wide_sub_req[1] ), - .axi_in_rsp_o ( wide_sub_rsp[1] ), - .axi_out_req_o ( wide_man_req[1] ), - .axi_out_rsp_i ( wide_man_rsp[1] ), - .end_of_sim_o ( end_of_sim[3] ) - ); - - axi_bw_monitor #( - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ), - .AxiIdWidth ( AxiNarrowInIdWidth ), - .Name ( "narrow 0" ) - ) i_axi_narrow_bw_monitor_0 ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( &end_of_sim ), - .req_i ( narrow_man_req[0] ), - .rsp_i ( narrow_man_rsp[0] ), - .ar_in_flight_o ( ), - .aw_in_flight_o ( ) - ); - - axi_bw_monitor #( - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ), - .AxiIdWidth ( AxiNarrowInIdWidth ), - .Name ( "narrow 1" ) - ) i_axi_narrow_bw_monitor_1 ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( &end_of_sim ), - .req_i ( narrow_man_req[1] ), - .rsp_i ( narrow_man_rsp[1] ), - .ar_in_flight_o ( ), - .aw_in_flight_o ( ) - ); - - axi_bw_monitor #( - .req_t ( axi_wide_in_req_t ), - .rsp_t ( axi_wide_in_rsp_t ), - .AxiIdWidth ( AxiWideInIdWidth ), - .Name ( "wide 0" ) - ) i_axi_wide_bw_monitor_0 ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( &end_of_sim ), - .req_i ( wide_man_req[0] ), - .rsp_i ( wide_man_rsp[0] ), - .ar_in_flight_o ( ), - .aw_in_flight_o ( ) - ); - - axi_bw_monitor #( - .req_t ( axi_wide_in_req_t ), - .rsp_t ( axi_wide_in_rsp_t ), - .AxiIdWidth ( AxiWideInIdWidth ), - .Name ( "wide 1" ) - ) i_axi_wide_bw_monitor_1 ( - .clk_i ( clk ), - .en_i ( rst_n ), - .end_of_sim_i ( &end_of_sim ), - .req_i ( wide_man_req[1] ), - .rsp_i ( wide_man_rsp[1] ), - .ar_in_flight_o ( ), - .aw_in_flight_o ( ) - ); - - initial begin - wait(&end_of_sim); - // Wait for some time - repeat (2) @(posedge clk); - // Stop the simulation - $stop; - end - - -endmodule diff --git a/hw/tb/tb_floo_narrow_wide_chimney.sv b/hw/tb/tb_floo_narrow_wide_chimney.sv deleted file mode 100644 index 9ceece4b..00000000 --- a/hw/tb/tb_floo_narrow_wide_chimney.sv +++ /dev/null @@ -1,361 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Tim Fischer - -`include "axi/typedef.svh" -`include "axi/assign.svh" -`include "floo_noc/typedef.svh" - -module tb_floo_narrow_wide_chimney; - - import floo_pkg::*; - import floo_narrow_wide_pkg::*; - - localparam time CyclTime = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - localparam int unsigned NarrowNumReads = 1000; - localparam int unsigned NarrowNumWrites = 1000; - localparam int unsigned WideNumReads = 1000; - localparam int unsigned WideNumWrites = 1000; - - localparam bit AtopSupport = 1'b1; - localparam int unsigned WideMaxUniqueIds = 2; - localparam int unsigned MaxAtomicTxns = 3; - - localparam int unsigned NumTargets = 2; - - localparam int unsigned ReorderBufferSize = 128; - localparam int unsigned MaxTxns = 32; - localparam int unsigned MaxTxnsPerId = 32; - - logic clk, rst_n; - - axi_narrow_in_req_t [NumTargets-1:0] narrow_man_req; - axi_narrow_in_rsp_t [NumTargets-1:0] narrow_man_rsp; - axi_wide_in_req_t [NumTargets-1:0] wide_man_req; - axi_wide_in_rsp_t [NumTargets-1:0] wide_man_rsp; - - axi_narrow_out_req_t [NumTargets-1:0] narrow_sub_req; - axi_narrow_out_rsp_t [NumTargets-1:0] narrow_sub_rsp; - axi_wide_out_req_t [NumTargets-1:0] wide_sub_req; - axi_wide_out_rsp_t [NumTargets-1:0] wide_sub_rsp; - - axi_narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; - axi_narrow_in_rsp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; - axi_wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; - axi_wide_in_rsp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; - - for (genvar i = 0; i < NumDirections; i++) begin : gen_dir - `AXI_ASSIGN_REQ_STRUCT(narrow_sub_req_id_mapped[i], narrow_sub_req[i]) - `AXI_ASSIGN_RESP_STRUCT(narrow_sub_rsp_id_mapped[i], narrow_sub_rsp[i]) - `AXI_ASSIGN_REQ_STRUCT(wide_sub_req_id_mapped[i], wide_sub_req[i]) - `AXI_ASSIGN_RESP_STRUCT(wide_sub_rsp_id_mapped[i], wide_sub_rsp[i]) - end - - floo_req_t [NumTargets-1:0] chimney_req; - floo_rsp_t [NumTargets-1:0] chimney_rsp; - floo_wide_t [NumTargets-1:0] chimney_wide; - - logic [NumTargets*3-1:0] end_of_sim; - - clk_rst_gen #( - .ClkPeriod ( CyclTime ), - .RstClkCycles ( 5 ) - ) i_clk_gen ( - .clk_o ( clk ), - .rst_no ( rst_n ) - ); - - typedef struct packed { - logic [AxiNarrowInAddrWidth-1:0] start_addr; - logic [AxiNarrowInAddrWidth-1:0] end_addr; - } node_addr_region_t; - - localparam int unsigned NumAddrRegions = 1; - localparam node_addr_region_t [NumAddrRegions-1:0] AddrRegions = '{ - '{start_addr: 48'h000_0000_0000, end_addr: 48'h000_0000_8000} - }; - - typedef struct packed { - int unsigned idx; - logic [AxiNarrowInAddrWidth-1:0] start_addr; - logic [AxiNarrowInAddrWidth-1:0] end_addr; - } node_addr_region_id_t; - - node_addr_region_id_t [NumTargets-1:0] node_addr_regions; - assign node_addr_regions = '{ - '{idx: 0, start_addr: 48'h000_0000_0000, end_addr: 48'h000_0000_4000}, - '{idx: 1, start_addr: 48'h000_0000_4000, end_addr: 48'h000_0000_8000} - }; - - floo_axi_test_node #( - .AxiAddrWidth ( AxiNarrowInAddrWidth ), - .AxiDataWidth ( AxiNarrowInDataWidth ), - .AxiIdInWidth ( AxiNarrowOutIdWidth ), - .AxiIdOutWidth ( AxiNarrowInIdWidth ), - .AxiUserWidth ( AxiNarrowInUserWidth ), - .mst_req_t ( axi_narrow_in_req_t ), - .mst_rsp_t ( axi_narrow_in_rsp_t ), - .slv_req_t ( axi_narrow_out_req_t ), - .slv_rsp_t ( axi_narrow_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( AtopSupport ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NarrowNumReads ), - .NumWrites ( NarrowNumWrites ) - ) i_narrow_test_node_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .mst_port_req_o ( narrow_man_req[0] ), - .mst_port_rsp_i ( narrow_man_rsp[0] ), - .slv_port_req_i ( narrow_sub_req[0] ), - .slv_port_rsp_o ( narrow_sub_rsp[0] ), - .end_of_sim ( end_of_sim[0] ) - ); - - floo_axi_test_node #( - .AxiAddrWidth ( AxiWideInAddrWidth ), - .AxiDataWidth ( AxiWideInDataWidth ), - .AxiIdInWidth ( AxiWideOutIdWidth ), - .AxiIdOutWidth ( AxiWideInIdWidth ), - .AxiUserWidth ( AxiWideInUserWidth ), - .mst_req_t ( axi_wide_in_req_t ), - .mst_rsp_t ( axi_wide_in_rsp_t ), - .slv_req_t ( axi_wide_out_req_t ), - .slv_rsp_t ( axi_wide_out_rsp_t ), - .Atops ( 1'b0 ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( WideNumReads ), - .NumWrites ( WideNumWrites ) - ) i_wide_test_node_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .mst_port_req_o ( wide_man_req[0] ), - .mst_port_rsp_i ( wide_man_rsp[0] ), - .slv_port_req_i ( wide_sub_req[0] ), - .slv_port_rsp_o ( wide_sub_rsp[0] ), - .end_of_sim ( end_of_sim[1] ) - ); - - axi_reorder_remap_compare #( - .AxiInIdWidth ( AxiNarrowInIdWidth ), - .AxiOutIdWidth ( AxiNarrowOutIdWidth ), - .aw_chan_t ( axi_narrow_in_aw_chan_t ), - .w_chan_t ( axi_narrow_in_w_chan_t ), - .b_chan_t ( axi_narrow_in_b_chan_t ), - .ar_chan_t ( axi_narrow_in_ar_chan_t ), - .r_chan_t ( axi_narrow_in_r_chan_t ), - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ) - ) i_narrow_channel_compare_0 ( - .clk_i ( clk ), - .mon_mst_req_i ( narrow_man_req[0] ), - .mon_mst_rsp_i ( narrow_man_rsp[0] ), - .mon_slv_req_i ( narrow_sub_req_id_mapped[1] ), - .mon_slv_rsp_i ( narrow_sub_rsp_id_mapped[1] ), - .end_of_sim_o ( end_of_sim[2] ) - ); - - axi_chan_compare #( - .IgnoreId ( 1'b1 ), - .aw_chan_t ( axi_wide_in_aw_chan_t ), - .w_chan_t ( axi_wide_in_w_chan_t ), - .b_chan_t ( axi_wide_in_b_chan_t ), - .ar_chan_t ( axi_wide_in_ar_chan_t ), - .r_chan_t ( axi_wide_in_r_chan_t ), - .req_t ( axi_wide_in_req_t ), - .resp_t ( axi_wide_in_rsp_t ) - ) i_wide_channel_compare_0 ( - .clk_a_i ( clk ), - .clk_b_i ( clk ), - .axi_a_req ( wide_man_req[0] ), - .axi_a_res ( wide_man_rsp[0] ), - .axi_b_req ( wide_sub_req_id_mapped[1] ), - .axi_b_res ( wide_sub_rsp_id_mapped[1] ) - ); - - floo_narrow_wide_chimney #( - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( MaxAtomicTxns ), - .NarrowMaxTxns ( MaxTxns ), - .NarrowMaxTxnsPerId ( MaxTxnsPerId ), - .NarrowReorderBufferSize ( ReorderBufferSize ), - .WideMaxTxns ( MaxTxns ), - .WideMaxUniqueIds ( WideMaxUniqueIds ), - .WideMaxTxnsPerId ( MaxTxnsPerId ), - .WideReorderBufferSize ( ReorderBufferSize ), - .CutAx ( 1'b0 ), - .CutRsp ( 1'b1 ) - ) i_floo_narrow_wide_chimney_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .axi_narrow_in_req_i ( narrow_man_req[0] ), - .axi_narrow_in_rsp_o ( narrow_man_rsp[0] ), - .axi_narrow_out_req_o ( narrow_sub_req[0] ), - .axi_narrow_out_rsp_i ( narrow_sub_rsp[0] ), - .axi_wide_in_req_i ( wide_man_req[0] ), - .axi_wide_in_rsp_o ( wide_man_rsp[0] ), - .axi_wide_out_req_o ( wide_sub_req[0] ), - .axi_wide_out_rsp_i ( wide_sub_rsp[0] ), - .id_i ( '0 ), - .route_table_i ( '0 ), - .floo_req_o ( chimney_req[0] ), - .floo_rsp_o ( chimney_rsp[0] ), - .floo_wide_o ( chimney_wide[0] ), - .floo_req_i ( chimney_req[1] ), - .floo_rsp_i ( chimney_rsp[1] ), - .floo_wide_i ( chimney_wide[1] ) - ); - - floo_narrow_wide_chimney #( - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( MaxAtomicTxns ), - .NarrowMaxTxns ( MaxTxns ), - .NarrowMaxTxnsPerId ( MaxTxnsPerId ), - .NarrowReorderBufferSize ( ReorderBufferSize ), - .WideMaxTxns ( MaxTxns ), - .WideMaxUniqueIds ( WideMaxUniqueIds ), - .WideMaxTxnsPerId ( MaxTxnsPerId ), - .WideReorderBufferSize ( ReorderBufferSize ), - .CutAx ( 1'b0 ), - .CutRsp ( 1'b1 ) - ) i_floo_narrow_wide_chimney_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .axi_narrow_in_req_i ( narrow_man_req[1] ), - .axi_narrow_in_rsp_o ( narrow_man_rsp[1] ), - .axi_narrow_out_req_o ( narrow_sub_req[1] ), - .axi_narrow_out_rsp_i ( narrow_sub_rsp[1] ), - .axi_wide_in_req_i ( wide_man_req[1] ), - .axi_wide_in_rsp_o ( wide_man_rsp[1] ), - .axi_wide_out_req_o ( wide_sub_req[1] ), - .axi_wide_out_rsp_i ( wide_sub_rsp[1] ), - .id_i ( '0 ), - .route_table_i ( '0 ), - .floo_req_o ( chimney_req[1] ), - .floo_rsp_o ( chimney_rsp[1] ), - .floo_wide_o ( chimney_wide[1] ), - .floo_req_i ( chimney_req[0] ), - .floo_rsp_i ( chimney_rsp[0] ), - .floo_wide_i ( chimney_wide[0] ) - ); - - axi_reorder_remap_compare #( - .AxiInIdWidth ( AxiNarrowInIdWidth ), - .AxiOutIdWidth ( AxiNarrowOutIdWidth ), - .aw_chan_t ( axi_narrow_in_aw_chan_t ), - .w_chan_t ( axi_narrow_in_w_chan_t ), - .b_chan_t ( axi_narrow_in_b_chan_t ), - .ar_chan_t ( axi_narrow_in_ar_chan_t ), - .r_chan_t ( axi_narrow_in_r_chan_t ), - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ) - ) i_narrow_channel_compare_1 ( - .clk_i ( clk ), - .mon_mst_req_i ( narrow_man_req[1] ), - .mon_mst_rsp_i ( narrow_man_rsp[1] ), - .mon_slv_req_i ( narrow_sub_req_id_mapped[0] ), - .mon_slv_rsp_i ( narrow_sub_rsp_id_mapped[0] ), - .end_of_sim_o ( end_of_sim[3] ) - ); - - axi_chan_compare #( - .IgnoreId ( 1'b1 ), - .aw_chan_t ( axi_wide_in_aw_chan_t ), - .w_chan_t ( axi_wide_in_w_chan_t ), - .b_chan_t ( axi_wide_in_b_chan_t ), - .ar_chan_t ( axi_wide_in_ar_chan_t ), - .r_chan_t ( axi_wide_in_r_chan_t ), - .req_t ( axi_wide_in_req_t ), - .resp_t ( axi_wide_in_rsp_t ) - ) i_wide_channel_compare_1 ( - .clk_a_i ( clk ), - .clk_b_i ( clk ), - .axi_a_req ( wide_man_req[1] ), - .axi_a_res ( wide_man_rsp[1] ), - .axi_b_req ( wide_sub_req_id_mapped[0] ), - .axi_b_res ( wide_sub_rsp_id_mapped[0] ) - ); - - floo_axi_test_node #( - .AxiAddrWidth ( AxiNarrowInAddrWidth ), - .AxiDataWidth ( AxiNarrowInDataWidth ), - .AxiIdOutWidth ( AxiNarrowInIdWidth ), - .AxiIdInWidth ( AxiNarrowOutIdWidth ), - .AxiUserWidth ( AxiNarrowInUserWidth ), - .mst_req_t ( axi_narrow_in_req_t ), - .mst_rsp_t ( axi_narrow_in_rsp_t ), - .slv_req_t ( axi_narrow_out_req_t ), - .slv_rsp_t ( axi_narrow_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( AtopSupport ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NarrowNumReads ), - .NumWrites ( NarrowNumWrites ) - ) i_narrow_test_node_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .mst_port_req_o ( narrow_man_req[1] ), - .mst_port_rsp_i ( narrow_man_rsp[1] ), - .slv_port_req_i ( narrow_sub_req[1] ), - .slv_port_rsp_o ( narrow_sub_rsp[1] ), - .end_of_sim ( end_of_sim[4] ) - ); - - floo_axi_test_node #( - .AxiAddrWidth ( AxiWideInAddrWidth ), - .AxiDataWidth ( AxiWideInDataWidth ), - .AxiIdInWidth ( AxiWideOutIdWidth ), - .AxiIdOutWidth ( AxiWideInIdWidth ), - .AxiUserWidth ( AxiWideInUserWidth ), - .mst_req_t ( axi_wide_in_req_t ), - .mst_rsp_t ( axi_wide_in_rsp_t ), - .slv_req_t ( axi_wide_out_req_t ), - .slv_rsp_t ( axi_wide_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .Atops ( 1'b0 ), - .AxiMaxBurstLen ( ReorderBufferSize ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( WideNumReads ), - .NumWrites ( WideNumWrites ) - ) i_wide_test_node_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .mst_port_req_o ( wide_man_req[1] ), - .mst_port_rsp_i ( wide_man_rsp[1] ), - .slv_port_req_i ( wide_sub_req[1] ), - .slv_port_rsp_o ( wide_sub_rsp[1] ), - .end_of_sim ( end_of_sim[5] ) - ); - - initial begin - wait(&end_of_sim); - $stop; - end - - -endmodule diff --git a/hw/tb/tb_floo_nw_chimney.sv b/hw/tb/tb_floo_nw_chimney.sv new file mode 100644 index 00000000..ef8736bb --- /dev/null +++ b/hw/tb/tb_floo_nw_chimney.sv @@ -0,0 +1,372 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +`include "axi/typedef.svh" +`include "axi/assign.svh" +`include "floo_noc/typedef.svh" + +module tb_floo_nw_chimney; + + import floo_pkg::*; + + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + localparam int unsigned NarrowNumReads = 1000; + localparam int unsigned NarrowNumWrites = 1000; + localparam int unsigned WideNumReads = 1000; + localparam int unsigned WideNumWrites = 1000; + + localparam bit AtopSupport = 1'b1; + localparam int unsigned MaxAtomicTxns = 3; + + // Function to generate a chimney config UniqueIds for testing + function automatic chimney_cfg_t gen_wide_chimney_cfg(); + chimney_cfg_t cfg = ChimneyDefaultCfg; + // cfg.MaxUniqueIds = 2; + cfg.CutRsp = 1'b1; // Otherwise the compare will fail since it is a feedthrough + return cfg; + endfunction + + function automatic chimney_cfg_t gen_narrow_chimney_cfg(); + chimney_cfg_t cfg = ChimneyDefaultCfg; + cfg.CutRsp = 1'b1; // Otherwise the compare will fail since it is a feedthrough + return cfg; + endfunction + + // Default chimney config with RoB for testing + localparam chimney_cfg_t WideChimneyCfg = gen_wide_chimney_cfg(); + localparam chimney_cfg_t NarrowChimneyCfg = gen_narrow_chimney_cfg(); + + localparam int unsigned NumTargets = 2; + + logic clk, rst_n; + + typedef logic [1:0] x_bits_t; + typedef logic [1:0] y_bits_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in, + floo_test_pkg::AxiCfgN, floo_test_pkg::AxiCfgW, hdr_t) + `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) + + axi_narrow_in_req_t [NumTargets-1:0] narrow_man_req; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_man_rsp; + axi_wide_in_req_t [NumTargets-1:0] wide_man_req; + axi_wide_in_rsp_t [NumTargets-1:0] wide_man_rsp; + + axi_narrow_out_req_t [NumTargets-1:0] narrow_sub_req; + axi_narrow_out_rsp_t [NumTargets-1:0] narrow_sub_rsp; + axi_wide_out_req_t [NumTargets-1:0] wide_sub_req; + axi_wide_out_rsp_t [NumTargets-1:0] wide_sub_rsp; + + axi_narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; + axi_wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; + axi_wide_in_rsp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; + + for (genvar i = 0; i < NumTargets; i++) begin : gen_dir + `AXI_ASSIGN_REQ_STRUCT(narrow_sub_req_id_mapped[i], narrow_sub_req[i]) + `AXI_ASSIGN_RESP_STRUCT(narrow_sub_rsp_id_mapped[i], narrow_sub_rsp[i]) + `AXI_ASSIGN_REQ_STRUCT(wide_sub_req_id_mapped[i], wide_sub_req[i]) + `AXI_ASSIGN_RESP_STRUCT(wide_sub_rsp_id_mapped[i], wide_sub_rsp[i]) + end + + floo_req_t [NumTargets-1:0] chimney_req; + floo_rsp_t [NumTargets-1:0] chimney_rsp; + floo_wide_t [NumTargets-1:0] chimney_wide; + + logic [NumTargets*3-1:0] end_of_sim; + + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o ( clk ), + .rst_no ( rst_n ) + ); + + typedef struct packed { + logic [floo_test_pkg::AxiCfg.AddrWidth-1:0] start_addr; + logic [floo_test_pkg::AxiCfg.AddrWidth-1:0] end_addr; + } node_addr_region_t; + + localparam int unsigned NumAddrRegions = 1; + localparam node_addr_region_t [NumAddrRegions-1:0] AddrRegions = '{ + '{start_addr: 32'h0000_0000, end_addr: 32'h0000_8000} + }; + + floo_axi_test_node #( + .AxiCfg ( floo_test_pkg::AxiCfgN ), + .mst_req_t ( axi_narrow_in_req_t ), + .mst_rsp_t ( axi_narrow_in_rsp_t ), + .slv_req_t ( axi_narrow_out_req_t ), + .slv_rsp_t ( axi_narrow_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( AtopSupport ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .AxiMaxBurstLen ( 1 ), + .NumReads ( NarrowNumReads ), + .NumWrites ( NarrowNumWrites ) + ) i_narrow_test_node_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mst_port_req_o ( narrow_man_req[0] ), + .mst_port_rsp_i ( narrow_man_rsp[0] ), + .slv_port_req_i ( narrow_sub_req[0] ), + .slv_port_rsp_o ( narrow_sub_rsp[0] ), + .end_of_sim ( end_of_sim[0] ) + ); + + floo_axi_test_node #( + .AxiCfg ( floo_test_pkg::AxiCfg ), + .mst_req_t ( axi_wide_in_req_t ), + .mst_rsp_t ( axi_wide_in_rsp_t ), + .slv_req_t ( axi_wide_out_req_t ), + .slv_rsp_t ( axi_wide_out_rsp_t ), + .Atops ( 1'b0 ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .NumReads ( WideNumReads ), + .NumWrites ( WideNumWrites ) + ) i_wide_test_node_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mst_port_req_o ( wide_man_req[0] ), + .mst_port_rsp_i ( wide_man_rsp[0] ), + .slv_port_req_i ( wide_sub_req[0] ), + .slv_port_rsp_o ( wide_sub_rsp[0] ), + .end_of_sim ( end_of_sim[1] ) + ); + + axi_reorder_remap_compare #( + .AxiInIdWidth ( floo_test_pkg::AxiCfgN.InIdWidth ), + .AxiOutIdWidth ( floo_test_pkg::AxiCfgN.OutIdWidth ), + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ) + ) i_narrow_channel_compare_0 ( + .clk_i ( clk ), + .mon_mst_req_i ( narrow_man_req[0] ), + .mon_mst_rsp_i ( narrow_man_rsp[0] ), + .mon_slv_req_i ( narrow_sub_req_id_mapped[1] ), + .mon_slv_rsp_i ( narrow_sub_rsp_id_mapped[1] ), + .end_of_sim_o ( end_of_sim[2] ) + ); + + axi_chan_compare #( + .IgnoreId ( 1'b1 ), + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) + ) i_wide_channel_compare_0 ( + .clk_a_i ( clk ), + .clk_b_i ( clk ), + .axi_a_req ( wide_man_req[0] ), + .axi_a_res ( wide_man_rsp[0] ), + .axi_b_req ( wide_sub_req_id_mapped[1] ), + .axi_b_res ( wide_sub_rsp_id_mapped[1] ) + ); + + floo_nw_chimney #( + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .ChimneyCfgN ( NarrowChimneyCfg ), + .ChimneyCfgW ( WideChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .hdr_t ( hdr_t ), + .id_t ( id_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) + ) i_floo_narrow_wide_chimney_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[0] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[0] ), + .axi_narrow_out_req_o ( narrow_sub_req[0] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[0] ), + .axi_wide_in_req_i ( wide_man_req[0] ), + .axi_wide_in_rsp_o ( wide_man_rsp[0] ), + .axi_wide_out_req_o ( wide_sub_req[0] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[0] ), + .id_i ( '0 ), + .route_table_i ( '0 ), + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_wide_o ( chimney_wide[0] ), + .floo_req_i ( chimney_req[1] ), + .floo_rsp_i ( chimney_rsp[1] ), + .floo_wide_i ( chimney_wide[1] ) + ); + + floo_nw_chimney #( + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .ChimneyCfgN ( NarrowChimneyCfg ), + .ChimneyCfgW ( WideChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .hdr_t ( hdr_t ), + .id_t ( id_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) + ) i_floo_narrow_wide_chimney_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[1] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[1] ), + .axi_narrow_out_req_o ( narrow_sub_req[1] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[1] ), + .axi_wide_in_req_i ( wide_man_req[1] ), + .axi_wide_in_rsp_o ( wide_man_rsp[1] ), + .axi_wide_out_req_o ( wide_sub_req[1] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[1] ), + .id_i ( '0 ), + .route_table_i ( '0 ), + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_wide_o ( chimney_wide[1] ), + .floo_req_i ( chimney_req[0] ), + .floo_rsp_i ( chimney_rsp[0] ), + .floo_wide_i ( chimney_wide[0] ) + ); + + axi_reorder_remap_compare #( + .AxiInIdWidth ( floo_test_pkg::AxiCfgN.InIdWidth ), + .AxiOutIdWidth ( floo_test_pkg::AxiCfgN.OutIdWidth ), + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ) + ) i_narrow_channel_compare_1 ( + .clk_i ( clk ), + .mon_mst_req_i ( narrow_man_req[1] ), + .mon_mst_rsp_i ( narrow_man_rsp[1] ), + .mon_slv_req_i ( narrow_sub_req_id_mapped[0] ), + .mon_slv_rsp_i ( narrow_sub_rsp_id_mapped[0] ), + .end_of_sim_o ( end_of_sim[3] ) + ); + + axi_chan_compare #( + .IgnoreId ( 1'b1 ), + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) + ) i_wide_channel_compare_1 ( + .clk_a_i ( clk ), + .clk_b_i ( clk ), + .axi_a_req ( wide_man_req[1] ), + .axi_a_res ( wide_man_rsp[1] ), + .axi_b_req ( wide_sub_req_id_mapped[0] ), + .axi_b_res ( wide_sub_rsp_id_mapped[0] ) + ); + + floo_axi_test_node #( + .AxiCfg ( floo_test_pkg::AxiCfgN ), + .mst_req_t ( axi_narrow_in_req_t ), + .mst_rsp_t ( axi_narrow_in_rsp_t ), + .slv_req_t ( axi_narrow_out_req_t ), + .slv_rsp_t ( axi_narrow_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( AtopSupport ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + + .AxiMaxBurstLen ( 1 ), + .NumReads ( NarrowNumReads ), + .NumWrites ( NarrowNumWrites ) + ) i_narrow_test_node_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mst_port_req_o ( narrow_man_req[1] ), + .mst_port_rsp_i ( narrow_man_rsp[1] ), + .slv_port_req_i ( narrow_sub_req[1] ), + .slv_port_rsp_o ( narrow_sub_rsp[1] ), + .end_of_sim ( end_of_sim[4] ) + ); + + floo_axi_test_node #( + .AxiCfg ( floo_test_pkg::AxiCfgW ), + .mst_req_t ( axi_wide_in_req_t ), + .mst_rsp_t ( axi_wide_in_rsp_t ), + .slv_req_t ( axi_wide_out_req_t ), + .slv_rsp_t ( axi_wide_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .Atops ( 1'b0 ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( WideNumReads ), + .NumWrites ( WideNumWrites ) + ) i_wide_test_node_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mst_port_req_o ( wide_man_req[1] ), + .mst_port_rsp_i ( wide_man_rsp[1] ), + .slv_port_req_i ( wide_sub_req[1] ), + .slv_port_rsp_o ( wide_sub_rsp[1] ), + .end_of_sim ( end_of_sim[5] ) + ); + + initial begin + wait(&end_of_sim); + $stop; + end + + +endmodule diff --git a/hw/tb/tb_floo_rob.sv b/hw/tb/tb_floo_rob.sv index 35e063e1..57648561 100644 --- a/hw/tb/tb_floo_rob.sv +++ b/hw/tb/tb_floo_rob.sv @@ -11,8 +11,6 @@ module tb_floo_rob; import floo_pkg::*; - import floo_test_pkg::*; - import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -21,14 +19,32 @@ module tb_floo_rob; localparam int unsigned NumReads = 1000; localparam int unsigned NumWrites = 1000; - localparam int unsigned ReorderBufferSize = 64; - localparam int unsigned MaxTxns = 32; - localparam int unsigned MaxTxnsPerId = 32; - localparam int unsigned NumSlaves = 4; logic clk, rst_n; + // Function to generate a chimney config with a RoB + function automatic chimney_cfg_t gen_rob_chimney_cfg(); + chimney_cfg_t cfg = ChimneyDefaultCfg; + cfg.BRoBType = SimpleRoB; + cfg.BRoBDepth = 64; + cfg.RRoBType = NoRoB; + cfg.RRoBDepth = 64; + return cfg; + endfunction + + // Default chimney config with RoB for testing + localparam chimney_cfg_t RoBChimneyCfg = gen_rob_chimney_cfg(); + typedef logic [$clog2(RoBChimneyCfg.BRoBDepth)-1:0] rob_idx_t; + + typedef logic [1:0] x_bits_t; + typedef logic [1:0] y_bits_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, rob_idx_t) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi, floo_test_pkg::AxiCfg) + `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_in, floo_test_pkg::AxiCfg, hdr_t) + `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) + axi_in_req_t node_mst_req; axi_in_rsp_t node_mst_rsp; @@ -52,7 +68,7 @@ module tb_floo_rob; logic [NumDirections-1:0] chimney_req_in_valid, chimney_req_in_ready; logic [NumDirections-1:0] chimney_rsp_in_valid, chimney_rsp_in_ready; - for (genvar i = 0; i < NumDirections; i++) begin : gen_directions + for (genvar i = 0; i < floo_pkg::NumDirections; i++) begin : gen_directions assign chimney_req_out_chan[i] = chimney_req_out[i].req; assign chimney_rsp_out_chan[i] = chimney_rsp_out[i].rsp; assign chimney_req_in[i].req = chimney_req_in_chan[i]; @@ -81,13 +97,13 @@ module tb_floo_rob; // Local Master // //////////////////// - id_t [NumDirections-1:0] xy_id; - assign xy_id[Eject] = '{x: 3'd1, y: 3'd1, port_id: 2'd0}; + id_t [floo_pkg::NumDirections-1:0] xy_id; + assign xy_id[floo_pkg::Eject] = '{x: 2'd1, y: 2'd1, port_id: 1'd0}; typedef struct packed { - int unsigned idx; - axi_in_addr_t start_addr; - axi_in_addr_t end_addr; + int unsigned idx; + axi_addr_t start_addr; + axi_addr_t end_addr; } node_addr_region_t; localparam int unsigned NumAddrRegions = 4; @@ -99,117 +115,153 @@ module tb_floo_rob; }; floo_axi_test_node #( - .AxiAddrWidth ( AxiInAddrWidth ), - .AxiDataWidth ( AxiInDataWidth ), - .AxiIdInWidth ( AxiInIdWidth ), - .AxiIdOutWidth ( AxiInIdWidth ), - .AxiUserWidth ( AxiInUserWidth ), - .mst_req_t ( axi_in_req_t ), - .mst_rsp_t ( axi_in_rsp_t ), - .slv_req_t ( axi_out_req_t ), - .slv_rsp_t ( axi_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .AxiMaxBurstLen ( 4 ), - .NumAddrRegions ( NumAddrRegions ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .NumReads ( NumReads ), - .NumWrites ( NumWrites ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .mst_req_t ( axi_in_req_t ), + .mst_rsp_t ( axi_in_rsp_t ), + .slv_req_t ( axi_out_req_t ), + .slv_rsp_t ( axi_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .AxiMaxBurstLen ( 4 ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( NumReads ), + .NumWrites ( NumWrites ) ) i_test_node_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .mst_port_req_o ( node_mst_req ), - .mst_port_rsp_i ( node_mst_rsp ), - .slv_port_req_i ( node_slv_req[Eject] ), - .slv_port_rsp_o ( node_slv_rsp[Eject] ), - .end_of_sim ( end_of_sim[0] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mst_port_req_o ( node_mst_req ), + .mst_port_rsp_i ( node_mst_rsp ), + .slv_port_req_i ( node_slv_req[floo_pkg::Eject] ), + .slv_port_rsp_o ( node_slv_rsp[floo_pkg::Eject] ), + .end_of_sim ( end_of_sim[0] ) + ); + + axi_dumper #( + .BusName ( "MasterAxi" ), + .LogAW ( 1'b0 ), + .LogAR ( 1'b0 ), + .LogW ( 1'b0 ), + .LogB ( 1'b0 ), + .LogR ( 1'b0 ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_rsp_t ) + ) i_axi_dumper ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( node_mst_req ), + .axi_resp_i ( node_mst_rsp ) ); floo_axi_chimney #( - .MaxTxns ( MaxTxns ), - .MaxTxnsPerId ( MaxTxnsPerId ), - .ReorderBufferSize ( ReorderBufferSize ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .ChimneyCfg ( RoBChimneyCfg ), // Needs RoB + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( floo_test_pkg::AtopSupport ), + .MaxAtomicTxns ( floo_test_pkg::MaxAtomicTxns ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .rob_idx_t ( rob_idx_t ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ) ) i_floo_axi_chimney ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .axi_in_req_i ( node_mst_req ), - .axi_in_rsp_o ( node_mst_rsp ), - .axi_out_req_o ( node_slv_req[Eject] ), - .axi_out_rsp_i ( node_slv_rsp[Eject] ), - .id_i ( xy_id[Eject] ), - .route_table_i ( '0 ), - .floo_req_o ( chimney_req_out[Eject] ), - .floo_rsp_o ( chimney_rsp_out[Eject] ), - .floo_req_i ( chimney_req_in[Eject] ), - .floo_rsp_i ( chimney_rsp_in[Eject] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_in_req_i ( node_mst_req ), + .axi_in_rsp_o ( node_mst_rsp ), + .axi_out_req_o ( node_slv_req[floo_pkg::Eject] ), + .axi_out_rsp_i ( node_slv_rsp[floo_pkg::Eject] ), + .id_i ( xy_id[floo_pkg::Eject] ), + .route_table_i ( '0 ), + .floo_req_o ( chimney_req_out[floo_pkg::Eject] ), + .floo_rsp_o ( chimney_rsp_out[floo_pkg::Eject] ), + .floo_req_i ( chimney_req_in[floo_pkg::Eject] ), + .floo_rsp_i ( chimney_rsp_in[floo_pkg::Eject] ) ); floo_router #( - .NumRoutes ( NumDirections ), + .NumRoutes ( floo_pkg::NumDirections ), .NumVirtChannels ( 1 ), - .NumPhysChannels ( 1 ), .flit_t ( floo_req_generic_flit_t ), - .ChannelFifoDepth ( 4 ), - .RouteAlgo ( XYRouting ), + .InFifoDepth ( 2 ), + .RouteAlgo ( floo_pkg::XYRouting ), .id_t ( id_t ) ) i_floo_req_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_enable_i ( 1'b0 ), - .xy_id_i ( xy_id[Eject] ), - .id_route_map_i ( '0 ), - .valid_i ( chimney_req_out_valid ), - .ready_o ( chimney_req_in_ready ), - .data_i ( chimney_req_out_chan ), - .valid_o ( chimney_req_in_valid ), - .ready_i ( chimney_req_out_ready ), - .data_o ( chimney_req_in_chan ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( xy_id[floo_pkg::Eject] ), + .id_route_map_i ( '0 ), + .valid_i ( chimney_req_out_valid ), + .ready_o ( chimney_req_in_ready ), + .data_i ( chimney_req_out_chan ), + .valid_o ( chimney_req_in_valid ), + .ready_i ( chimney_req_out_ready ), + .data_o ( chimney_req_in_chan ) ); floo_router #( - .NumRoutes ( NumDirections ), + .NumRoutes ( floo_pkg::NumDirections ), .NumVirtChannels ( 1 ), - .NumPhysChannels ( 1 ), .flit_t ( floo_rsp_generic_flit_t ), - .ChannelFifoDepth ( 4 ), - .RouteAlgo ( XYRouting ), + .InFifoDepth ( 2 ), + .RouteAlgo ( floo_pkg::XYRouting ), .id_t ( id_t ) ) i_floo_rsp_router ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_enable_i ( 1'b0 ), - .xy_id_i ( xy_id[Eject] ), - .id_route_map_i ( '0 ), - .valid_i ( chimney_rsp_out_valid ), - .ready_o ( chimney_rsp_in_ready ), - .data_i ( chimney_rsp_out_chan ), - .valid_o ( chimney_rsp_in_valid ), - .ready_i ( chimney_rsp_out_ready ), - .data_o ( chimney_rsp_in_chan ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( xy_id[floo_pkg::Eject] ), + .id_route_map_i ( '0 ), + .valid_i ( chimney_rsp_out_valid ), + .ready_o ( chimney_rsp_in_ready ), + .data_i ( chimney_rsp_out_chan ), + .valid_o ( chimney_rsp_in_valid ), + .ready_i ( chimney_rsp_out_ready ), + .data_o ( chimney_rsp_in_chan ) ); - localparam slave_type_e SlaveType[NumDirections-1] = '{ - FastSlave, FastSlave, SlowSlave, MixedSlave}; + localparam floo_test_pkg::slave_type_e SlaveType[floo_pkg::NumDirections-1] = '{ + floo_test_pkg::FastSlave, + floo_test_pkg::FastSlave, + floo_test_pkg::SlowSlave, + floo_test_pkg::MixedSlave + }; for (genvar i = North; i <= West; i++) begin : gen_slaves if (i == North) begin : gen_north - assign xy_id[i] = '{x: 3'd1, y: 3'd2, port_id: 2'd0}; + assign xy_id[i] = '{x: 2'd1, y: 2'd2, port_id: 1'd0}; end else if (i == South) begin : gen_south - assign xy_id[i] = '{x: 3'd1, y: 3'd0, port_id: 2'd0}; + assign xy_id[i] = '{x: 2'd1, y: 2'd0, port_id: 1'd0}; end else if (i == East) begin : gen_east - assign xy_id[i] = '{x: 3'd2, y: 3'd1, port_id: 2'd0}; + assign xy_id[i] = '{x: 2'd2, y: 2'd1, port_id: 1'd0}; end else if (i == West) begin : gen_west - assign xy_id[i] = '{x: 3'd0, y: 3'd1, port_id: 2'd0}; + assign xy_id[i] = '{x: 2'd0, y: 2'd1, port_id: 1'd0}; end floo_axi_chimney #( - .MaxTxns ( MaxTxns ), - .MaxTxnsPerId ( MaxTxnsPerId ), - .ReorderBufferSize ( ReorderBufferSize ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .ChimneyCfg ( floo_test_pkg::ChimneyCfg ), // Does not need RoB + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( floo_test_pkg::AtopSupport ), + .MaxAtomicTxns ( floo_test_pkg::MaxAtomicTxns ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .rob_idx_t ( rob_idx_t ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ) ) i_floo_axi_chimney ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -227,18 +279,31 @@ module tb_floo_rob; .floo_rsp_i ( chimney_rsp_in[i] ) ); + axi_dumper #( + .BusName ( $sformatf("Slave%0d", i)), + .LogAW ( 1'b0 ), + .LogAR ( 1'b0 ), + .LogW ( 1'b0 ), + .LogB ( 1'b0 ), + .LogR ( 1'b0 ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_rsp_t ) + ) i_axi_dumper ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( node_slv_req[i] ), + .axi_resp_i ( node_slv_rsp[i] ) + ); + floo_axi_rand_slave #( - .AxiAddrWidth ( AxiOutAddrWidth ), - .AxiDataWidth ( AxiOutDataWidth ), - .AxiIdWidth ( AxiOutIdWidth ), - .AxiUserWidth ( AxiOutUserWidth ), - .axi_req_t ( axi_out_req_t ), - .axi_rsp_t ( axi_out_rsp_t ), - .ApplTime ( ApplTime ), - .TestTime ( TestTime ), - .SlaveType ( SlaveType[i] ), - .DstStartAddr ( 32'h0000_0000 ), // TODO: make this configurable - .DstEndAddr ( 32'h0000_8000 ) + .AxiCfg ( floo_test_pkg::AxiCfg ), + .axi_req_t ( axi_out_req_t ), + .axi_rsp_t ( axi_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .SlaveType ( SlaveType[i] ), + .DstStartAddr ( 32'h0000_0000 ), // TODO: make this configurable + .DstEndAddr ( 32'h0000_8000 ) ) i_test_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -251,28 +316,28 @@ module tb_floo_rob; end axi_reorder_compare #( - .NumSlaves ( NumSlaves ), - .AxiIdWidth ( AxiInIdWidth ), - .NumAddrRegions ( NumAddrRegions ), - .addr_t ( axi_in_addr_t ), - .rule_t ( node_addr_region_t ), - .AddrRegions ( AddrRegions ), - .aw_chan_t ( axi_in_aw_chan_t ), - .w_chan_t ( axi_in_w_chan_t ), - .b_chan_t ( axi_in_b_chan_t ), - .ar_chan_t ( axi_in_ar_chan_t ), - .r_chan_t ( axi_in_r_chan_t ), - .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_rsp_t ), - .Verbose ( 1'b0 ) + .NumSlaves ( NumSlaves ), + .AxiIdWidth ( floo_test_pkg::AxiCfg.InIdWidth ), + .NumAddrRegions ( NumAddrRegions ), + .addr_t ( axi_addr_t ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .aw_chan_t ( axi_in_aw_chan_t ), + .w_chan_t ( axi_in_w_chan_t ), + .b_chan_t ( axi_in_b_chan_t ), + .ar_chan_t ( axi_in_ar_chan_t ), + .r_chan_t ( axi_in_r_chan_t ), + .req_t ( axi_in_req_t ), + .rsp_t ( axi_in_rsp_t ), + .Verbose ( 1'b0 ) ) i_axi_reorder_compare ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .mon_mst_req_i ( node_mst_req ), - .mon_mst_rsp_i ( node_mst_rsp ), - .mon_slv_req_i ( node_slv_req_id_mapped[West:North] ), - .mon_slv_rsp_i ( node_slv_rsp_id_mapped[West:North] ), - .end_of_sim_o ( end_of_sim[1] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mon_mst_req_i ( node_mst_req ), + .mon_mst_rsp_i ( node_mst_rsp ), + .mon_slv_req_i ( node_slv_req_id_mapped[West:North] ), + .mon_slv_rsp_i ( node_slv_rsp_id_mapped[West:North] ), + .end_of_sim_o ( end_of_sim[1] ) ); initial begin diff --git a/hw/tb/tb_floo_router.sv b/hw/tb/tb_floo_router.sv index 61ac20f2..18342f1d 100644 --- a/hw/tb/tb_floo_router.sv +++ b/hw/tb/tb_floo_router.sv @@ -16,7 +16,6 @@ module tb_floo_router; import floo_pkg::*; - import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -42,6 +41,12 @@ module tb_floo_router; localparam int unsigned FlitWidth = 123; localparam int unsigned MaxPacketLength = 32; + typedef logic [FlitWidth-1:0] payload_t; + typedef logic [IdWidth-1:0] id_t; + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, logic, logic) + `FLOO_TYPEDEF_GENERIC_FLIT_T(req, hdr_t, payload_t) + logic clk, rst_n; clk_rst_gen #( @@ -225,7 +230,7 @@ module tb_floo_router; .NumRoutes ( NumPorts ), .NumVirtChannels ( NumVirtChannels ), .flit_t ( floo_req_generic_flit_t ), - .ChannelFifoDepth( 4 ), + .InFifoDepth( 4 ), .RouteAlgo ( IdIsPort ), .IdWidth ( IdWidth ) ) i_dut ( diff --git a/hw/tb/tb_floo_vc_dma_mesh.sv b/hw/tb/tb_floo_vc_dma_mesh.sv index a12294f1..8a4e6ad2 100644 --- a/hw/tb/tb_floo_vc_dma_mesh.sv +++ b/hw/tb/tb_floo_vc_dma_mesh.sv @@ -4,13 +4,12 @@ // // Author: Tim Fischer +`include "axi/typedef.svh" `include "floo_noc/typedef.svh" -`include "common_cells/assertions.svh" module tb_floo_vc_dma_mesh; import floo_pkg::*; - import floo_vc_narrow_wide_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -20,29 +19,30 @@ module tb_floo_vc_dma_mesh; localparam int unsigned NumY = 4; localparam int unsigned NumMax = (NumX > NumY) ? NumX : NumY; + typedef logic[$clog2(NumX+2)-1:0] x_bits_t; + typedef logic[$clog2(NumY+2)-1:0] y_bits_t; + typedef logic [2:0] vc_id_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + `FLOO_TYPEDEF_VC_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic, vc_id_t) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in, + floo_test_pkg::AxiCfgN, floo_test_pkg::AxiCfgW, hdr_t) + `FLOO_TYPEDEF_VC_NW_LINK_ALL(vc_req, vc_rsp, vc_wide, req, rsp, wide, vc_id_t) + + function automatic chimney_cfg_t gen_cut_rsp_cfg(); + chimney_cfg_t cfg = floo_pkg::ChimneyDefaultCfg; + cfg.CutRsp = 1'b1; + return cfg; + endfunction + + localparam chimney_cfg_t ChimneyCfg = gen_cut_rsp_cfg(); + localparam int unsigned HBMLatency = 100; - localparam axi_narrow_in_addr_t HBMSize = 48'h10000; // 64KB - localparam axi_narrow_in_addr_t MemSize = HBMSize; - - if (RouteAlgo == XYRouting) begin : gen_asserts - `ASSERT_INIT(NotEnoughXBits, $clog2(NumX + 2) <= $bits(x_bits_t)) - `ASSERT_INIT(NotEnoughYBits, $clog2(NumY + 2) <= $bits(y_bits_t)) - `ASSERT_INIT(NotEnoughAddrOffset, $clog2(HBMSize) <= XYAddrOffsetX) - end else begin : gen_error - $fatal(1, "This testbench only supports XYRouting"); - end + localparam axi_narrow_addr_t HBMSize = 48'h10000; // 64KB + localparam axi_narrow_addr_t MemSize = HBMSize; - // Narrow Wide Chimney parameters - localparam bit CutAx = 1'b1; - localparam bit CutRsp = 1'b1; - localparam int unsigned NarrowMaxTxnsPerId = 4; - localparam int unsigned NarrowReorderBufferSize = 32'd256; - localparam int unsigned WideMaxTxnsPerId = 32; - localparam int unsigned WideReorderBufferSize = 32'd64; - localparam int unsigned NarrowMaxTxns = 32; - localparam int unsigned WideMaxTxns = 32; - - localparam int unsigned ChannelFifoDepth = 2; // VCDepth + localparam int unsigned ChannelFifoDepth = 2; localparam int unsigned WormholeVCDepth = 3; // >= ChannelFifoDepth localparam int unsigned FixedWormholeVC = 1; // send all Wormhole flits to same VC localparam int unsigned AllowVCOverflow = 1; // 1: FVADA, 0: fixed VC, direction based @@ -112,21 +112,21 @@ module tb_floo_vc_dma_mesh; //////////////////////////////// floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( AxiWideOutAddrWidth ), - .DataWidth ( AxiWideOutDataWidth ), - .UserWidth ( AxiWideOutUserWidth ), - .IdWidth ( AxiWideOutIdWidth ), - .axi_req_t ( axi_wide_out_req_t ), - .axi_rsp_t ( axi_wide_out_rsp_t ), - .aw_chan_t ( axi_wide_out_aw_chan_t ), - .w_chan_t ( axi_wide_out_w_chan_t ), - .b_chan_t ( axi_wide_out_b_chan_t ), - .ar_chan_t ( axi_wide_out_ar_chan_t ), - .r_chan_t ( axi_wide_out_r_chan_t ) + .TA ( ApplTime ), + .TT ( TestTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .AddrWidth ( floo_test_pkg::AxiCfgW.AddrWidth ), + .DataWidth ( floo_test_pkg::AxiCfgW.DataWidth ), + .UserWidth ( floo_test_pkg::AxiCfgW.UserWidth ), + .IdWidth ( floo_test_pkg::AxiCfgW.OutIdWidth ), + .axi_req_t ( axi_wide_out_req_t ), + .axi_rsp_t ( axi_wide_out_rsp_t ), + .aw_chan_t ( axi_wide_out_aw_chan_t ), + .w_chan_t ( axi_wide_out_w_chan_t ), + .b_chan_t ( axi_wide_out_b_chan_t ), + .ar_chan_t ( axi_wide_out_ar_chan_t ), + .r_chan_t ( axi_wide_out_r_chan_t ) ) i_floo_wide_hbm_model [West:North][NumMax-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -135,21 +135,21 @@ module tb_floo_vc_dma_mesh; ); floo_hbm_model #( - .TA ( ApplTime ), - .TT ( TestTime ), - .Latency ( HBMLatency ), - .NumChannels ( 1 ), - .AddrWidth ( AxiNarrowOutAddrWidth ), - .DataWidth ( AxiNarrowOutDataWidth ), - .UserWidth ( AxiNarrowOutUserWidth ), - .IdWidth ( AxiNarrowOutIdWidth ), - .axi_req_t ( axi_narrow_out_req_t ), - .axi_rsp_t ( axi_narrow_out_rsp_t ), - .aw_chan_t ( axi_narrow_out_aw_chan_t ), - .w_chan_t ( axi_narrow_out_w_chan_t ), - .b_chan_t ( axi_narrow_out_b_chan_t ), - .ar_chan_t ( axi_narrow_out_ar_chan_t ), - .r_chan_t ( axi_narrow_out_r_chan_t ) + .TA ( ApplTime ), + .TT ( TestTime ), + .Latency ( HBMLatency ), + .NumChannels ( 1 ), + .AddrWidth ( floo_test_pkg::AxiCfgN.AddrWidth ), + .DataWidth ( floo_test_pkg::AxiCfgN.DataWidth ), + .UserWidth ( floo_test_pkg::AxiCfgN.UserWidth ), + .IdWidth ( floo_test_pkg::AxiCfgN.OutIdWidth ), + .axi_req_t ( axi_narrow_out_req_t ), + .axi_rsp_t ( axi_narrow_out_rsp_t ), + .aw_chan_t ( axi_narrow_out_aw_chan_t ), + .w_chan_t ( axi_narrow_out_w_chan_t ), + .b_chan_t ( axi_narrow_out_b_chan_t ), + .ar_chan_t ( axi_narrow_out_ar_chan_t ), + .r_chan_t ( axi_narrow_out_r_chan_t ) ) i_floo_narrow_hbm_model [West:North][NumMax-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -212,22 +212,34 @@ module tb_floo_vc_dma_mesh; end floo_vc_narrow_wide_chimney #( - .NarrowMaxTxns ( NarrowMaxTxns ), - .WideMaxTxns ( WideMaxTxns ), - .NarrowReorderBufferSize ( NarrowReorderBufferSize ), - .WideReorderBufferSize ( WideReorderBufferSize ), - .CutAx ( CutAx ), - .CutRsp ( CutRsp ), - .NumRoutes ( int'(NumDirections) ), - .OutputDir ( route_direction_e'(i) ), - .NumVC (Only1VC? 1 : (i==North||i==South)? 2:4), - .InputFifoDepth ( WormholeVCDepth ), - .VCDepth ( ChannelFifoDepth ), - .CreditShortcut ( CreditShortcut ), - .AllowVCOverflow ( AllowVCOverflow ), - .FixedWormholeVC ( FixedWormholeVC ), - .WormholeVCId (i==East? 2: i==West? 1: 0), - .WormholeVCDepth ( WormholeVCDepth ) + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .ChimneyCfgN ( ChimneyCfg ), + .ChimneyCfgW ( ChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .OutputDir ( route_direction_e'(i) ), + .NumVC ( Only1VC? 1 : (i==North||i==South)? 2:4 ), + .InputFifoDepth ( WormholeVCDepth ), + .VCDepth ( ChannelFifoDepth ), + .CreditShortcut ( CreditShortcut ), + .AllowVCOverflow ( AllowVCOverflow ), + .FixedWormholeVC ( FixedWormholeVC ), + .WormholeVCId ( i==East? 2: i==West? 1: 0 ), + .WormholeVCDepth ( WormholeVCDepth ), + .hdr_t ( hdr_t ), + .id_t ( id_t ), + .vc_id_t ( vc_id_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_vc_req_t ( floo_vc_req_t ), + .floo_vc_rsp_t ( floo_vc_rsp_t ), + .floo_vc_wide_t ( floo_vc_wide_t ) ) i_hbm_chimney [NumChimneys-1:0] ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -269,26 +281,23 @@ module tb_floo_vc_dma_mesh; floo_vc_wide_t [NumDirections-1:0] wide_out, wide_in; localparam int unsigned Index = y * NumX + x+1; - localparam logic [AxiNarrowInAddrWidth-1:0] MemBaseAddr = - (x+1) << XYAddrOffsetX | (y+1) << XYAddrOffsetY; + localparam axi_narrow_addr_t MemBaseAddr = + (x+1) << floo_test_pkg::RouteCfg.XYAddrOffsetX | + (y+1) << floo_test_pkg::RouteCfg.XYAddrOffsetY; assign current_id = '{x: x+1, y: y+1, port_id: 0}; floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiNarrowInDataWidth ), - .AddrWidth ( AxiNarrowInAddrWidth ), - .UserWidth ( AxiNarrowInUserWidth ), - .AxiIdInWidth ( AxiNarrowOutIdWidth ), - .AxiIdOutWidth ( AxiNarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*NarrowMaxTxnsPerId ), - .axi_in_req_t ( axi_narrow_out_req_t ), - .axi_in_rsp_t ( axi_narrow_out_rsp_t ), - .axi_out_req_t ( axi_narrow_in_req_t ), - .axi_out_rsp_t ( axi_narrow_in_rsp_t ), - .JobId ( 100 + Index ) + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgN) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 100 + Index ) ) i_narrow_dma_node ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -300,21 +309,17 @@ module tb_floo_vc_dma_mesh; ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .DataWidth ( AxiWideInDataWidth ), - .AddrWidth ( AxiWideInAddrWidth ), - .UserWidth ( AxiWideInUserWidth ), - .AxiIdInWidth ( AxiWideOutIdWidth ), - .AxiIdOutWidth ( AxiWideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .NumAxInFlight ( 2*WideMaxTxnsPerId ), - .axi_in_req_t ( axi_wide_out_req_t ), - .axi_in_rsp_t ( axi_wide_out_rsp_t ), - .axi_out_req_t ( axi_wide_in_req_t ), - .axi_out_rsp_t ( axi_wide_in_rsp_t ), - .JobId ( Index ) + .TA ( ApplTime ), + .TT ( TestTime ), + .AxiCfg ( axi_cfg_swap_iw(floo_test_pkg::AxiCfgW) ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .NumAxInFlight ( 2*floo_test_pkg::ChimneyCfg.MaxTxnsPerId ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( Index ) ) i_wide_dma_node ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -326,10 +331,10 @@ module tb_floo_vc_dma_mesh; ); axi_bw_monitor #( - .req_t ( axi_narrow_in_req_t ), - .rsp_t ( axi_narrow_in_rsp_t ), - .AxiIdWidth ( AxiNarrowInIdWidth ), - .Name ( NarrowDmaName ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( floo_test_pkg::AxiCfgN.InIdWidth ), + .Name ( NarrowDmaName ) ) i_axi_narrow_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), @@ -341,10 +346,10 @@ module tb_floo_vc_dma_mesh; ); axi_bw_monitor #( - .req_t ( axi_wide_in_req_t ), - .rsp_t ( axi_wide_in_rsp_t ), - .AxiIdWidth ( AxiWideInIdWidth ), - .Name ( WideDmaName ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( floo_test_pkg::AxiCfgW.InIdWidth ), + .Name ( WideDmaName ) ) i_axi_wide_bw_monitor ( .clk_i ( clk ), .en_i ( rst_n ), @@ -356,22 +361,34 @@ module tb_floo_vc_dma_mesh; ); floo_vc_narrow_wide_chimney #( - .NarrowMaxTxns ( NarrowMaxTxns ), - .WideMaxTxns ( WideMaxTxns ), - .NarrowReorderBufferSize ( NarrowReorderBufferSize ), - .WideReorderBufferSize ( WideReorderBufferSize ), - .CutAx ( CutAx ), - .CutRsp ( CutRsp ), - .NumRoutes ( int'(NumDirections) ), - .OutputDir ( Eject ), - .InputFifoDepth ( WormholeVCDepth ), - .NumVC ( NumVCLocal ), - .VCDepth ( ChannelFifoDepth ), - .CreditShortcut ( CreditShortcut ), - .AllowVCOverflow ( AllowVCOverflow ), - .FixedWormholeVC ( FixedWormholeVC ), - .WormholeVCId ( 0 ), - .WormholeVCDepth ( WormholeVCDepth ) + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), + .ChimneyCfgN ( ChimneyCfg ), + .ChimneyCfgW ( ChimneyCfg ), + .RouteCfg ( floo_test_pkg::RouteCfg ), + .OutputDir ( Eject ), + .InputFifoDepth ( WormholeVCDepth ), + .NumVC ( NumVCLocal ), + .VCDepth ( ChannelFifoDepth ), + .CreditShortcut ( CreditShortcut ), + .AllowVCOverflow ( AllowVCOverflow ), + .FixedWormholeVC ( FixedWormholeVC ), + .WormholeVCId ( 0 ), + .WormholeVCDepth ( WormholeVCDepth ), + .hdr_t ( hdr_t ), + .id_t ( id_t ), + .vc_id_t ( vc_id_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_vc_req_t ( floo_vc_req_t ), + .floo_vc_rsp_t ( floo_vc_rsp_t ), + .floo_vc_wide_t ( floo_vc_wide_t ) ) i_dma_chimney ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -397,12 +414,16 @@ module tb_floo_vc_dma_mesh; ); floo_vc_narrow_wide_router #( + .AxiCfgN ( floo_test_pkg::AxiCfgN ), + .AxiCfgW ( floo_test_pkg::AxiCfgW ), .NumPorts ( int'(NumDirections) ), .NumVC ( Only1VC ? {1, 1, 1, 1, NumVCLocal} : {2, 4, 2, 4, NumVCLocal} ), - .RouteAlgo ( RouteAlgo ), + .RouteAlgo ( floo_test_pkg::RouteCfg.RouteAlgo ), .id_t ( id_t ), + .hdr_t ( hdr_t ), + .vc_id_t ( vc_id_t ), .NumVCToOut ( Only1VC ? {1, 1, 1, 1, 1} : {y==NumY-1 ? 1 : 2, x==NumX-1 ? 1 : 4, @@ -418,7 +439,10 @@ module tb_floo_vc_dma_mesh; .AllowOverflowFromDeeperVC (AllowOverflowFromDeeperVC), .WormholeVCId ( Only1VC? {0, 0, 0, 0, 0} : - {0, 1, 0, 2, 0} ) + {0, 1, 0, 2, 0} ), + .floo_vc_req_t ( floo_vc_req_t ), + .floo_vc_rsp_t ( floo_vc_rsp_t ), + .floo_vc_wide_t ( floo_vc_wide_t ) ) i_router ( .clk_i ( clk ), .rst_ni ( rst_n ), diff --git a/hw/tb/tb_floo_vc_router.sv b/hw/tb/tb_floo_vc_router.sv index e58871a3..82c2aeb1 100644 --- a/hw/tb/tb_floo_vc_router.sv +++ b/hw/tb/tb_floo_vc_router.sv @@ -8,14 +8,21 @@ module tb_floo_vc_router; import floo_pkg::*; - import floo_vc_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; localparam time TestTime = 8ns; + typedef logic [2:0] x_bits_t; + typedef logic [2:0] y_bits_t; + typedef logic [1:0] port_id_t; + typedef logic [2:0] vc_id_t; + typedef logic [63:0] payload_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, port_id_t) + `FLOO_TYPEDEF_VC_HDR_T(hdr_t, id_t, id_t, logic, logic, vc_id_t) + `FLOO_TYPEDEF_GENERIC_FLIT_T(req, hdr_t, payload_t) + localparam type flit_t = floo_req_generic_flit_t; - localparam type payload_t = floo_req_payload_t; localparam int NumVCWidth = 2; localparam int NumPorts = 5; localparam int Debug = 0; diff --git a/hw/tb/wave/tb_floo_dma_mesh.wave.tcl b/hw/tb/wave/tb_floo_dma_mesh.wave.tcl index eb942b2a..6d57341d 100644 --- a/hw/tb/wave/tb_floo_dma_mesh.wave.tcl +++ b/hw/tb/wave/tb_floo_dma_mesh.wave.tcl @@ -8,7 +8,7 @@ floo_wave_init set tb_name tb_floo_dma_mesh -set routers [find instances -bydu floo_narrow_wide_router -nodu] +set routers [find instances -bydu floo_nw_router -nodu] set num_y [regexp -all {x\[0\]} $routers] set num_x [regexp -all {y\[0\]} $routers] @@ -25,17 +25,17 @@ for {set y 0} {$y < $num_y} {incr y} { for {set y 0} {$y < $num_y} {incr y} { # East - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] 1 + floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] 1 # West - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[4]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] 1 + floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] 1 } for {set x 0} {$x < $num_x} {incr x} { # North - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] 1 + floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[0]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] 1 # South - floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] 1 + floo_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] 1 } floo_wave_style diff --git a/hw/tb/wave/tb_floo_rob.wave.tcl b/hw/tb/wave/tb_floo_rob.wave.tcl index 269001ce..945ab797 100644 --- a/hw/tb/wave/tb_floo_rob.wave.tcl +++ b/hw/tb/wave/tb_floo_rob.wave.tcl @@ -8,9 +8,8 @@ floo_wave_init floo_axi_chimney_wave tb_floo_rob/i_floo_axi_chimney [list MstChimney] -for {set i 1} {$i <= 4} {incr i} { - set id [expr $i - 1] - set groups [list SlvChimney${id}] +for {set i 0} {$i < 4} {incr i} { + set groups [list SlvChimney${i}] floo_axi_chimney_wave tb_floo_rob/gen_slaves[${i}]/i_floo_axi_chimney $groups 0 } diff --git a/hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl b/hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl new file mode 100644 index 00000000..4ac58083 --- /dev/null +++ b/hw/tb/wave/tb_floo_vc_dma_mesh.wave.tcl @@ -0,0 +1,41 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +source hw/tb/wave/wave.tcl + +floo_wave_init + +set tb_name tb_floo_vc_dma_mesh + +set routers [find instances -bydu floo_vc_narrow_wide_router -nodu] +set num_y [regexp -all {x\[0\]} $routers] +set num_x [regexp -all {y\[0\]} $routers] + +for {set y 0} {$y < $num_y} {incr y} { + for {set x 0} {$x < $num_x} {incr x} { + set groups [list Node X=${x} Y=${y}] + floo_vc_narrow_wide_chimney_wave $tb_name/gen_x[$x]/gen_y[$y]/i_dma_chimney [concat $groups [list Chimney]] + floo_router_wave $tb_name/gen_x[$x]/gen_y[$y]/i_router [concat $groups [list Router]] + + floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_narrow_bw_monitor/*in_flight_o $groups 1 + floo_add_wave $tb_name/gen_x[$x]/gen_y[$y]/i_axi_wide_bw_monitor/*in_flight_o $groups 1 + } +} + +for {set y 0} {$y < $num_y} {incr y} { + # East + floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[1]/i_hbm_chimney[$y] [list HBM East "Channel ${y}" Chimney] + # West + floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[3]/i_hbm_chimney[$y] [list HBM West "Channel ${y}" Chimney] + +} + +for {set x 0} {$x < $num_x} {incr x} { + # North + floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[0]/i_hbm_chimney[$x] [list HBM North "Channel ${x}" Chimney] + # South + floo_vc_narrow_wide_chimney_wave $tb_name/gen_hbm_chimneys[2]/i_hbm_chimney[$x] [list HBM South "Channel ${x}" Chimney] +} + +floo_wave_style diff --git a/hw/tb/wave/wave.tcl b/hw/tb/wave/wave.tcl index b343ab20..96066db0 100644 --- a/hw/tb/wave/wave.tcl +++ b/hw/tb/wave/wave.tcl @@ -147,6 +147,10 @@ proc floo_narrow_wide_chimney_wave {dut groups {expand 1}} { } } +proc floo_vc_narrow_wide_chimney_wave {dut groups} { + floo_add_wave $dut/* $groups +} + proc floo_router_wave {dut groups} { floo_add_wave $dut/* $groups } diff --git a/hw/test/floo_axi_rand_slave.sv b/hw/test/floo_axi_rand_slave.sv index 1746273f..bee2d0fb 100644 --- a/hw/test/floo_axi_rand_slave.sv +++ b/hw/test/floo_axi_rand_slave.sv @@ -8,25 +8,18 @@ `include "axi/typedef.svh" /// A AXI4 Bus Multi-Slave generating random AXI respones with configurable response time -module floo_axi_rand_slave - import floo_test_pkg::*; -#( - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdWidth = 0, - parameter int unsigned AxiUserWidth = 0, +module floo_axi_rand_slave #( + parameter floo_pkg::axi_cfg_t AxiCfg = '0, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic, - // Dependent parameter, DO NOT OVERWRITE! - parameter int unsigned AxiStrbWidth = AxiDataWidth/8, // TB Parameters parameter time ApplTime = 2ns, parameter time TestTime = 8ns, - parameter logic[AxiAddrWidth-1:0] DstStartAddr = '0, - parameter logic[AxiAddrWidth-1:0] DstEndAddr = '1, - parameter slave_type_e SlaveType = MixedSlave, + parameter logic[AxiCfg.AddrWidth-1:0] DstStartAddr = '0, + parameter logic[AxiCfg.AddrWidth-1:0] DstEndAddr = '1, + parameter floo_test_pkg::slave_type_e SlaveType = floo_test_pkg::MixedSlave, parameter int unsigned NumSlaves = 4, - localparam logic[AxiAddrWidth-1:0] SlvAddrSpace = (DstEndAddr - DstStartAddr) / NumSlaves + localparam logic[AxiCfg.AddrWidth-1:0] SlvAddrSpace = (DstEndAddr - DstStartAddr) / NumSlaves ) ( input logic clk_i, input logic rst_ni, @@ -38,25 +31,25 @@ module floo_axi_rand_slave output axi_rsp_t [NumSlaves-1:0] mon_mst_port_rsp_o ); - typedef logic [AxiAddrWidth-1:0] addr_t; - typedef logic [AxiDataWidth-1:0] data_t; - typedef logic [AxiStrbWidth-1:0] strb_t; - typedef logic [AxiIdWidth-1:0] id_t; - typedef logic [AxiUserWidth-1:0] user_t; + typedef logic [AxiCfg.AddrWidth-1:0] addr_t; + typedef logic [AxiCfg.DataWidth-1:0] data_t; + typedef logic [AxiCfg.DataWidth/8-1:0] strb_t; + typedef logic [AxiCfg.OutIdWidth-1:0] id_t; + typedef logic [AxiCfg.UserWidth-1:0] user_t; `AXI_TYPEDEF_ALL(axi_xbar, addr_t, id_t, data_t, strb_t, user_t) AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ) + .AXI_ADDR_WIDTH ( AxiCfg.AddrWidth ), + .AXI_DATA_WIDTH ( AxiCfg.DataWidth ), + .AXI_ID_WIDTH ( AxiCfg.OutIdWidth ), + .AXI_USER_WIDTH ( AxiCfg.UserWidth ) ) slave_dv [NumSlaves] (clk_i); typedef struct packed { logic [31:0] idx; - logic [AxiAddrWidth-1:0] start_addr; - logic [AxiAddrWidth-1:0] end_addr; + logic [AxiCfg.AddrWidth-1:0] start_addr; + logic [AxiCfg.AddrWidth-1:0] end_addr; } xbar_rule_t; xbar_rule_t [NumSlaves-1:0] XbarAddrMap; @@ -76,11 +69,11 @@ module floo_axi_rand_slave FallThrough: 1, LatencyMode: axi_pkg::CUT_ALL_PORTS, PipelineStages: 0, - AxiIdWidthSlvPorts: AxiIdWidth, - AxiIdUsedSlvPorts: AxiIdWidth, + AxiIdWidthSlvPorts: AxiCfg.OutIdWidth, + AxiIdUsedSlvPorts: AxiCfg.OutIdWidth, UniqueIds: 0, - AxiAddrWidth: AxiAddrWidth, - AxiDataWidth: AxiDataWidth, + AxiAddrWidth: AxiCfg.AddrWidth, + AxiDataWidth: AxiCfg.DataWidth, NoAddrRules: NumSlaves }; @@ -90,34 +83,34 @@ module floo_axi_rand_slave axi_xbar_resp_t [NumSlaves-1:0] xbar_out_rsp; axi_xbar #( - .Cfg (XbarCfg), - .Connectivity ('1), - .ATOPs (0), - .slv_aw_chan_t(axi_xbar_aw_chan_t), - .mst_aw_chan_t(axi_xbar_aw_chan_t), - .w_chan_t (axi_xbar_w_chan_t ), - .slv_b_chan_t (axi_xbar_b_chan_t ), - .mst_b_chan_t (axi_xbar_b_chan_t ), - .slv_ar_chan_t(axi_xbar_ar_chan_t), - .mst_ar_chan_t(axi_xbar_ar_chan_t), - .slv_r_chan_t (axi_xbar_r_chan_t ), - .mst_r_chan_t (axi_xbar_r_chan_t ), - .slv_req_t (axi_xbar_req_t ), - .slv_resp_t (axi_xbar_resp_t ), - .mst_req_t (axi_xbar_req_t ), - .mst_resp_t (axi_xbar_resp_t ), - .rule_t (xbar_rule_t) + .Cfg ( XbarCfg ), + .Connectivity ( '1 ), + .ATOPs ( 0 ), + .slv_aw_chan_t ( axi_xbar_aw_chan_t ), + .mst_aw_chan_t ( axi_xbar_aw_chan_t ), + .w_chan_t ( axi_xbar_w_chan_t ), + .slv_b_chan_t ( axi_xbar_b_chan_t ), + .mst_b_chan_t ( axi_xbar_b_chan_t ), + .slv_ar_chan_t ( axi_xbar_ar_chan_t ), + .mst_ar_chan_t ( axi_xbar_ar_chan_t ), + .slv_r_chan_t ( axi_xbar_r_chan_t ), + .mst_r_chan_t ( axi_xbar_r_chan_t ), + .slv_req_t ( axi_xbar_req_t ), + .slv_resp_t ( axi_xbar_resp_t ), + .mst_req_t ( axi_xbar_req_t ), + .mst_resp_t ( axi_xbar_resp_t ), + .rule_t ( xbar_rule_t ) ) i_xbar ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .test_i (1'b0), - .slv_ports_req_i (xbar_in_req), - .slv_ports_resp_o (xbar_in_rsp), - .mst_ports_req_o (xbar_out_req), - .mst_ports_resp_i (xbar_out_rsp), - .addr_map_i (XbarAddrMap), - .en_default_mst_port_i('1), - .default_mst_port_i ('0) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( 1'b0 ), + .slv_ports_req_i ( xbar_in_req ), + .slv_ports_resp_o ( xbar_in_rsp ), + .mst_ports_req_o ( xbar_out_req ), + .mst_ports_resp_i ( xbar_out_rsp ), + .addr_map_i ( XbarAddrMap ), + .en_default_mst_port_i ( '1 ), + .default_mst_port_i ( '0 ) ); assign xbar_in_req = slv_port_req_i; @@ -132,24 +125,24 @@ module floo_axi_rand_slave typedef axi_test::axi_rand_slave #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdWidth ), - .UW ( AxiUserWidth ), + .AW ( AxiCfg.AddrWidth ), + .DW ( AxiCfg.DataWidth ), + .IW ( AxiCfg.OutIdWidth ), + .UW ( AxiCfg.UserWidth ), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) + .TA ( ApplTime ), + .TT ( TestTime ) ) axi_rand_slave_t; typedef axi_test::axi_rand_slave #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdWidth ), - .UW ( AxiUserWidth ), + .AW ( AxiCfg.AddrWidth ), + .DW ( AxiCfg.DataWidth ), + .IW ( AxiCfg.OutIdWidth ), + .UW ( AxiCfg.UserWidth ), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), + .TA ( ApplTime ), + .TT ( TestTime ), // Responsiveness .AX_MIN_WAIT_CYCLES (0), .AX_MAX_WAIT_CYCLES (5), @@ -161,13 +154,13 @@ module floo_axi_rand_slave typedef axi_test::axi_rand_slave #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdWidth ), - .UW ( AxiUserWidth ), + .AW ( AxiCfg.AddrWidth ), + .DW ( AxiCfg.DataWidth ), + .IW ( AxiCfg.OutIdWidth ), + .UW ( AxiCfg.UserWidth ), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), + .TA ( ApplTime ), + .TT ( TestTime ), // Responsiveness .AX_MIN_WAIT_CYCLES (50), .AX_MAX_WAIT_CYCLES (100), @@ -181,7 +174,7 @@ module floo_axi_rand_slave axi_rand_slow_slave_t axi_rand_slow_slave[NumSlaves]; axi_rand_fast_slave_t axi_rand_fast_slave[NumSlaves]; - if (SlaveType == SlowSlave) begin : gen_slow_slaves + if (SlaveType == floo_test_pkg::SlowSlave) begin : gen_slow_slaves for (genvar i = 0; i < NumSlaves; i++) begin : gen_slow_slaves initial begin axi_rand_slow_slave[i] = new( slave_dv[i] ); @@ -190,7 +183,7 @@ module floo_axi_rand_slave axi_rand_slow_slave[i].run(); end end - end else if (SlaveType == FastSlave) begin : gen_fast_slaves + end else if (SlaveType == floo_test_pkg::FastSlave) begin : gen_fast_slaves for (genvar i = 0; i < NumSlaves; i++) begin : gen_fast_slaves initial begin axi_rand_fast_slave[i] = new( slave_dv[i] ); @@ -199,7 +192,7 @@ module floo_axi_rand_slave axi_rand_fast_slave[i].run(); end end - end else if (SlaveType == MixedSlave) begin : gen_mixed_slaves + end else if (SlaveType == floo_test_pkg::MixedSlave) begin : gen_mixed_slaves for (genvar i = 0; i < NumSlaves; i++) begin : gen_mixed_slaves if (i % 2 == 0) begin : gen_slow_slaves initial begin diff --git a/hw/test/floo_axi_test_node.sv b/hw/test/floo_axi_test_node.sv index 72adf292..200b6df4 100644 --- a/hw/test/floo_axi_test_node.sv +++ b/hw/test/floo_axi_test_node.sv @@ -8,23 +8,17 @@ /// A AXI4 Bus Master-Slave Node for generating random AXI transactions module floo_axi_test_node #( - parameter int unsigned AxiAddrWidth = 0, - parameter int unsigned AxiDataWidth = 0, - parameter int unsigned AxiIdInWidth = 0, - parameter int unsigned AxiIdOutWidth = 0, - parameter int unsigned AxiUserWidth = 0, + parameter floo_pkg::axi_cfg_t AxiCfg = '{default:0}, parameter type mst_req_t = logic, parameter type mst_rsp_t = logic, parameter type slv_req_t = logic, parameter type slv_rsp_t = logic, - // Dependent parameter, DO NOT OVERWRITE! - parameter int unsigned AxiStrbWidth = AxiDataWidth/8, // TB Parameters parameter time ApplTime = 2ns, parameter time TestTime = 8ns, parameter bit Atops = 1'b0, parameter int unsigned AxiMaxBurstLen = 128, - parameter int unsigned NumAddrRegions = 1, + parameter int unsigned NumAddrRegions = 0, parameter type rule_t = logic, parameter rule_t [NumAddrRegions-1:0] AddrRegions = '0, parameter int unsigned NumReads = 0, @@ -41,11 +35,12 @@ module floo_axi_test_node #( output logic end_of_sim ); + AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdOutWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ) + .AXI_ADDR_WIDTH ( AxiCfg.AddrWidth ), + .AXI_DATA_WIDTH ( AxiCfg.DataWidth ), + .AXI_ID_WIDTH ( AxiCfg.OutIdWidth ), + .AXI_USER_WIDTH ( AxiCfg.UserWidth ) ) master_dv (clk_i); `AXI_ASSIGN_TO_REQ(mst_port_req_o, master_dv) @@ -53,10 +48,10 @@ module floo_axi_test_node #( typedef axi_test::axi_rand_master #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdOutWidth ), - .UW ( AxiUserWidth ), + .AW ( AxiCfg.AddrWidth ), + .DW ( AxiCfg.DataWidth ), + .IW ( AxiCfg.OutIdWidth ), + .UW ( AxiCfg.UserWidth ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ), @@ -77,10 +72,10 @@ module floo_axi_test_node #( ) axi_rand_master_t; AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdOutWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ) + .AXI_ADDR_WIDTH ( AxiCfg.AddrWidth ), + .AXI_DATA_WIDTH ( AxiCfg.DataWidth ), + .AXI_ID_WIDTH ( AxiCfg.OutIdWidth ), + .AXI_USER_WIDTH ( AxiCfg.UserWidth ) ) slave_dv (clk_i); `AXI_ASSIGN_FROM_REQ(slave_dv, slv_port_req_i) @@ -88,10 +83,10 @@ module floo_axi_test_node #( typedef axi_test::axi_rand_slave #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdOutWidth ), - .UW ( AxiUserWidth ), + .AW ( AxiCfg.AddrWidth ), + .DW ( AxiCfg.DataWidth ), + .IW ( AxiCfg.OutIdWidth ), + .UW ( AxiCfg.UserWidth ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) diff --git a/hw/test/floo_dma_test_node.sv b/hw/test/floo_dma_test_node.sv index 598f4447..39dc7f66 100644 --- a/hw/test/floo_dma_test_node.sv +++ b/hw/test/floo_dma_test_node.sv @@ -15,12 +15,7 @@ module floo_dma_test_node #( parameter time TT = 9ns, parameter int unsigned BufferDepth = 16, parameter int unsigned NumAxInFlight = 16, - parameter int unsigned DataWidth = 32, - parameter int unsigned AddrWidth = 32, - parameter int unsigned UserWidth = 1, - parameter int unsigned AxiIdWidth = 2, - parameter int unsigned AxiIdInWidth = AxiIdWidth, - parameter int unsigned AxiIdOutWidth = AxiIdWidth, + parameter floo_pkg::axi_cfg_t AxiCfg = '{default:0}, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic, parameter type axi_in_req_t = axi_req_t, @@ -29,8 +24,8 @@ module floo_dma_test_node #( parameter type axi_out_rsp_t = axi_rsp_t, parameter int unsigned TFLenWidth = 32, parameter int unsigned MemSysDepth = 0, - parameter logic [AddrWidth-1:0] MemBaseAddr = 32'h0, - parameter logic [AddrWidth-1:0] MemSize = 32'h10000, + parameter logic [AxiCfg.AddrWidth-1:0] MemBaseAddr = 32'h0, + parameter logic [AxiCfg.AddrWidth-1:0] MemSize = 32'h10000, parameter bit MaskInvalidData = 1, parameter bit RAWCouplingAvail = 1, parameter bit HardwareLegalizer = 1, @@ -56,7 +51,7 @@ module floo_dma_test_node #( localparam bit PrintFifoInfo = 1'b0; // dependent parameters - localparam int unsigned StrbWidth = DataWidth / 8; + localparam int unsigned StrbWidth = AxiCfg.DataWidth / 8; localparam int unsigned OffsetWidth = $clog2(StrbWidth); // parse error handling caps @@ -67,12 +62,12 @@ module floo_dma_test_node #( typedef logic [7:0] byte_t; // dependent typed - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; + typedef logic [AxiCfg.AddrWidth-1:0] addr_t; + typedef logic [AxiCfg.DataWidth-1:0] data_t; typedef logic [StrbWidth-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - typedef logic [AxiIdInWidth-1:0] id_in_t; - typedef logic [AxiIdOutWidth-1:0] id_out_t; + typedef logic [AxiCfg.UserWidth-1:0] user_t; + typedef logic [AxiCfg.InIdWidth-1:0] id_in_t; + typedef logic [AxiCfg.OutIdWidth-1:0] id_out_t; typedef logic [OffsetWidth-1:0] offset_t; typedef logic [TFLenWidth-1:0] tf_len_t; @@ -134,8 +129,8 @@ module floo_dma_test_node #( typedef struct packed { logic [31:0] idx; - logic [AddrWidth-1:0] start_addr; - logic [AddrWidth-1:0] end_addr; + logic [AxiCfg.AddrWidth-1:0] start_addr; + logic [AxiCfg.AddrWidth-1:0] end_addr; } xbar_rule_t; xbar_rule_t [0:0] XbarAddrMap; @@ -150,11 +145,11 @@ module floo_dma_test_node #( MaxMstTrans: 128, FallThrough: 1, LatencyMode: axi_pkg::CUT_ALL_PORTS, - AxiIdWidthSlvPorts: AxiIdOutWidth, - AxiIdUsedSlvPorts: AxiIdOutWidth, + AxiIdWidthSlvPorts: AxiCfg.OutIdWidth, + AxiIdUsedSlvPorts: AxiCfg.OutIdWidth, UniqueIds: 0, - AxiAddrWidth: AddrWidth, - AxiDataWidth: DataWidth, + AxiAddrWidth: AxiCfg.AddrWidth, + AxiDataWidth: AxiCfg.DataWidth, NoAddrRules: 1, PipelineStages: 0 }; @@ -163,10 +158,10 @@ module floo_dma_test_node #( // DMA //-------------------------------------- idma_backend_rw_axi #( - .DataWidth ( DataWidth ), - .AddrWidth ( AddrWidth ), - .AxiIdWidth ( AxiIdOutWidth ), - .UserWidth ( UserWidth ), + .DataWidth ( AxiCfg.DataWidth ), + .AddrWidth ( AxiCfg.AddrWidth ), + .AxiIdWidth ( AxiCfg.OutIdWidth ), + .UserWidth ( AxiCfg.UserWidth ), .TFLenWidth ( TFLenWidth ), .MaskInvalidData ( MaskInvalidData ), .BufferDepth ( BufferDepth ), @@ -252,11 +247,7 @@ module floo_dma_test_node #( ); floo_axi_rand_slave #( - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( DataWidth ), - .AxiIdWidth ( AxiIdOutWidth ), - .AxiUserWidth ( UserWidth ), - .AxiStrbWidth ( StrbWidth ), + .AxiCfg ( AxiCfg ), .ApplTime ( TA ), .TestTime ( TT ), .SlaveType ( floo_test_pkg::FastSlave ), @@ -273,17 +264,13 @@ module floo_dma_test_node #( ); floo_axi_rand_slave #( - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( DataWidth ), - .AxiIdWidth ( AxiIdInWidth ), - .AxiUserWidth ( UserWidth ), - .AxiStrbWidth ( StrbWidth ), - .ApplTime ( TA ), - .TestTime ( TT ), - .SlaveType ( floo_test_pkg::FastSlave ), - .NumSlaves ( 1 ), - .axi_req_t ( axi_in_req_t ), - .axi_rsp_t ( axi_in_rsp_t ) + .AxiCfg ( floo_pkg::axi_cfg_swap_iw(AxiCfg) ), + .ApplTime ( TA ), + .TestTime ( TT ), + .SlaveType ( floo_test_pkg::FastSlave ), + .NumSlaves ( 1 ), + .axi_req_t ( axi_in_req_t ), + .axi_rsp_t ( axi_in_rsp_t ) ) i_sink_in_mem ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -305,22 +292,22 @@ module floo_dma_test_node #( //-------------------------------------- // virtual interface definition IDMA_DV #( - .DataWidth ( DataWidth ), - .AddrWidth ( AddrWidth ), - .UserWidth ( UserWidth ), - .AxiIdWidth ( AxiIdOutWidth ), - .TFLenWidth ( TFLenWidth ) + .DataWidth ( AxiCfg.DataWidth ), + .AddrWidth ( AxiCfg.AddrWidth ), + .UserWidth ( AxiCfg.UserWidth ), + .AxiIdWidth ( AxiCfg.OutIdWidth ), + .TFLenWidth ( TFLenWidth ) ) idma_dv (clk_i); // DMA driver type typedef idma_test::idma_driver #( - .DataWidth ( DataWidth ), - .AddrWidth ( AddrWidth ), - .UserWidth ( UserWidth ), - .AxiIdWidth ( AxiIdOutWidth ), - .TFLenWidth ( TFLenWidth ), - .TA ( TA ), - .TT ( TT ) + .DataWidth ( AxiCfg.DataWidth ), + .AddrWidth ( AxiCfg.AddrWidth ), + .UserWidth ( AxiCfg.UserWidth ), + .AxiIdWidth ( AxiCfg.OutIdWidth ), + .TFLenWidth ( TFLenWidth ), + .TA ( TA ), + .TT ( TT ) ) drv_t; // instantiation of the driver @@ -343,7 +330,7 @@ module floo_dma_test_node #( //-------------------------------------- // job type definition typedef idma_test::idma_job #( - .AddrWidth ( AddrWidth ) + .AddrWidth ( AxiCfg.AddrWidth ) ) tb_dma_job_t; // request and response queues @@ -403,7 +390,7 @@ module floo_dma_test_node #( // pop front to get a job automatic tb_dma_job_t now = req_jobs.pop_front(); // print job to terminal - if (EnableDebug) $display("[DMA%0d]%s", JobId + 1, now.pprint()); + if (EnableDebug) $display("[DMA%0d]%s", JobId, now.pprint()); // launch DUT drv.launch_tf( now.length, diff --git a/hw/test/floo_test_pkg.sv b/hw/test/floo_test_pkg.sv index 11138d16..3fcec1d7 100644 --- a/hw/test/floo_test_pkg.sv +++ b/hw/test/floo_test_pkg.sv @@ -8,8 +8,6 @@ package floo_test_pkg; - import floo_pkg::*; - typedef enum { FastSlave, SlowSlave, @@ -25,20 +23,49 @@ package floo_test_pkg; localparam int unsigned ChannelFifoDepth = 2; localparam int unsigned OutputFifoDepth = 2; - // Chimney parameters - localparam bit CutAx = 1'b1; - localparam bit CutRsp = 1'b0; - localparam int unsigned MaxTxnsPerId = 16; - localparam rob_type_e RoBType = NormalRoB; - localparam int unsigned ReorderBufferSize = 32'd64; - - // Narrow Wide Chimney parameters - localparam bit NarrowRoBSimple = 1'b1; - localparam int unsigned NarrowMaxTxnsPerId = 4; - localparam rob_type_e NarrowRoBType = NoRoB; - localparam int unsigned NarrowReorderBufferSize = 32'd256; - localparam int unsigned WideMaxTxnsPerId = 32; - localparam rob_type_e WideRoBType = NoRoB; - localparam int unsigned WideReorderBufferSize = 32'd128; + // Default route config for testing + localparam floo_pkg::route_cfg_t RouteCfg = '{ + RouteAlgo: floo_pkg::XYRouting, + UseIdTable: 0, + XYAddrOffsetX: 16, + XYAddrOffsetY: 20, + IdAddrOffset: 0, + NumAddrRules: 0, + SamNumRules: 0, + NumRoutes: 0 + }; + + // Common chimney parameters + localparam bit AtopSupport = 1'b1; + localparam int unsigned MaxAtomicTxns = 4; + + // Axi chimney parameters + localparam floo_pkg::axi_cfg_t AxiCfg = '{ + AddrWidth: 32, + DataWidth: 64, + UserWidth: 1, + InIdWidth: 3, + OutIdWidth: 3 + }; + + localparam floo_pkg::axi_cfg_t AxiCfgN = '{ + AddrWidth: 48, + DataWidth: 64, + UserWidth: 5, + InIdWidth: 4, + OutIdWidth: 2 + }; + + // AXI nw_chimney parameters + localparam floo_pkg::axi_cfg_t AxiCfgW = '{ + AddrWidth: 48, + DataWidth: 512, + UserWidth: 1, + InIdWidth: 3, + OutIdWidth: 1 + }; + + // Default chimney config for testing + localparam floo_pkg::chimney_cfg_t ChimneyCfg = floo_pkg::ChimneyDefaultCfg; endpackage diff --git a/util/gen_jobs.py b/util/gen_jobs.py index 3d8c628e..11567264 100755 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -13,6 +13,8 @@ MEM_SIZE = 2**16 NUM_X = 4 NUM_Y = 4 +XY_ADDR_OFFSET_X = 16 +XY_ADDR_OFFSET_Y = 20 data_widths = {"wide": 512, "narrow": 64} @@ -25,7 +27,7 @@ def clog2(x: int): def get_xy_base_addr(x: int, y: int): """Get the address of a tile in the mesh.""" assert x <= NUM_X+1 and y <= NUM_Y+1 - return (x + 2 ** clog2(NUM_X + 2) * y) * MEM_SIZE + return (x << XY_ADDR_OFFSET_X) + (y << XY_ADDR_OFFSET_Y) def gen_job_str(