From 7a80050f37d36344496e440c45d6e79151121ea2 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Fri, 31 May 2024 17:01:13 +0200 Subject: [PATCH] hw: `floo_input_port` Clean up --- hw/floo_vc_router.sv | 61 +++++------ hw/tb/tb_floo_vc_router.sv | 4 +- hw/vc_router_util/floo_input_port.sv | 150 ++++++++++++++------------- 3 files changed, 105 insertions(+), 110 deletions(-) diff --git a/hw/floo_vc_router.sv b/hw/floo_vc_router.sv index 0eac46c9..1c30aeec 100644 --- a/hw/floo_vc_router.sv +++ b/hw/floo_vc_router.sv @@ -38,9 +38,7 @@ module floo_vc_router import floo_pkg::*; #( parameter int SingleStage = 0, // 0: standard 2 stage, 1: single stage parameter type flit_t = logic, parameter type hdr_t = logic, - parameter int HdrLength = $bits(hdr_t), - parameter int DataLength = $bits(flit_t) - HdrLength, - parameter type flit_payload_t = logic[DataLength-1:0], + parameter type payload_t = logic, // Route Algorithm stuff parameter route_algo_e RouteAlgo = XYRouting, @@ -93,7 +91,7 @@ Structure: // These arrays are too large: in these dimensions where there are fewer vc, the highest indexes are never accessed, so the synthesizer should remove them logic [NumPorts-1:0][NumVCMax-1:0] vc_ctrl_head_v; hdr_t [NumPorts-1:0][NumVCMax-1:0] vc_ctrl_head; -flit_payload_t [NumPorts-1:0][NumVCMax-1:0] vc_data_head; +payload_t [NumPorts-1:0][NumVCMax-1:0] vc_data_head; logic [NumPorts-1:0] read_enable_sa_stage; logic [NumPorts-1:0][NumVCMax-1:0] read_vc_id_oh_sa_stage; @@ -150,39 +148,32 @@ logic [NumPorts-1:0][NumPorts-1:0] wormhole_sa_global_input_dir // ============= for (genvar in_port = 0; in_port < NumPorts; in_port++) begin : gen_input_ports - floo_input_port #( - .flit_t (flit_t), - .flit_payload_t (flit_payload_t), - .hdr_t (hdr_t), - .NumVC (NumVC[in_port]), - .NumVCWidth (NumVCWidth), - .VCDepth (VCDepth), - .DeeperVCId (WormholeVCId[in_port >= Eject ? in_port : (in_port+2) % 4]), - .DeeperVCDepth (WormholeVCDepth) - ) i_input_port ( - // input from other router or local port - .credit_v_o (credit_v_o [in_port]), - .credit_id_o (credit_id_o [in_port]), - .data_v_i (data_v_i [in_port]), - .data_i (data_i [in_port]), - - // output head flit ctrl info to SA & RC unit - .vc_ctrl_head_v_o (vc_ctrl_head_v [in_port][NumVC[in_port]-1:0]), - .vc_ctrl_head_o (vc_ctrl_head [in_port][NumVC[in_port]-1:0]), - - // output data to switch traversal - .vc_data_head_o (vc_data_head [in_port][NumVC[in_port]-1:0]), - // pop flit ctrl fifo (comes from SA stage) - .read_enable_sa_stage_i (read_enable_sa_stage [in_port]), - .read_vc_id_oh_sa_stage_i (sa_local_vc_id_oh [in_port][NumVC[in_port]-1:0]), - - // pop flit data fifo (comes from ST stage) - .read_enable_st_stage_i (read_enable_st_stage [in_port]), - .read_vc_id_oh_st_stage_i (read_vc_id_oh_st_stage[in_port][NumVC[in_port]-1:0]), + localparam int unsigned DeeperVCId = WormholeVCId[in_port >= Eject ? in_port : (in_port+2) % 4]; + floo_input_port #( + .flit_t ( flit_t ), + .payload_t ( payload_t ), + .hdr_t ( hdr_t ), + .NumVC ( NumVC[in_port] ), + .VCIdxWidth ( NumVCWidth ), + .VCDepth ( VCDepth ), + .DeeperVCId ( DeeperVCId ), + .DeeperVCDepth ( WormholeVCDepth ) + ) i_input_port ( .clk_i, - .rst_ni + .rst_ni, + .credit_valid_o ( credit_v_o[in_port] ), + .credit_id_o ( credit_id_o[in_port] ), + .data_valid_i ( data_v_i[in_port] ), + .data_i ( data_i[in_port] ), + .vc_hdr_valid_o ( vc_ctrl_head_v[in_port][NumVC[in_port]-1:0] ), + .vc_hdr_o ( vc_ctrl_head[in_port][NumVC[in_port]-1:0] ), + .vc_data_o ( vc_data_head[in_port][NumVC[in_port]-1:0] ), + .read_enable_sa_stage_i ( read_enable_sa_stage[in_port] ), + .read_vc_id_oh_sa_stage_i ( sa_local_vc_id_oh[in_port][NumVC[in_port]-1:0] ), + .read_enable_st_stage_i ( read_enable_st_stage[in_port] ), + .read_vc_id_oh_st_stage_i ( read_vc_id_oh_st_stage[in_port][NumVC[in_port]-1:0] ) ); end @@ -558,7 +549,7 @@ floo_vc_router_switch #( .NumVC (NumVC), .NumVCMax (NumVCMax), .flit_t (flit_t), - .flit_payload_t (flit_payload_t), + .flit_payload_t (payload_t), .hdr_t (hdr_t), .RouteAlgo (RouteAlgo) ) i_floo_vc_router_switch ( diff --git a/hw/tb/tb_floo_vc_router.sv b/hw/tb/tb_floo_vc_router.sv index 80fd56e9..4d6faba6 100644 --- a/hw/tb/tb_floo_vc_router.sv +++ b/hw/tb/tb_floo_vc_router.sv @@ -17,7 +17,7 @@ localparam time TestTime = 8ns; localparam type flit_t = floo_req_generic_flit_t; localparam int HdrLength = $bits(hdr_t); localparam int DataLength = $bits(flit_t) - HdrLength; -localparam type flit_payload_t = logic[DataLength-1:0]; +localparam type payload_t = logic[DataLength-1:0]; localparam int NumVCWidth = 2; localparam int NumPorts = 5; localparam int Debug = 0; @@ -72,7 +72,7 @@ floo_vc_router #( .RouteAlgo (XYRouting), .flit_t (flit_t), .hdr_t (hdr_t), - .flit_payload_t (flit_payload_t), + .payload_t (payload_t), .id_t (id_t), .FixedWormholeVC (0), //without special features .UpdateRRArbIfNotSent(0), //without special features diff --git a/hw/vc_router_util/floo_input_port.sv b/hw/vc_router_util/floo_input_port.sv index 01d11397..bb075453 100644 --- a/hw/vc_router_util/floo_input_port.sv +++ b/hw/vc_router_util/floo_input_port.sv @@ -4,110 +4,114 @@ // // Lukas Berner -`include "common_cells/assertions.svh" - +/// Accepts flits from the input port and stores them in a FIFO. module floo_input_port #( - parameter type flit_t = logic, - parameter type hdr_t = logic, - parameter int HdrLength = $bits(hdr_t), - parameter int DataLength = $bits(flit_t) - HdrLength, - parameter type flit_payload_t = logic[DataLength-1:0], - parameter int NumVC = 4, - parameter int NumVCWidth = 2, - parameter int VCDepth = 3, - parameter int DeeperVCId = 0, - parameter int DeeperVCDepth = 2 + /// Types of the flit, header and payload + parameter type flit_t = logic, + parameter type hdr_t = logic, + parameter type payload_t = logic, + /// Number of virtual channels + parameter int unsigned NumVC = 32'd0, + /// Width of the VC index + parameter int unsigned VCIdxWidth = 32'd0, + /// Depth of the VC FIFOs + parameter int unsigned VCDepth = 32'd0, + /// Deeper FIFO for a specific VC + parameter int unsigned DeeperVCId = 32'd0, + /// Depth of the deeper FIFO + parameter int unsigned DeeperVCDepth = 32'd0 ) ( input logic clk_i, input logic rst_ni, - // input from other router or local port - output logic credit_v_o, - output logic [NumVCWidth-1:0] credit_id_o, - input logic data_v_i, - input flit_t data_i, - - output logic [NumVC-1:0] vc_ctrl_head_v_o, - output hdr_t [NumVC-1:0] vc_ctrl_head_o, - output flit_payload_t [NumVC-1:0] vc_data_head_o, - + /// input from other router or local port + output logic credit_valid_o, + output logic [VCIdxWidth-1:0] credit_id_o, + input logic data_valid_i, + input flit_t data_i, + /// output to router + output logic [NumVC-1:0] vc_hdr_valid_o, + output hdr_t [NumVC-1:0] vc_hdr_o, + output payload_t [NumVC-1:0] vc_data_o, // input pop flit ctrl fifo (comes from SA stage) - input logic read_enable_sa_stage_i, - input logic [NumVC-1:0] read_vc_id_oh_sa_stage_i, - + input logic read_enable_sa_stage_i, + input logic [NumVC-1:0] read_vc_id_oh_sa_stage_i, // input pop flit ctrl fifo (comes from ST stage) - input logic read_enable_st_stage_i, - input logic [NumVC-1:0] read_vc_id_oh_st_stage_i + input logic read_enable_st_stage_i, + input logic [NumVC-1:0] read_vc_id_oh_st_stage_i ); -logic [NumVC-1:0] data_v_i_oh; -logic [NumVC-1:0] remove_ctrl_head; -logic [NumVC-1:0] remove_data_head; +logic [NumVC-1:0] data_valid_i_oh; +logic [NumVC-1:0] remove_hdr; +logic [NumVC-1:0] remove_data; -// where to add data +// One-hot encoding of valid data always_comb begin - data_v_i_oh = '0; - if(data_v_i) begin - data_v_i_oh[data_i.hdr.vc_id[NumVCWidth-1:0]] = 1'b1; + data_valid_i_oh = '0; + if(data_valid_i) begin + data_valid_i_oh[data_i.hdr.vc_id[VCIdxWidth-1:0]] = 1'b1; end end -// when to remove from fifo +// When to remove from fifo always_comb begin - // remove ctrl at SA stage - remove_ctrl_head = '0; - if(read_enable_sa_stage_i) - remove_ctrl_head = read_vc_id_oh_sa_stage_i; - // remove data at ST stage - remove_data_head = '0; - if(read_enable_st_stage_i) - remove_data_head = read_vc_id_oh_st_stage_i; + // Remove ctrl at SA stage + remove_hdr = '0; + if(read_enable_sa_stage_i) begin + remove_hdr = read_vc_id_oh_sa_stage_i; + end + // Remove data at ST stage + remove_data = '0; + if(read_enable_st_stage_i) begin + remove_data = read_vc_id_oh_st_stage_i; + end end -// data fifo -> hdr is always before payload in flits -for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_data_fifos +// Data Fifo +for(genvar vc = 0; vc < NumVC; vc++) begin: gen_data_fifos + localparam int unsigned Depth = (vc == DeeperVCId) ? DeeperVCDepth : VCDepth; floo_input_fifo #( - .Depth (v_chan == DeeperVCId ? DeeperVCDepth : VCDepth), - .type_t (flit_payload_t) + .Depth ( Depth ), + .type_t ( payload_t ) ) i_data_fifo ( .clk_i, .rst_ni, - .data_i (data_i [DataLength-1:0]), - .valid_i (data_v_i_oh [v_chan]), - .data_o (vc_data_head_o [v_chan]), - .valid_o (), - .ready_i (remove_data_head [v_chan]) + .data_i ( data_i.payload ), + .valid_i ( data_valid_i_oh[vc] ), + .data_o ( vc_data_o [vc] ), + .valid_o ( ), + .ready_i ( remove_data[vc] ) ); -end -// ctrl fifo -> hdr is always before payload in flits -for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_ctrl_fifos floo_input_fifo #( - .Depth (v_chan == DeeperVCId ? DeeperVCDepth : VCDepth), - .type_t (hdr_t) - ) i_data_fifo ( - .clk_i, - .rst_ni, - .data_i (data_i [DataLength+HdrLength-1:DataLength]), - .valid_i (data_v_i_oh [v_chan]), - .data_o (vc_ctrl_head_o [v_chan]), - .valid_o (vc_ctrl_head_v_o [v_chan]), - .ready_i (remove_ctrl_head [v_chan]) - ); + .Depth ( Depth ), + .type_t ( hdr_t ) + ) i_hdr_fifo ( + .clk_i, + .rst_ni, + .data_i ( data_i.hdr ), + .valid_i ( data_valid_i_oh[vc] ), + .data_o ( vc_hdr_o[vc] ), + .valid_o ( vc_hdr_valid_o[vc] ), + .ready_i ( remove_hdr [vc] ) + ); end -assign credit_v_o = read_enable_st_stage_i; //could also be from sa stage -logic [NumVCWidth-1:0][NumVC-1:0] id_mask; +logic [VCIdxWidth-1:0][NumVC-1:0] id_mask; + +// Could also be from sa stage +assign credit_valid_o = read_enable_st_stage_i; -//extract credit_id from onehot: create id mask -for(genvar i = 0; i < NumVCWidth; i++) begin : gen_id_mask_NumVCWidth +// Extract `credit_id` from onehot: create id mask +for(genvar i = 0; i < VCIdxWidth; i++) begin : gen_id_mask_NumVCWidth for(genvar j = 0; j < NumVC; j++) begin : gen_id_mask_NumVC assign id_mask[i][j] = (j/(2**i)) % 2; end end -//mask looks like this: N_Input = 3: (0,0) is first bit + +// Mask looks like this: N_Input = 3: (0,0) is first bit // 0 0 0 // 1 0 0 // 0 1 0 // 1 1 0 // 0 0 1 // 1 0 1 // 0 1 1 // 1 1 1 -// use mask to get credit_id -for(genvar i = 0; i < NumVCWidth; i++) begin : gen_get_credit_id +// Use mask to get credit_id +for(genvar i = 0; i < VCIdxWidth; i++) begin : gen_get_credit_id assign credit_id_o[i] = |(read_vc_id_oh_st_stage_i & id_mask[i]); end