From cb417aeda1a7e5ac227194a3b68775d34e6d8b16 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Fri, 31 May 2024 16:18:42 +0200 Subject: [PATCH] floogen(pkg): Refer `rsvd` as `payload` in generic flit types --- floogen/model/link.py | 2 +- hw/floo_axi_pkg.sv | 4 ++-- hw/floo_narrow_wide_pkg.sv | 6 +++--- hw/floo_vc_narrow_wide_chimney.sv | 6 +++--- hw/tb/tb_floo_router.sv | 4 ++-- hw/vc_router_util/floo_vc_router_switch.sv | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/floogen/model/link.py b/floogen/model/link.py index 11026c7a..f0aa1051 100644 --- a/floogen/model/link.py +++ b/floogen/model/link.py @@ -109,7 +109,7 @@ def render_flit(cls, protocols): for phys_ch, size in link_sizes.items(): struct_dict = { "hdr": "hdr_t", - "rsvd": f"logic[{size-1}:0]", + "payload": f"logic[{size-1}:0]", } string += sv_struct_typedef(f"floo_{phys_ch}_generic_flit_t", struct_dict) return string diff --git a/hw/floo_axi_pkg.sv b/hw/floo_axi_pkg.sv index d6d57d6b..2cb18822 100644 --- a/hw/floo_axi_pkg.sv +++ b/hw/floo_axi_pkg.sv @@ -139,12 +139,12 @@ package floo_axi_pkg; typedef struct packed { hdr_t hdr; - logic [73:0] rsvd; + logic [73:0] payload; } floo_req_generic_flit_t; typedef struct packed { hdr_t hdr; - logic [70:0] rsvd; + logic [70:0] payload; } floo_rsp_generic_flit_t; diff --git a/hw/floo_narrow_wide_pkg.sv b/hw/floo_narrow_wide_pkg.sv index d15f9792..a3f363a3 100644 --- a/hw/floo_narrow_wide_pkg.sv +++ b/hw/floo_narrow_wide_pkg.sv @@ -206,17 +206,17 @@ package floo_narrow_wide_pkg; typedef struct packed { hdr_t hdr; - logic [87:0] rsvd; + logic [87:0] payload; } floo_req_generic_flit_t; typedef struct packed { hdr_t hdr; - logic [71:0] rsvd; + logic [71:0] payload; } floo_rsp_generic_flit_t; typedef struct packed { hdr_t hdr; - logic [577:0] rsvd; + logic [577:0] payload; } floo_wide_generic_flit_t; diff --git a/hw/floo_vc_narrow_wide_chimney.sv b/hw/floo_vc_narrow_wide_chimney.sv index bb62bd2b..b4253b40 100644 --- a/hw/floo_vc_narrow_wide_chimney.sv +++ b/hw/floo_vc_narrow_wide_chimney.sv @@ -928,7 +928,7 @@ module floo_vc_narrow_wide_chimney .valid_i ( floo_req_arb_req_in ), .data_i ( floo_req_arb_in ), .ready_o ( floo_req_arb_gnt_out ), - .data_o ( {floo_req_arb_sel_hdr, floo_req_o.req.generic.rsvd}), + .data_o ( {floo_req_arb_sel_hdr, floo_req_o.req.generic.payload}), .ready_i ( floo_req_o.valid ), .valid_o ( floo_req_arb_v ) ); @@ -942,7 +942,7 @@ module floo_vc_narrow_wide_chimney .valid_i ( floo_rsp_arb_req_in ), .data_i ( floo_rsp_arb_in ), .ready_o ( floo_rsp_arb_gnt_out ), - .data_o ( {floo_rsp_arb_sel_hdr,floo_rsp_o.rsp.generic.rsvd}), + .data_o ( {floo_rsp_arb_sel_hdr,floo_rsp_o.rsp.generic.payload}), .ready_i ( floo_rsp_o.valid ), .valid_o ( floo_rsp_arb_v ) ); @@ -956,7 +956,7 @@ module floo_vc_narrow_wide_chimney .valid_i ( floo_wide_arb_req_in ), .data_i ( floo_wide_arb_in ), .ready_o ( floo_wide_arb_gnt_out ), - .data_o ( {floo_wide_arb_sel_hdr, floo_wide_o.wide.generic.rsvd}), + .data_o ( {floo_wide_arb_sel_hdr, floo_wide_o.wide.generic.payload}), .ready_i ( floo_wide_o.valid ), .valid_o ( floo_wide_arb_v ) ); diff --git a/hw/tb/tb_floo_router.sv b/hw/tb/tb_floo_router.sv index 8c8f219d..61ac20f2 100644 --- a/hw/tb/tb_floo_router.sv +++ b/hw/tb/tb_floo_router.sv @@ -116,7 +116,7 @@ module tb_floo_router; rand_data.data_mod_id_c.constraint_mode(1); if (rand_data.randomize()) begin automatic floo_req_generic_flit_t next_flit = '0; - next_flit.rsvd = rand_data.data; + next_flit.payload = rand_data.data; next_flit.hdr.src_id = port; next_flit.hdr.dst_id = stimuli.id; next_flit.hdr.last = j == stimuli.len-1; @@ -343,7 +343,7 @@ module tb_floo_router; golden = golden_queue[result.hdr.src_id][virt_channel][port].pop_front(); end - if (result.rsvd != golden.rsvd) begin + if (result.payload != golden.payload) begin $error("ERROR! Mismatch for port %d channel %d (from %d, target port %d)", port, virt_channel, result.hdr.src_id, result.hdr.dst_id); end diff --git a/hw/vc_router_util/floo_vc_router_switch.sv b/hw/vc_router_util/floo_vc_router_switch.sv index eb27f722..781fa0fc 100644 --- a/hw/vc_router_util/floo_vc_router_switch.sv +++ b/hw/vc_router_util/floo_vc_router_switch.sv @@ -51,7 +51,7 @@ if(RouteAlgo != XYRouting) begin : gen_switch_not_XY_routing_optimized // dont need to check bits on diagonal if(out_port != in_port) begin : gen_nXYopt_out_neq_in if(inport_id_oh_per_output_i[out_port][in_port]) begin : gen_nXYopt_found_match - data_o[out_port].rsvd = data_head_per_inport[in_port]; + data_o[out_port].payload = data_head_per_inport[in_port]; data_o[out_port].hdr.rob_req = ctrl_head_per_inport_i[in_port].rob_req; data_o[out_port].hdr.rob_idx = ctrl_head_per_inport_i[in_port].rob_idx; data_o[out_port].hdr.dst_id = ctrl_head_per_inport_i[in_port].dst_id; @@ -78,7 +78,7 @@ end else begin : gen_switch_XY_routing_optimized (out_port == West && (in_port == South || in_port == North)) )) begin : gen_XYopt_possible_connection if(inport_id_oh_per_output_i[out_port][in_port]) begin : gen_nXYopt_found_match - data_o[out_port].rsvd = data_head_per_inport[in_port]; + data_o[out_port].payload = data_head_per_inport[in_port]; data_o[out_port].hdr.rob_req = ctrl_head_per_inport_i[in_port].rob_req; data_o[out_port].hdr.rob_idx = ctrl_head_per_inport_i[in_port].rob_idx; data_o[out_port].hdr.dst_id = ctrl_head_per_inport_i[in_port].dst_id;